1 /* 2 * GXBB clock tree IDs 3 */ 4 5 #ifndef __GXBB_CLKC_H 6 #define __GXBB_CLKC_H 7 8 #define CLKID_CPUCLK 1 9 #define CLKID_HDMI_PLL 2 10 #define CLKID_FCLK_DIV2 4 11 #define CLKID_FCLK_DIV3 5 12 #define CLKID_FCLK_DIV4 6 13 #define CLKID_GP0_PLL 9 14 #define CLKID_CLK81 12 15 #define CLKID_MPLL2 15 16 #define CLKID_I2C 22 17 #define CLKID_SAR_ADC 23 18 #define CLKID_RNG0 25 19 #define CLKID_SPI 34 20 #define CLKID_ETH 36 21 #define CLKID_AIU_GLUE 38 22 #define CLKID_I2S_OUT 40 23 #define CLKID_MIXER_IFACE 44 24 #define CLKID_AIU 47 25 #define CLKID_USB0 50 26 #define CLKID_USB1 51 27 #define CLKID_USB 55 28 #define CLKID_HDMI_PCLK 63 29 #define CLKID_USB1_DDR_BRIDGE 64 30 #define CLKID_USB0_DDR_BRIDGE 65 31 #define CLKID_SANA 69 32 #define CLKID_GCLK_VENCI_INT0 77 33 #define CLKID_AOCLK_GATE 80 34 #define CLKID_AO_I2C 93 35 #define CLKID_SD_EMMC_A 94 36 #define CLKID_SD_EMMC_B 95 37 #define CLKID_SD_EMMC_C 96 38 #define CLKID_SAR_ADC_CLK 97 39 #define CLKID_SAR_ADC_SEL 98 40 #define CLKID_MALI_0_SEL 100 41 #define CLKID_MALI_0 102 42 #define CLKID_MALI_1_SEL 103 43 #define CLKID_MALI_1 105 44 #define CLKID_MALI 106 45 46 #endif /* __GXBB_CLKC_H */ 47