1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Rahul Sharma <rahul.sharma@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Provides Constants for Exynos5260 clocks. 10 */ 11 12 #ifndef _DT_BINDINGS_CLK_EXYNOS5260_H 13 #define _DT_BINDINGS_CLK_EXYNOS5260_H 14 15 /* Clock names: <cmu><type><IP> */ 16 17 /* List Of Clocks For CMU_TOP */ 18 19 #define TOP_FOUT_DISP_PLL 1 20 #define TOP_FOUT_AUD_PLL 2 21 #define TOP_MOUT_AUDTOP_PLL_USER 3 22 #define TOP_MOUT_AUD_PLL 4 23 #define TOP_MOUT_DISP_PLL 5 24 #define TOP_MOUT_BUSTOP_PLL_USER 6 25 #define TOP_MOUT_MEMTOP_PLL_USER 7 26 #define TOP_MOUT_MEDIATOP_PLL_USER 8 27 #define TOP_MOUT_DISP_DISP_333 9 28 #define TOP_MOUT_ACLK_DISP_333 10 29 #define TOP_MOUT_DISP_DISP_222 11 30 #define TOP_MOUT_ACLK_DISP_222 12 31 #define TOP_MOUT_DISP_MEDIA_PIXEL 13 32 #define TOP_MOUT_FIMD1 14 33 #define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 34 #define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 35 #define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 36 #define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 37 #define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 38 #define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 39 #define TOP_MOUT_BUS4_BUSTOP_100 21 40 #define TOP_MOUT_BUS4_BUSTOP_400 22 41 #define TOP_MOUT_BUS3_BUSTOP_100 23 42 #define TOP_MOUT_BUS3_BUSTOP_400 24 43 #define TOP_MOUT_BUS2_BUSTOP_400 25 44 #define TOP_MOUT_BUS2_BUSTOP_100 26 45 #define TOP_MOUT_BUS1_BUSTOP_100 27 46 #define TOP_MOUT_BUS1_BUSTOP_400 28 47 #define TOP_MOUT_SCLK_FSYS_USB 29 48 #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 49 #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 50 #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 51 #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 52 #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 53 #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 54 #define TOP_MOUT_ACLK_ISP1_266 36 55 #define TOP_MOUT_ISP1_MEDIA_266 37 56 #define TOP_MOUT_ACLK_ISP1_400 38 57 #define TOP_MOUT_ISP1_MEDIA_400 39 58 #define TOP_MOUT_SCLK_ISP1_SPI0 40 59 #define TOP_MOUT_SCLK_ISP1_SPI1 41 60 #define TOP_MOUT_SCLK_ISP1_UART 42 61 #define TOP_MOUT_SCLK_ISP1_SENSOR2 43 62 #define TOP_MOUT_SCLK_ISP1_SENSOR1 44 63 #define TOP_MOUT_SCLK_ISP1_SENSOR0 45 64 #define TOP_MOUT_ACLK_MFC_333 46 65 #define TOP_MOUT_MFC_BUSTOP_333 47 66 #define TOP_MOUT_ACLK_G2D_333 48 67 #define TOP_MOUT_G2D_BUSTOP_333 49 68 #define TOP_MOUT_ACLK_GSCL_FIMC 50 69 #define TOP_MOUT_GSCL_BUSTOP_FIMC 51 70 #define TOP_MOUT_ACLK_GSCL_333 52 71 #define TOP_MOUT_GSCL_BUSTOP_333 53 72 #define TOP_MOUT_ACLK_GSCL_400 54 73 #define TOP_MOUT_M2M_MEDIATOP_400 55 74 #define TOP_DOUT_ACLK_MFC_333 56 75 #define TOP_DOUT_ACLK_G2D_333 57 76 #define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 77 #define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 78 #define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 79 #define TOP_DOUT_ACLK_GSCL_FIMC 61 80 #define TOP_DOUT_ACLK_GSCL_400 62 81 #define TOP_DOUT_ACLK_GSCL_333 63 82 #define TOP_DOUT_SCLK_ISP1_SPI0_B 64 83 #define TOP_DOUT_SCLK_ISP1_SPI0_A 65 84 #define TOP_DOUT_ACLK_ISP1_400 66 85 #define TOP_DOUT_ACLK_ISP1_266 67 86 #define TOP_DOUT_SCLK_ISP1_UART 68 87 #define TOP_DOUT_SCLK_ISP1_SPI1_B 69 88 #define TOP_DOUT_SCLK_ISP1_SPI1_A 70 89 #define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 90 #define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 91 #define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 92 #define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 93 #define TOP_DOUT_SCLK_DISP_PIXEL 75 94 #define TOP_DOUT_ACLK_DISP_222 76 95 #define TOP_DOUT_ACLK_DISP_333 77 96 #define TOP_DOUT_ACLK_BUS4_100 78 97 #define TOP_DOUT_ACLK_BUS4_400 79 98 #define TOP_DOUT_ACLK_BUS3_100 80 99 #define TOP_DOUT_ACLK_BUS3_400 81 100 #define TOP_DOUT_ACLK_BUS2_100 82 101 #define TOP_DOUT_ACLK_BUS2_400 83 102 #define TOP_DOUT_ACLK_BUS1_100 84 103 #define TOP_DOUT_ACLK_BUS1_400 85 104 #define TOP_DOUT_SCLK_PERI_SPI1_B 86 105 #define TOP_DOUT_SCLK_PERI_SPI1_A 87 106 #define TOP_DOUT_SCLK_PERI_SPI0_B 88 107 #define TOP_DOUT_SCLK_PERI_SPI0_A 89 108 #define TOP_DOUT_SCLK_PERI_UART0 90 109 #define TOP_DOUT_SCLK_PERI_UART2 91 110 #define TOP_DOUT_SCLK_PERI_UART1 92 111 #define TOP_DOUT_SCLK_PERI_SPI2_B 93 112 #define TOP_DOUT_SCLK_PERI_SPI2_A 94 113 #define TOP_DOUT_ACLK_PERI_AUD 95 114 #define TOP_DOUT_ACLK_PERI_66 96 115 #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 116 #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 117 #define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 118 #define TOP_DOUT_ACLK_FSYS_200 100 119 #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 120 #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 121 #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 122 #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 123 #define TOP_SCLK_FIMD1 105 124 #define TOP_SCLK_MMC2 106 125 #define TOP_SCLK_MMC1 107 126 #define TOP_SCLK_MMC0 108 127 #define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 128 #define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 129 #define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 130 #define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 131 #define phyclk_hdmi_phy_tmds_clko 113 132 #define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 133 #define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 134 #define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 135 #define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 136 #define PHYCLK_DPTX_PHY_CLK_DIV2 118 137 #define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 138 #define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 139 #define PHYCLK_USBHOST20_PHY_FREECLK 121 140 #define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 141 #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 142 #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 143 #define TOP_NR_CLK 125 144 145 146 /* List Of Clocks For CMU_EGL */ 147 148 #define EGL_FOUT_EGL_PLL 1 149 #define EGL_FOUT_EGL_DPLL 2 150 #define EGL_MOUT_EGL_B 3 151 #define EGL_MOUT_EGL_PLL 4 152 #define EGL_DOUT_EGL_PLL 5 153 #define EGL_DOUT_EGL_PCLK_DBG 6 154 #define EGL_DOUT_EGL_ATCLK 7 155 #define EGL_DOUT_PCLK_EGL 8 156 #define EGL_DOUT_ACLK_EGL 9 157 #define EGL_DOUT_EGL2 10 158 #define EGL_DOUT_EGL1 11 159 #define EGL_NR_CLK 12 160 161 162 /* List Of Clocks For CMU_KFC */ 163 164 #define KFC_FOUT_KFC_PLL 1 165 #define KFC_MOUT_KFC_PLL 2 166 #define KFC_MOUT_KFC 3 167 #define KFC_DOUT_KFC_PLL 4 168 #define KFC_DOUT_PCLK_KFC 5 169 #define KFC_DOUT_ACLK_KFC 6 170 #define KFC_DOUT_KFC_PCLK_DBG 7 171 #define KFC_DOUT_KFC_ATCLK 8 172 #define KFC_DOUT_KFC2 9 173 #define KFC_DOUT_KFC1 10 174 #define KFC_NR_CLK 11 175 176 177 /* List Of Clocks For CMU_MIF */ 178 179 #define MIF_FOUT_MEM_PLL 1 180 #define MIF_FOUT_MEDIA_PLL 2 181 #define MIF_FOUT_BUS_PLL 3 182 #define MIF_MOUT_CLK2X_PHY 4 183 #define MIF_MOUT_MIF_DREX2X 5 184 #define MIF_MOUT_CLKM_PHY 6 185 #define MIF_MOUT_MIF_DREX 7 186 #define MIF_MOUT_MEDIA_PLL 8 187 #define MIF_MOUT_BUS_PLL 9 188 #define MIF_MOUT_MEM_PLL 10 189 #define MIF_DOUT_ACLK_BUS_100 11 190 #define MIF_DOUT_ACLK_BUS_200 12 191 #define MIF_DOUT_ACLK_MIF_466 13 192 #define MIF_DOUT_CLK2X_PHY 14 193 #define MIF_DOUT_CLKM_PHY 15 194 #define MIF_DOUT_BUS_PLL 16 195 #define MIF_DOUT_MEM_PLL 17 196 #define MIF_DOUT_MEDIA_PLL 18 197 #define MIF_CLK_LPDDR3PHY_WRAP1 19 198 #define MIF_CLK_LPDDR3PHY_WRAP0 20 199 #define MIF_CLK_MONOCNT 21 200 #define MIF_CLK_MIF_RTC 22 201 #define MIF_CLK_DREX1 23 202 #define MIF_CLK_DREX0 24 203 #define MIF_CLK_INTMEM 25 204 #define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 205 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 206 #define MIF_NR_CLK 28 207 208 209 /* List Of Clocks For CMU_G3D */ 210 211 #define G3D_FOUT_G3D_PLL 1 212 #define G3D_MOUT_G3D_PLL 2 213 #define G3D_DOUT_PCLK_G3D 3 214 #define G3D_DOUT_ACLK_G3D 4 215 #define G3D_CLK_G3D_HPM 5 216 #define G3D_CLK_G3D 6 217 #define G3D_NR_CLK 7 218 219 220 /* List Of Clocks For CMU_AUD */ 221 222 #define AUD_MOUT_SCLK_AUD_PCM 1 223 #define AUD_MOUT_SCLK_AUD_I2S 2 224 #define AUD_MOUT_AUD_PLL_USER 3 225 #define AUD_DOUT_ACLK_AUD_131 4 226 #define AUD_DOUT_SCLK_AUD_UART 5 227 #define AUD_DOUT_SCLK_AUD_PCM 6 228 #define AUD_DOUT_SCLK_AUD_I2S 7 229 #define AUD_CLK_AUD_UART 8 230 #define AUD_CLK_PCM 9 231 #define AUD_CLK_I2S 10 232 #define AUD_CLK_DMAC 11 233 #define AUD_CLK_SRAMC 12 234 #define AUD_SCLK_AUD_UART 13 235 #define AUD_SCLK_PCM 14 236 #define AUD_SCLK_I2S 15 237 #define AUD_NR_CLK 16 238 239 240 /* List Of Clocks For CMU_MFC */ 241 242 #define MFC_MOUT_ACLK_MFC_333_USER 1 243 #define MFC_DOUT_PCLK_MFC_83 2 244 #define MFC_CLK_MFC 3 245 #define MFC_CLK_SMMU2_MFCM1 4 246 #define MFC_CLK_SMMU2_MFCM0 5 247 #define MFC_NR_CLK 6 248 249 250 /* List Of Clocks For CMU_GSCL */ 251 252 #define GSCL_MOUT_ACLK_CSIS 1 253 #define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 254 #define GSCL_MOUT_ACLK_M2M_400_USER 3 255 #define GSCL_MOUT_ACLK_GSCL_333_USER 4 256 #define GSCL_DOUT_ACLK_CSIS_200 5 257 #define GSCL_DOUT_PCLK_M2M_100 6 258 #define GSCL_CLK_PIXEL_GSCL1 7 259 #define GSCL_CLK_PIXEL_GSCL0 8 260 #define GSCL_CLK_MSCL1 9 261 #define GSCL_CLK_MSCL0 10 262 #define GSCL_CLK_GSCL1 11 263 #define GSCL_CLK_GSCL0 12 264 #define GSCL_CLK_FIMC_LITE_D 13 265 #define GSCL_CLK_FIMC_LITE_B 14 266 #define GSCL_CLK_FIMC_LITE_A 15 267 #define GSCL_CLK_CSIS1 16 268 #define GSCL_CLK_CSIS0 17 269 #define GSCL_CLK_SMMU3_LITE_D 18 270 #define GSCL_CLK_SMMU3_LITE_B 19 271 #define GSCL_CLK_SMMU3_LITE_A 20 272 #define GSCL_CLK_SMMU3_GSCL0 21 273 #define GSCL_CLK_SMMU3_GSCL1 22 274 #define GSCL_CLK_SMMU3_MSCL0 23 275 #define GSCL_CLK_SMMU3_MSCL1 24 276 #define GSCL_SCLK_CSIS1_WRAP 25 277 #define GSCL_SCLK_CSIS0_WRAP 26 278 #define GSCL_NR_CLK 27 279 280 281 /* List Of Clocks For CMU_FSYS */ 282 283 #define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 284 #define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 285 #define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 286 #define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 287 #define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 288 #define FSYS_CLK_TSI 6 289 #define FSYS_CLK_USBLINK 7 290 #define FSYS_CLK_USBHOST20 8 291 #define FSYS_CLK_USBDRD30 9 292 #define FSYS_CLK_SROMC 10 293 #define FSYS_CLK_PDMA 11 294 #define FSYS_CLK_MMC2 12 295 #define FSYS_CLK_MMC1 13 296 #define FSYS_CLK_MMC0 14 297 #define FSYS_CLK_RTIC 15 298 #define FSYS_CLK_SMMU_RTIC 16 299 #define FSYS_PHYCLK_USBDRD30 17 300 #define FSYS_PHYCLK_USBHOST20 18 301 #define FSYS_NR_CLK 19 302 303 304 /* List Of Clocks For CMU_PERI */ 305 306 #define PERI_MOUT_SCLK_SPDIF 1 307 #define PERI_MOUT_SCLK_I2SCOD 2 308 #define PERI_MOUT_SCLK_PCM 3 309 #define PERI_DOUT_I2S 4 310 #define PERI_DOUT_PCM 5 311 #define PERI_CLK_WDT_KFC 6 312 #define PERI_CLK_WDT_EGL 7 313 #define PERI_CLK_HSIC3 8 314 #define PERI_CLK_HSIC2 9 315 #define PERI_CLK_HSIC1 10 316 #define PERI_CLK_HSIC0 11 317 #define PERI_CLK_PCM 12 318 #define PERI_CLK_MCT 13 319 #define PERI_CLK_I2S 14 320 #define PERI_CLK_I2CHDMI 15 321 #define PERI_CLK_I2C7 16 322 #define PERI_CLK_I2C6 17 323 #define PERI_CLK_I2C5 18 324 #define PERI_CLK_I2C4 19 325 #define PERI_CLK_I2C9 20 326 #define PERI_CLK_I2C8 21 327 #define PERI_CLK_I2C11 22 328 #define PERI_CLK_I2C10 23 329 #define PERI_CLK_HDMICEC 24 330 #define PERI_CLK_EFUSE_WRITER 25 331 #define PERI_CLK_ABB 26 332 #define PERI_CLK_UART2 27 333 #define PERI_CLK_UART1 28 334 #define PERI_CLK_UART0 29 335 #define PERI_CLK_ADC 30 336 #define PERI_CLK_TMU4 31 337 #define PERI_CLK_TMU3 32 338 #define PERI_CLK_TMU2 33 339 #define PERI_CLK_TMU1 34 340 #define PERI_CLK_TMU0 35 341 #define PERI_CLK_SPI2 36 342 #define PERI_CLK_SPI1 37 343 #define PERI_CLK_SPI0 38 344 #define PERI_CLK_SPDIF 39 345 #define PERI_CLK_PWM 40 346 #define PERI_CLK_UART4 41 347 #define PERI_CLK_CHIPID 42 348 #define PERI_CLK_PROVKEY0 43 349 #define PERI_CLK_PROVKEY1 44 350 #define PERI_CLK_SECKEY 45 351 #define PERI_CLK_TOP_RTC 46 352 #define PERI_CLK_TZPC10 47 353 #define PERI_CLK_TZPC9 48 354 #define PERI_CLK_TZPC8 49 355 #define PERI_CLK_TZPC7 50 356 #define PERI_CLK_TZPC6 51 357 #define PERI_CLK_TZPC5 52 358 #define PERI_CLK_TZPC4 53 359 #define PERI_CLK_TZPC3 54 360 #define PERI_CLK_TZPC2 55 361 #define PERI_CLK_TZPC1 56 362 #define PERI_CLK_TZPC0 57 363 #define PERI_SCLK_UART2 58 364 #define PERI_SCLK_UART1 59 365 #define PERI_SCLK_UART0 60 366 #define PERI_SCLK_SPI2 61 367 #define PERI_SCLK_SPI1 62 368 #define PERI_SCLK_SPI0 63 369 #define PERI_SCLK_SPDIF 64 370 #define PERI_SCLK_I2S 65 371 #define PERI_SCLK_PCM1 66 372 #define PERI_NR_CLK 67 373 374 375 /* List Of Clocks For CMU_DISP */ 376 377 #define DISP_MOUT_SCLK_HDMI_SPDIF 1 378 #define DISP_MOUT_SCLK_HDMI_PIXEL 2 379 #define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 380 #define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 381 #define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 382 #define DISP_MOUT_HDMI_PHY_PIXEL 6 383 #define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 384 #define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 385 #define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 386 #define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 387 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 388 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 389 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 390 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 391 #define DISP_MOUT_ACLK_DISP_222_USER 15 392 #define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 393 #define DISP_MOUT_ACLK_DISP_333_USER 17 394 #define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 395 #define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 396 #define DISP_DOUT_PCLK_DISP_111 20 397 #define DISP_CLK_SMMU_TV 21 398 #define DISP_CLK_SMMU_FIMD1M1 22 399 #define DISP_CLK_SMMU_FIMD1M0 23 400 #define DISP_CLK_PIXEL_MIXER 24 401 #define DISP_CLK_PIXEL_DISP 25 402 #define DISP_CLK_MIXER 26 403 #define DISP_CLK_MIPIPHY 27 404 #define DISP_CLK_HDMIPHY 28 405 #define DISP_CLK_HDMI 29 406 #define DISP_CLK_FIMD1 30 407 #define DISP_CLK_DSIM1 31 408 #define DISP_CLK_DPPHY 32 409 #define DISP_CLK_DP 33 410 #define DISP_SCLK_PIXEL 34 411 #define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 412 #define DISP_NR_CLK 36 413 414 415 /* List Of Clocks For CMU_G2D */ 416 417 #define G2D_MOUT_ACLK_G2D_333_USER 1 418 #define G2D_DOUT_PCLK_G2D_83 2 419 #define G2D_CLK_SMMU3_JPEG 3 420 #define G2D_CLK_MDMA 4 421 #define G2D_CLK_JPEG 5 422 #define G2D_CLK_G2D 6 423 #define G2D_CLK_SSS 7 424 #define G2D_CLK_SLIM_SSS 8 425 #define G2D_CLK_SMMU_SLIM_SSS 9 426 #define G2D_CLK_SMMU_SSS 10 427 #define G2D_CLK_SMMU_MDMA 11 428 #define G2D_CLK_SMMU3_G2D 12 429 #define G2D_NR_CLK 13 430 431 432 /* List Of Clocks For CMU_ISP */ 433 434 #define ISP_MOUT_ISP_400_USER 1 435 #define ISP_MOUT_ISP_266_USER 2 436 #define ISP_DOUT_SCLK_MPWM 3 437 #define ISP_DOUT_CA5_PCLKDBG 4 438 #define ISP_DOUT_CA5_ATCLKIN 5 439 #define ISP_DOUT_PCLK_ISP_133 6 440 #define ISP_DOUT_PCLK_ISP_66 7 441 #define ISP_CLK_GIC 8 442 #define ISP_CLK_WDT 9 443 #define ISP_CLK_UART 10 444 #define ISP_CLK_SPI1 11 445 #define ISP_CLK_SPI0 12 446 #define ISP_CLK_SMMU_SCALERP 13 447 #define ISP_CLK_SMMU_SCALERC 14 448 #define ISP_CLK_SMMU_ISPCX 15 449 #define ISP_CLK_SMMU_ISP 16 450 #define ISP_CLK_SMMU_FD 17 451 #define ISP_CLK_SMMU_DRC 18 452 #define ISP_CLK_PWM 19 453 #define ISP_CLK_MTCADC 20 454 #define ISP_CLK_MPWM 21 455 #define ISP_CLK_MCUCTL 22 456 #define ISP_CLK_I2C1 23 457 #define ISP_CLK_I2C0 24 458 #define ISP_CLK_FIMC_SCALERP 25 459 #define ISP_CLK_FIMC_SCALERC 26 460 #define ISP_CLK_FIMC 27 461 #define ISP_CLK_FIMC_FD 28 462 #define ISP_CLK_FIMC_DRC 29 463 #define ISP_CLK_CA5 30 464 #define ISP_SCLK_SPI0_EXT 31 465 #define ISP_SCLK_SPI1_EXT 32 466 #define ISP_SCLK_UART_EXT 33 467 #define ISP_NR_CLK 34 468 469 #endif 470