1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Tomasz Figa <t.figa@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Device Tree binding constants for Samsung Exynos3250 clock controllers. 10 */ 11 12 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 13 #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 14 15 /* 16 * Let each exported clock get a unique index, which is used on DT-enabled 17 * platforms to lookup the clock from a clock specifier. These indices are 18 * therefore considered an ABI and so must not be changed. This implies 19 * that new clocks should be added either in free spaces between clock groups 20 * or at the end. 21 */ 22 23 24 /* 25 * Main CMU 26 */ 27 28 #define CLK_OSCSEL 1 29 #define CLK_FIN_PLL 2 30 #define CLK_FOUT_APLL 3 31 #define CLK_FOUT_VPLL 4 32 #define CLK_FOUT_UPLL 5 33 #define CLK_FOUT_MPLL 6 34 #define CLK_ARM_CLK 7 35 36 /* Muxes */ 37 #define CLK_MOUT_MPLL_USER_L 16 38 #define CLK_MOUT_GDL 17 39 #define CLK_MOUT_MPLL_USER_R 18 40 #define CLK_MOUT_GDR 19 41 #define CLK_MOUT_EBI 20 42 #define CLK_MOUT_ACLK_200 21 43 #define CLK_MOUT_ACLK_160 22 44 #define CLK_MOUT_ACLK_100 23 45 #define CLK_MOUT_ACLK_266_1 24 46 #define CLK_MOUT_ACLK_266_0 25 47 #define CLK_MOUT_ACLK_266 26 48 #define CLK_MOUT_VPLL 27 49 #define CLK_MOUT_EPLL_USER 28 50 #define CLK_MOUT_EBI_1 29 51 #define CLK_MOUT_UPLL 30 52 #define CLK_MOUT_ACLK_400_MCUISP_SUB 31 53 #define CLK_MOUT_MPLL 32 54 #define CLK_MOUT_ACLK_400_MCUISP 33 55 #define CLK_MOUT_VPLLSRC 34 56 #define CLK_MOUT_CAM1 35 57 #define CLK_MOUT_CAM_BLK 36 58 #define CLK_MOUT_MFC 37 59 #define CLK_MOUT_MFC_1 38 60 #define CLK_MOUT_MFC_0 39 61 #define CLK_MOUT_G3D 40 62 #define CLK_MOUT_G3D_1 41 63 #define CLK_MOUT_G3D_0 42 64 #define CLK_MOUT_MIPI0 43 65 #define CLK_MOUT_FIMD0 44 66 #define CLK_MOUT_UART_ISP 45 67 #define CLK_MOUT_SPI1_ISP 46 68 #define CLK_MOUT_SPI0_ISP 47 69 #define CLK_MOUT_TSADC 48 70 #define CLK_MOUT_MMC1 49 71 #define CLK_MOUT_MMC0 50 72 #define CLK_MOUT_UART1 51 73 #define CLK_MOUT_UART0 52 74 #define CLK_MOUT_SPI1 53 75 #define CLK_MOUT_SPI0 54 76 #define CLK_MOUT_AUDIO 55 77 #define CLK_MOUT_MPLL_USER_C 56 78 #define CLK_MOUT_HPM 57 79 #define CLK_MOUT_CORE 58 80 #define CLK_MOUT_APLL 59 81 #define CLK_MOUT_ACLK_266_SUB 60 82 83 /* Dividers */ 84 #define CLK_DIV_GPL 64 85 #define CLK_DIV_GDL 65 86 #define CLK_DIV_GPR 66 87 #define CLK_DIV_GDR 67 88 #define CLK_DIV_MPLL_PRE 68 89 #define CLK_DIV_ACLK_400_MCUISP 69 90 #define CLK_DIV_EBI 70 91 #define CLK_DIV_ACLK_200 71 92 #define CLK_DIV_ACLK_160 72 93 #define CLK_DIV_ACLK_100 73 94 #define CLK_DIV_ACLK_266 74 95 #define CLK_DIV_CAM1 75 96 #define CLK_DIV_CAM_BLK 76 97 #define CLK_DIV_MFC 77 98 #define CLK_DIV_G3D 78 99 #define CLK_DIV_MIPI0_PRE 79 100 #define CLK_DIV_MIPI0 80 101 #define CLK_DIV_FIMD0 81 102 #define CLK_DIV_UART_ISP 82 103 #define CLK_DIV_SPI1_ISP_PRE 83 104 #define CLK_DIV_SPI1_ISP 84 105 #define CLK_DIV_SPI0_ISP_PRE 85 106 #define CLK_DIV_SPI0_ISP 86 107 #define CLK_DIV_TSADC_PRE 87 108 #define CLK_DIV_TSADC 88 109 #define CLK_DIV_MMC1_PRE 89 110 #define CLK_DIV_MMC1 90 111 #define CLK_DIV_MMC0_PRE 91 112 #define CLK_DIV_MMC0 92 113 #define CLK_DIV_UART1 93 114 #define CLK_DIV_UART0 94 115 #define CLK_DIV_SPI1_PRE 95 116 #define CLK_DIV_SPI1 96 117 #define CLK_DIV_SPI0_PRE 97 118 #define CLK_DIV_SPI0 98 119 #define CLK_DIV_PCM 99 120 #define CLK_DIV_AUDIO 100 121 #define CLK_DIV_I2S 101 122 #define CLK_DIV_CORE2 102 123 #define CLK_DIV_APLL 103 124 #define CLK_DIV_PCLK_DBG 104 125 #define CLK_DIV_ATB 105 126 #define CLK_DIV_COREM 106 127 #define CLK_DIV_CORE 107 128 #define CLK_DIV_HPM 108 129 #define CLK_DIV_COPY 109 130 131 /* Gates */ 132 #define CLK_ASYNC_G3D 128 133 #define CLK_ASYNC_MFCL 129 134 #define CLK_PPMULEFT 130 135 #define CLK_GPIO_LEFT 131 136 #define CLK_ASYNC_ISPMX 132 137 #define CLK_ASYNC_FSYSD 133 138 #define CLK_ASYNC_LCD0X 134 139 #define CLK_ASYNC_CAMX 135 140 #define CLK_PPMURIGHT 136 141 #define CLK_GPIO_RIGHT 137 142 #define CLK_MONOCNT 138 143 #define CLK_TZPC6 139 144 #define CLK_PROVISIONKEY1 140 145 #define CLK_PROVISIONKEY0 141 146 #define CLK_CMU_ISPPART 142 147 #define CLK_TMU_APBIF 143 148 #define CLK_KEYIF 144 149 #define CLK_RTC 145 150 #define CLK_WDT 146 151 #define CLK_MCT 147 152 #define CLK_SECKEY 148 153 #define CLK_TZPC5 149 154 #define CLK_TZPC4 150 155 #define CLK_TZPC3 151 156 #define CLK_TZPC2 152 157 #define CLK_TZPC1 153 158 #define CLK_TZPC0 154 159 #define CLK_CMU_COREPART 155 160 #define CLK_CMU_TOPPART 156 161 #define CLK_PMU_APBIF 157 162 #define CLK_SYSREG 158 163 #define CLK_CHIP_ID 159 164 #define CLK_QEJPEG 160 165 #define CLK_PIXELASYNCM1 161 166 #define CLK_PIXELASYNCM0 162 167 #define CLK_PPMUCAMIF 163 168 #define CLK_QEM2MSCALER 164 169 #define CLK_QEGSCALER1 165 170 #define CLK_QEGSCALER0 166 171 #define CLK_SMMUJPEG 167 172 #define CLK_SMMUM2M2SCALER 168 173 #define CLK_SMMUGSCALER1 169 174 #define CLK_SMMUGSCALER0 170 175 #define CLK_JPEG 171 176 #define CLK_M2MSCALER 172 177 #define CLK_GSCALER1 173 178 #define CLK_GSCALER0 174 179 #define CLK_QEMFC 175 180 #define CLK_PPMUMFC_L 176 181 #define CLK_SMMUMFC_L 177 182 #define CLK_MFC 178 183 #define CLK_SMMUG3D 179 184 #define CLK_QEG3D 180 185 #define CLK_PPMUG3D 181 186 #define CLK_G3D 182 187 #define CLK_QE_CH1_LCD 183 188 #define CLK_QE_CH0_LCD 184 189 #define CLK_PPMULCD0 185 190 #define CLK_SMMUFIMD0 186 191 #define CLK_DSIM0 187 192 #define CLK_FIMD0 188 193 #define CLK_CAM1 189 194 #define CLK_UART_ISP_TOP 190 195 #define CLK_SPI1_ISP_TOP 191 196 #define CLK_SPI0_ISP_TOP 192 197 #define CLK_TSADC 193 198 #define CLK_PPMUFILE 194 199 #define CLK_USBOTG 195 200 #define CLK_USBHOST 196 201 #define CLK_SROMC 197 202 #define CLK_SDMMC1 198 203 #define CLK_SDMMC0 199 204 #define CLK_PDMA1 200 205 #define CLK_PDMA0 201 206 #define CLK_PWM 202 207 #define CLK_PCM 203 208 #define CLK_I2S 204 209 #define CLK_SPI1 205 210 #define CLK_SPI0 206 211 #define CLK_I2C7 207 212 #define CLK_I2C6 208 213 #define CLK_I2C5 209 214 #define CLK_I2C4 210 215 #define CLK_I2C3 211 216 #define CLK_I2C2 212 217 #define CLK_I2C1 213 218 #define CLK_I2C0 214 219 #define CLK_UART1 215 220 #define CLK_UART0 216 221 #define CLK_BLOCK_LCD 217 222 #define CLK_BLOCK_G3D 218 223 #define CLK_BLOCK_MFC 219 224 #define CLK_BLOCK_CAM 220 225 #define CLK_SMIES 221 226 227 /* Special clocks */ 228 #define CLK_SCLK_JPEG 224 229 #define CLK_SCLK_M2MSCALER 225 230 #define CLK_SCLK_GSCALER1 226 231 #define CLK_SCLK_GSCALER0 227 232 #define CLK_SCLK_MFC 228 233 #define CLK_SCLK_G3D 229 234 #define CLK_SCLK_MIPIDPHY2L 230 235 #define CLK_SCLK_MIPI0 231 236 #define CLK_SCLK_FIMD0 232 237 #define CLK_SCLK_CAM1 233 238 #define CLK_SCLK_UART_ISP 234 239 #define CLK_SCLK_SPI1_ISP 235 240 #define CLK_SCLK_SPI0_ISP 236 241 #define CLK_SCLK_UPLL 237 242 #define CLK_SCLK_TSADC 238 243 #define CLK_SCLK_EBI 239 244 #define CLK_SCLK_MMC1 240 245 #define CLK_SCLK_MMC0 241 246 #define CLK_SCLK_I2S 242 247 #define CLK_SCLK_PCM 243 248 #define CLK_SCLK_SPI1 244 249 #define CLK_SCLK_SPI0 245 250 #define CLK_SCLK_UART1 246 251 #define CLK_SCLK_UART0 247 252 253 /* 254 * Total number of clocks of main CMU. 255 * NOTE: Must be equal to last clock ID increased by one. 256 */ 257 #define CLK_NR_CLKS 248 258 259 /* 260 * CMU DMC 261 */ 262 263 #define CLK_FOUT_BPLL 1 264 #define CLK_FOUT_EPLL 2 265 266 /* Muxes */ 267 #define CLK_MOUT_MPLL_MIF 8 268 #define CLK_MOUT_BPLL 9 269 #define CLK_MOUT_DPHY 10 270 #define CLK_MOUT_DMC_BUS 11 271 #define CLK_MOUT_EPLL 12 272 273 /* Dividers */ 274 #define CLK_DIV_DMC 16 275 #define CLK_DIV_DPHY 17 276 #define CLK_DIV_DMC_PRE 18 277 #define CLK_DIV_DMCP 19 278 #define CLK_DIV_DMCD 20 279 280 /* 281 * Total number of clocks of main CMU. 282 * NOTE: Must be equal to last clock ID increased by one. 283 */ 284 #define NR_CLKS_DMC 21 285 286 /* 287 * CMU ISP 288 */ 289 290 /* Dividers */ 291 292 #define CLK_DIV_ISP1 1 293 #define CLK_DIV_ISP0 2 294 #define CLK_DIV_MCUISP1 3 295 #define CLK_DIV_MCUISP0 4 296 #define CLK_DIV_MPWM 5 297 298 /* Gates */ 299 300 #define CLK_UART_ISP 8 301 #define CLK_WDT_ISP 9 302 #define CLK_PWM_ISP 10 303 #define CLK_I2C1_ISP 11 304 #define CLK_I2C0_ISP 12 305 #define CLK_MPWM_ISP 13 306 #define CLK_MCUCTL_ISP 14 307 #define CLK_PPMUISPX 15 308 #define CLK_PPMUISPMX 16 309 #define CLK_QE_LITE1 17 310 #define CLK_QE_LITE0 18 311 #define CLK_QE_FD 19 312 #define CLK_QE_DRC 20 313 #define CLK_QE_ISP 21 314 #define CLK_CSIS1 22 315 #define CLK_SMMU_LITE1 23 316 #define CLK_SMMU_LITE0 24 317 #define CLK_SMMU_FD 25 318 #define CLK_SMMU_DRC 26 319 #define CLK_SMMU_ISP 27 320 #define CLK_GICISP 28 321 #define CLK_CSIS0 29 322 #define CLK_MCUISP 30 323 #define CLK_LITE1 31 324 #define CLK_LITE0 32 325 #define CLK_FD 33 326 #define CLK_DRC 34 327 #define CLK_ISP 35 328 #define CLK_QE_ISPCX 36 329 #define CLK_QE_SCALERP 37 330 #define CLK_QE_SCALERC 38 331 #define CLK_SMMU_SCALERP 39 332 #define CLK_SMMU_SCALERC 40 333 #define CLK_SCALERP 41 334 #define CLK_SCALERC 42 335 #define CLK_SPI1_ISP 43 336 #define CLK_SPI0_ISP 44 337 #define CLK_SMMU_ISPCX 45 338 #define CLK_ASYNCAXIM 46 339 #define CLK_SCLK_MPWM_ISP 47 340 341 /* 342 * Total number of clocks of CMU_ISP. 343 * NOTE: Must be equal to last clock ID increased by one. 344 */ 345 #define NR_CLKS_ISP 48 346 347 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ 348