1*35af99f7SCaleb James DeLisle /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*35af99f7SCaleb James DeLisle 3*35af99f7SCaleb James DeLisle #ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ 4*35af99f7SCaleb James DeLisle #define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ 5*35af99f7SCaleb James DeLisle 6*35af99f7SCaleb James DeLisle #define EN751221_CLK_PCIE 0 7*35af99f7SCaleb James DeLisle #define EN751221_CLK_SPI 1 8*35af99f7SCaleb James DeLisle #define EN751221_CLK_BUS 2 9*35af99f7SCaleb James DeLisle #define EN751221_CLK_CPU 3 10*35af99f7SCaleb James DeLisle #define EN751221_CLK_GSW 4 11*35af99f7SCaleb James DeLisle 12*35af99f7SCaleb James DeLisle #endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */ 13