xref: /linux/include/dt-bindings/clock/canaan,k230-clk.h (revision 2ed2e359dea752e7758d29a423033031a0b96584)

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Kendryte Canaan K230 Clock Drivers
 *
 * Author: Xukai Wang <kingxukai@zohomail.com>
 */

#ifndef __DT_BINDINGS_CANAAN_K230_CLOCK_H__
#define __DT_BINDINGS_CANAAN_K230_CLOCK_H__

#define K230_CPU0_SRC_GATE			0
#define K230_CPU0_PLIC_GATE			1
#define K230_CPU0_NOC_DDRCP4_GATE		2
#define K230_CPU0_APB_GATE			3
#define K230_CPU0_SRC_RATE			4
#define K230_CPU0_AXI_RATE			5
#define K230_CPU0_PLIC_RATE			6
#define K230_CPU0_APB_RATE			7
#define K230_HS_SSI0_MUX			8
#define K230_HS_USB_REF_MUX			9
#define K230_HS_HCLK_HIGH_GATE			10
#define K230_HS_HCLK_GATE			11
#define K230_HS_SD0_AHB_GATE			12
#define K230_HS_SD1_AHB_GATE			13
#define K230_HS_SSI1_AHB_GATE			14
#define K230_HS_SSI2_AHB_GATE			15
#define K230_HS_USB0_AHB_GATE			16
#define K230_HS_USB1_AHB_GATE			17
#define K230_HS_SSI0_AXI_GATE			18
#define K230_HS_SSI1_GATE			19
#define K230_HS_SSI2_GATE			20
#define K230_HS_QSPI_AXI_SRC_GATE		21
#define K230_HS_SSI1_AXI_GATE			22
#define K230_HS_SSI2_AXI_GATE			23
#define K230_HS_SD_CARD_SRC_GATE		24
#define K230_HS_SD0_CARD_GATE			25
#define K230_HS_SD1_CARD_GATE			26
#define K230_HS_SD_AXI_SRC_GATE			27
#define K230_HS_SD0_AXI_GATE			28
#define K230_HS_SD1_AXI_GATE			29
#define K230_HS_SD0_BASE_GATE			30
#define K230_HS_SD1_BASE_GATE			31
#define K230_HS_SSI0_GATE			32
#define K230_HS_SD_TIMER_SRC_GATE		33
#define K230_HS_SD0_TIMER_GATE			34
#define K230_HS_SD1_TIMER_GATE			35
#define K230_HS_USB0_REF_GATE			36
#define K230_HS_USB1_REF_GATE			37
#define K230_HS_HCLK_HIGH_RATE			38
#define K230_HS_HCLK_RATE			39
#define K230_HS_SSI0_AXI_RATE			40
#define K230_HS_SSI1_RATE			41
#define K230_HS_SSI2_RATE			42
#define K230_HS_QSPI_AXI_SRC_RATE		43
#define K230_HS_SD_CARD_SRC_RATE		44
#define K230_HS_SD_AXI_SRC_RATE			45
#define K230_HS_USB_REF_50M_RATE		46
#define K230_HS_SD_TIMER_SRC_RATE		47
#define K230_TIMER0_MUX				48
#define K230_TIMER1_MUX				49
#define K230_TIMER2_MUX				50
#define K230_TIMER3_MUX				51
#define K230_TIMER4_MUX				52
#define K230_TIMER5_MUX				53
#define K230_SHRM_SRAM_MUX			54
#define K230_DDRC_SRC_MUX			55
#define K230_AI_SRC_MUX				56
#define K230_CAMERA0_MUX			57
#define K230_CAMERA1_MUX			58
#define K230_CAMERA2_MUX			59
#define K230_CPU1_SRC_MUX			60
#define K230_CPU1_SRC_GATE			61
#define K230_CPU1_PLIC_GATE			62
#define K230_CPU1_APB_GATE			63
#define K230_CPU1_SRC_RATE			64
#define K230_CPU1_AXI_RATE			65
#define K230_CPU1_PLIC_RATE			66
#define K230_PMU_APB_GATE			67
#define K230_LS_APB_SRC_GATE			68
#define K230_LS_UART0_APB_GATE			69
#define K230_LS_UART1_APB_GATE			70
#define K230_LS_UART2_APB_GATE			71
#define K230_LS_UART3_APB_GATE			72
#define K230_LS_UART4_APB_GATE			73
#define K230_LS_I2C0_APB_GATE			74
#define K230_LS_I2C1_APB_GATE			75
#define K230_LS_I2C2_APB_GATE			76
#define K230_LS_I2C3_APB_GATE			77
#define K230_LS_I2C4_APB_GATE			78
#define K230_LS_GPIO_APB_GATE			79
#define K230_LS_PWM_APB_GATE			80
#define K230_LS_JAMLINK0_APB_GATE		81
#define K230_LS_JAMLINK1_APB_GATE		82
#define K230_LS_JAMLINK2_APB_GATE		83
#define K230_LS_JAMLINK3_APB_GATE		84
#define K230_LS_AUDIO_APB_GATE			85
#define K230_LS_ADC_APB_GATE			86
#define K230_LS_CODEC_APB_GATE			87
#define K230_LS_I2C0_GATE			88
#define K230_LS_I2C1_GATE			89
#define K230_LS_I2C2_GATE			90
#define K230_LS_I2C3_GATE			91
#define K230_LS_I2C4_GATE			92
#define K230_LS_CODEC_ADC_GATE			93
#define K230_LS_CODEC_DAC_GATE			94
#define K230_LS_AUDIO_DEV_GATE			95
#define K230_LS_PDM_GATE			96
#define K230_LS_ADC_GATE			97
#define K230_LS_UART0_GATE			98
#define K230_LS_UART1_GATE			99
#define K230_LS_UART2_GATE			100
#define K230_LS_UART3_GATE			101
#define K230_LS_UART4_GATE			102
#define K230_LS_JAMLINK0CO_GATE			103
#define K230_LS_JAMLINK1CO_GATE			104
#define K230_LS_JAMLINK2CO_GATE			105
#define K230_LS_JAMLINK3CO_GATE			106
#define K230_LS_GPIO_DEBOUNCE_GATE		107
#define K230_SYSCTL_WDT0_APB_GATE		108
#define K230_SYSCTL_WDT1_APB_GATE		109
#define K230_SYSCTL_TIMER_APB_GATE		110
#define K230_SYSCTL_IOMUX_APB_GATE		111
#define K230_SYSCTL_MAILBOX_APB_GATE		112
#define K230_SYSCTL_HDI_GATE			113
#define K230_SYSCTL_TIME_STAMP_GATE		114
#define K230_SYSCTL_WDT0_GATE			115
#define K230_SYSCTL_WDT1_GATE			116
#define K230_TIMER0_GATE			117
#define K230_TIMER1_GATE			118
#define K230_TIMER2_GATE			119
#define K230_TIMER3_GATE			120
#define K230_TIMER4_GATE			121
#define K230_TIMER5_GATE			122
#define K230_SHRM_APB_GATE			123
#define K230_SHRM_AXI_GATE			124
#define K230_SHRM_AXI_SLAVE_GATE		125
#define K230_SHRM_NONAI2D_AXI_GATE		126
#define K230_SHRM_SRAM_GATE			127
#define K230_SHRM_DECOMPRESS_AXI_GATE		128
#define K230_SHRM_SDMA_AXI_GATE			129
#define K230_SHRM_PDMA_AXI_GATE			130
#define K230_DDRC_SRC_GATE			131
#define K230_DDRC_BYPASS_GATE			132
#define K230_DDRC_APB_GATE			133
#define K230_DISPLAY_AHB_GATE			134
#define K230_DISPLAY_AXI_GATE			135
#define K230_DISPLAY_GPU_GATE			136
#define K230_DISPLAY_DPIP_GATE			137
#define K230_DISPLAY_CFG_GATE			138
#define K230_DISPLAY_REF_GATE			139
#define K230_USB_480M_GATE			140
#define K230_USB_100M_GATE			141
#define K230_DPHY_DFT_GATE			142
#define K230_SPI2AXI_GATE			143
#define K230_AI_SRC_GATE			144
#define K230_AI_AXI_GATE			145
#define K230_AI_SRC_RATE			146
#define K230_CAMERA0_GATE			147
#define K230_CAMERA1_GATE			148
#define K230_CAMERA2_GATE			149
#define K230_LS_APB_SRC_RATE			150
#define K230_LS_I2C0_RATE			151
#define K230_LS_I2C1_RATE			152
#define K230_LS_I2C2_RATE			153
#define K230_LS_I2C3_RATE			154
#define K230_LS_I2C4_RATE			155
#define K230_LS_CODEC_ADC_RATE			156
#define K230_LS_CODEC_DAC_RATE			157
#define K230_LS_AUDIO_DEV_RATE			158
#define K230_LS_PDM_RATE			159
#define K230_LS_ADC_RATE			160
#define K230_LS_UART0_RATE			161
#define K230_LS_UART1_RATE			162
#define K230_LS_UART2_RATE			163
#define K230_LS_UART3_RATE			164
#define K230_LS_UART4_RATE			165
#define K230_LS_JAMLINKCO_SRC_RATE		166
#define K230_LS_GPIO_DEBOUNCE_RATE		167
#define K230_SYSCTL_HDI_RATE			168
#define K230_SYSCTL_TIME_STAMP_RATE		169
#define K230_SYSCTL_TEMP_SENSOR_RATE		170
#define K230_SYSCTL_WDT0_RATE			171
#define K230_SYSCTL_WDT1_RATE			172
#define K230_TIMER0_SRC_RATE			173
#define K230_TIMER1_SRC_RATE			174
#define K230_TIMER2_SRC_RATE			175
#define K230_TIMER3_SRC_RATE			176
#define K230_TIMER4_SRC_RATE			177
#define K230_TIMER5_SRC_RATE			178
#define K230_SHRM_APB_RATE			179
#define K230_DDRC_SRC_RATE			180
#define K230_DDRC_APB_RATE			181
#define K230_DISPLAY_AHB_RATE			182
#define K230_DISPLAY_CLKEXT_RATE		183
#define K230_DISPLAY_GPU_RATE			184
#define K230_DISPLAY_DPIP_RATE			185
#define K230_DISPLAY_CFG_RATE			186
#define K230_VPU_SRC_GATE			187
#define K230_VPU_AXI_GATE			188
#define K230_VPU_DDRCP2_GATE			189
#define K230_VPU_CFG_GATE			190
#define K230_VPU_SRC_RATE			191
#define K230_VPU_AXI_SRC_RATE			192
#define K230_VPU_CFG_RATE			193
#define K230_SEC_APB_GATE			194
#define K230_SEC_FIX_GATE			195
#define K230_SEC_AXI_GATE			196
#define K230_SEC_APB_RATE			197
#define K230_SEC_FIX_RATE			198
#define K230_SEC_AXI_RATE			199
#define K230_USB_480M_RATE			200
#define K230_USB_100M_RATE			201
#define K230_DPHY_DFT_RATE			202
#define K230_SPI2AXI_RATE			203
#define K230_CAMERA0_RATE			204
#define K230_CAMERA1_RATE			205
#define K230_CAMERA2_RATE			206
#define K230_SHRM_SRAM_DIV2			207

#endif /* __DT_BINDINGS_CANAAN_K230_CLOCK_H__ */