1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Meson-AXG clock tree IDs 4 * 5 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 6 */ 7 8 #ifndef __AXG_CLKC_H 9 #define __AXG_CLKC_H 10 11 #define CLKID_SYS_PLL 0 12 #define CLKID_FIXED_PLL 1 13 #define CLKID_FCLK_DIV2 2 14 #define CLKID_FCLK_DIV3 3 15 #define CLKID_FCLK_DIV4 4 16 #define CLKID_FCLK_DIV5 5 17 #define CLKID_FCLK_DIV7 6 18 #define CLKID_GP0_PLL 7 19 #define CLKID_CLK81 10 20 #define CLKID_MPLL0 11 21 #define CLKID_MPLL1 12 22 #define CLKID_MPLL2 13 23 #define CLKID_MPLL3 14 24 #define CLKID_DDR 15 25 #define CLKID_AUDIO_LOCKER 16 26 #define CLKID_MIPI_DSI_HOST 17 27 #define CLKID_ISA 18 28 #define CLKID_PL301 19 29 #define CLKID_PERIPHS 20 30 #define CLKID_SPICC0 21 31 #define CLKID_I2C 22 32 #define CLKID_RNG0 23 33 #define CLKID_UART0 24 34 #define CLKID_MIPI_DSI_PHY 25 35 #define CLKID_SPICC1 26 36 #define CLKID_PCIE_A 27 37 #define CLKID_PCIE_B 28 38 #define CLKID_HIU_IFACE 29 39 #define CLKID_ASSIST_MISC 30 40 #define CLKID_SD_EMMC_B 31 41 #define CLKID_SD_EMMC_C 32 42 #define CLKID_DMA 33 43 #define CLKID_SPI 34 44 #define CLKID_AUDIO 35 45 #define CLKID_ETH 36 46 #define CLKID_UART1 37 47 #define CLKID_G2D 38 48 #define CLKID_USB0 39 49 #define CLKID_USB1 40 50 #define CLKID_RESET 41 51 #define CLKID_USB 42 52 #define CLKID_AHB_ARB0 43 53 #define CLKID_EFUSE 44 54 #define CLKID_BOOT_ROM 45 55 #define CLKID_AHB_DATA_BUS 46 56 #define CLKID_AHB_CTRL_BUS 47 57 #define CLKID_USB1_DDR_BRIDGE 48 58 #define CLKID_USB0_DDR_BRIDGE 49 59 #define CLKID_MMC_PCLK 50 60 #define CLKID_VPU_INTR 51 61 #define CLKID_SEC_AHB_AHB3_BRIDGE 52 62 #define CLKID_GIC 53 63 #define CLKID_AO_MEDIA_CPU 54 64 #define CLKID_AO_AHB_SRAM 55 65 #define CLKID_AO_AHB_BUS 56 66 #define CLKID_AO_IFACE 57 67 #define CLKID_AO_I2C 58 68 #define CLKID_SD_EMMC_B_CLK0 59 69 #define CLKID_SD_EMMC_C_CLK0 60 70 #define CLKID_HIFI_PLL 69 71 #define CLKID_PCIE_CML_EN0 79 72 #define CLKID_PCIE_CML_EN1 80 73 #define CLKID_GEN_CLK 84 74 #define CLKID_VPU_0_SEL 92 75 #define CLKID_VPU_0 93 76 #define CLKID_VPU_1_SEL 95 77 #define CLKID_VPU_1 96 78 #define CLKID_VPU 97 79 #define CLKID_VAPB_0_SEL 99 80 #define CLKID_VAPB_0 100 81 #define CLKID_VAPB_1_SEL 102 82 #define CLKID_VAPB_1 103 83 #define CLKID_VAPB_SEL 104 84 #define CLKID_VAPB 105 85 #define CLKID_VCLK 106 86 #define CLKID_VCLK2 107 87 #define CLKID_VCLK_DIV1 122 88 #define CLKID_VCLK_DIV2 123 89 #define CLKID_VCLK_DIV4 124 90 #define CLKID_VCLK_DIV6 125 91 #define CLKID_VCLK_DIV12 126 92 #define CLKID_VCLK2_DIV1 127 93 #define CLKID_VCLK2_DIV2 128 94 #define CLKID_VCLK2_DIV4 129 95 #define CLKID_VCLK2_DIV6 130 96 #define CLKID_VCLK2_DIV12 131 97 #define CLKID_CTS_ENCL 133 98 #define CLKID_VDIN_MEAS 136 99 100 #endif /* __AXG_CLKC_H */ 101