1*9c92ab61SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 29bc01114STero Kristo /* 39bc01114STero Kristo * Copyright 2017 Texas Instruments, Inc. 49bc01114STero Kristo */ 59bc01114STero Kristo #ifndef __DT_BINDINGS_CLK_AM4_H 69bc01114STero Kristo #define __DT_BINDINGS_CLK_AM4_H 79bc01114STero Kristo 89bc01114STero Kristo #define AM4_CLKCTRL_OFFSET 0x20 99bc01114STero Kristo #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) 109bc01114STero Kristo 118cfbdbd9STero Kristo /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 128cfbdbd9STero Kristo 139bc01114STero Kristo /* l4_wkup clocks */ 149bc01114STero Kristo #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) 159bc01114STero Kristo #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 169bc01114STero Kristo #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) 179bc01114STero Kristo #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) 189bc01114STero Kristo #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) 199bc01114STero Kristo #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) 209bc01114STero Kristo #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) 219bc01114STero Kristo #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) 229bc01114STero Kristo #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) 239bc01114STero Kristo #define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) 249bc01114STero Kristo #define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) 259bc01114STero Kristo #define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) 269bc01114STero Kristo 279bc01114STero Kristo /* mpu clocks */ 289bc01114STero Kristo #define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 299bc01114STero Kristo 309bc01114STero Kristo /* gfx_l3 clocks */ 319bc01114STero Kristo #define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 329bc01114STero Kristo 339bc01114STero Kristo /* l4_rtc clocks */ 349bc01114STero Kristo #define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 359bc01114STero Kristo 369bc01114STero Kristo /* l4_per clocks */ 379bc01114STero Kristo #define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 389bc01114STero Kristo #define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 399bc01114STero Kristo #define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 409bc01114STero Kristo #define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 419bc01114STero Kristo #define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 429bc01114STero Kristo #define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 439bc01114STero Kristo #define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) 449bc01114STero Kristo #define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) 459bc01114STero Kristo #define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 469bc01114STero Kristo #define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 479bc01114STero Kristo #define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 489bc01114STero Kristo #define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 499bc01114STero Kristo #define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 509bc01114STero Kristo #define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 519bc01114STero Kristo #define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) 529bc01114STero Kristo #define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) 539bc01114STero Kristo #define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) 549bc01114STero Kristo #define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) 559bc01114STero Kristo #define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) 569bc01114STero Kristo #define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) 579bc01114STero Kristo #define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) 589bc01114STero Kristo #define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) 599bc01114STero Kristo #define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) 609bc01114STero Kristo #define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) 619bc01114STero Kristo #define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) 629bc01114STero Kristo #define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) 639bc01114STero Kristo #define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) 649bc01114STero Kristo #define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) 659bc01114STero Kristo #define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) 669bc01114STero Kristo #define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) 679bc01114STero Kristo #define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) 689bc01114STero Kristo #define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) 699bc01114STero Kristo #define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) 709bc01114STero Kristo #define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) 719bc01114STero Kristo #define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) 729bc01114STero Kristo #define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) 739bc01114STero Kristo #define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) 749bc01114STero Kristo #define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) 759bc01114STero Kristo #define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) 769bc01114STero Kristo #define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) 779bc01114STero Kristo #define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) 789bc01114STero Kristo #define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) 799bc01114STero Kristo #define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) 809bc01114STero Kristo #define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) 819bc01114STero Kristo #define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) 829bc01114STero Kristo #define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) 839bc01114STero Kristo #define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) 849bc01114STero Kristo #define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) 859bc01114STero Kristo #define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) 869bc01114STero Kristo #define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) 879bc01114STero Kristo #define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) 889bc01114STero Kristo #define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) 899bc01114STero Kristo #define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) 909bc01114STero Kristo #define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) 919bc01114STero Kristo #define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) 929bc01114STero Kristo #define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) 939bc01114STero Kristo #define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) 949bc01114STero Kristo #define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) 959bc01114STero Kristo #define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) 969bc01114STero Kristo #define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) 979bc01114STero Kristo #define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) 989bc01114STero Kristo #define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) 999bc01114STero Kristo #define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) 1009bc01114STero Kristo #define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) 1019bc01114STero Kristo #define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) 1029bc01114STero Kristo #define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) 1039bc01114STero Kristo #define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) 1049bc01114STero Kristo #define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) 1059bc01114STero Kristo #define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) 1069bc01114STero Kristo 1078cfbdbd9STero Kristo /* XXX: Compatibility part end. */ 1088cfbdbd9STero Kristo 1098cfbdbd9STero Kristo /* l3s_tsc clocks */ 1108cfbdbd9STero Kristo #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 1118cfbdbd9STero Kristo #define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) 1128cfbdbd9STero Kristo #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) 1138cfbdbd9STero Kristo 1148cfbdbd9STero Kristo /* l4_wkup_aon clocks */ 1158cfbdbd9STero Kristo #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 1168cfbdbd9STero Kristo #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) 1178cfbdbd9STero Kristo #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) 1188cfbdbd9STero Kristo #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) 1198cfbdbd9STero Kristo 1208cfbdbd9STero Kristo /* l4_wkup clocks */ 1218cfbdbd9STero Kristo #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 1228cfbdbd9STero Kristo #define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) 1238cfbdbd9STero Kristo #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) 1248cfbdbd9STero Kristo #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) 1258cfbdbd9STero Kristo #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) 1268cfbdbd9STero Kristo #define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340) 1278cfbdbd9STero Kristo #define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348) 1288cfbdbd9STero Kristo #define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350) 1298cfbdbd9STero Kristo #define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358) 1308cfbdbd9STero Kristo #define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360) 1318cfbdbd9STero Kristo #define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368) 1328cfbdbd9STero Kristo 1338cfbdbd9STero Kristo /* mpu clocks */ 1348cfbdbd9STero Kristo #define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 1358cfbdbd9STero Kristo 1368cfbdbd9STero Kristo /* gfx_l3 clocks */ 1378cfbdbd9STero Kristo #define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 1388cfbdbd9STero Kristo 1398cfbdbd9STero Kristo /* l4_rtc clocks */ 1408cfbdbd9STero Kristo #define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 1418cfbdbd9STero Kristo 1428cfbdbd9STero Kristo /* l3 clocks */ 1438cfbdbd9STero Kristo #define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 1448cfbdbd9STero Kristo #define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 1458cfbdbd9STero Kristo #define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 1468cfbdbd9STero Kristo #define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 1478cfbdbd9STero Kristo #define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 1488cfbdbd9STero Kristo #define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 1498cfbdbd9STero Kristo #define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 1508cfbdbd9STero Kristo #define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 1518cfbdbd9STero Kristo #define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 1528cfbdbd9STero Kristo #define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 1538cfbdbd9STero Kristo #define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 1548cfbdbd9STero Kristo 1558cfbdbd9STero Kristo /* l3s clocks */ 1568cfbdbd9STero Kristo #define AM4_L3S_CLKCTRL_OFFSET 0x68 1578cfbdbd9STero Kristo #define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) 1588cfbdbd9STero Kristo #define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) 1598cfbdbd9STero Kristo #define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) 1608cfbdbd9STero Kristo #define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) 1618cfbdbd9STero Kristo #define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) 1628cfbdbd9STero Kristo #define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) 1638cfbdbd9STero Kristo #define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) 1648cfbdbd9STero Kristo #define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258) 1658cfbdbd9STero Kristo #define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260) 1668cfbdbd9STero Kristo #define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268) 1678cfbdbd9STero Kristo 1688cfbdbd9STero Kristo /* pruss_ocp clocks */ 1698cfbdbd9STero Kristo #define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320 1708cfbdbd9STero Kristo #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) 1718cfbdbd9STero Kristo #define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320) 1728cfbdbd9STero Kristo 1738cfbdbd9STero Kristo /* l4ls clocks */ 1748cfbdbd9STero Kristo #define AM4_L4LS_CLKCTRL_OFFSET 0x420 1758cfbdbd9STero Kristo #define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) 1768cfbdbd9STero Kristo #define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420) 1778cfbdbd9STero Kristo #define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428) 1788cfbdbd9STero Kristo #define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430) 1798cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438) 1808cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440) 1818cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448) 1828cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450) 1838cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458) 1848cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460) 1858cfbdbd9STero Kristo #define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468) 1868cfbdbd9STero Kristo #define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478) 1878cfbdbd9STero Kristo #define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480) 1888cfbdbd9STero Kristo #define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488) 1898cfbdbd9STero Kristo #define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490) 1908cfbdbd9STero Kristo #define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498) 1918cfbdbd9STero Kristo #define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0) 1928cfbdbd9STero Kristo #define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8) 1938cfbdbd9STero Kristo #define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0) 1948cfbdbd9STero Kristo #define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8) 1958cfbdbd9STero Kristo #define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0) 1968cfbdbd9STero Kristo #define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8) 1978cfbdbd9STero Kristo #define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0) 1988cfbdbd9STero Kristo #define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500) 1998cfbdbd9STero Kristo #define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508) 2008cfbdbd9STero Kristo #define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510) 2018cfbdbd9STero Kristo #define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518) 2028cfbdbd9STero Kristo #define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520) 2038cfbdbd9STero Kristo #define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528) 2048cfbdbd9STero Kristo #define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530) 2058cfbdbd9STero Kristo #define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538) 2068cfbdbd9STero Kristo #define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540) 2078cfbdbd9STero Kristo #define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548) 2088cfbdbd9STero Kristo #define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550) 2098cfbdbd9STero Kristo #define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558) 2108cfbdbd9STero Kristo #define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560) 2118cfbdbd9STero Kristo #define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568) 2128cfbdbd9STero Kristo #define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570) 2138cfbdbd9STero Kristo #define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578) 2148cfbdbd9STero Kristo #define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580) 2158cfbdbd9STero Kristo #define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588) 2168cfbdbd9STero Kristo #define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590) 2178cfbdbd9STero Kristo #define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598) 2188cfbdbd9STero Kristo #define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0) 2198cfbdbd9STero Kristo #define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8) 2208cfbdbd9STero Kristo #define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0) 2218cfbdbd9STero Kristo 2228cfbdbd9STero Kristo /* emif clocks */ 2238cfbdbd9STero Kristo #define AM4_EMIF_CLKCTRL_OFFSET 0x720 2248cfbdbd9STero Kristo #define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) 2258cfbdbd9STero Kristo #define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720) 2268cfbdbd9STero Kristo 2278cfbdbd9STero Kristo /* dss clocks */ 2288cfbdbd9STero Kristo #define AM4_DSS_CLKCTRL_OFFSET 0xa20 2298cfbdbd9STero Kristo #define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) 2308cfbdbd9STero Kristo #define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20) 2318cfbdbd9STero Kristo 2328cfbdbd9STero Kristo /* cpsw_125mhz clocks */ 2338cfbdbd9STero Kristo #define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20 2348cfbdbd9STero Kristo #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) 2358cfbdbd9STero Kristo #define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20) 2368cfbdbd9STero Kristo 2379bc01114STero Kristo #endif 238