1*9bc01114STero Kristo /* 2*9bc01114STero Kristo * Copyright 2017 Texas Instruments, Inc. 3*9bc01114STero Kristo * 4*9bc01114STero Kristo * This software is licensed under the terms of the GNU General Public 5*9bc01114STero Kristo * License version 2, as published by the Free Software Foundation, and 6*9bc01114STero Kristo * may be copied, distributed, and modified under those terms. 7*9bc01114STero Kristo * 8*9bc01114STero Kristo * This program is distributed in the hope that it will be useful, 9*9bc01114STero Kristo * but WITHOUT ANY WARRANTY; without even the implied warranty of 10*9bc01114STero Kristo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11*9bc01114STero Kristo * GNU General Public License for more details. 12*9bc01114STero Kristo */ 13*9bc01114STero Kristo #ifndef __DT_BINDINGS_CLK_AM4_H 14*9bc01114STero Kristo #define __DT_BINDINGS_CLK_AM4_H 15*9bc01114STero Kristo 16*9bc01114STero Kristo #define AM4_CLKCTRL_OFFSET 0x20 17*9bc01114STero Kristo #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) 18*9bc01114STero Kristo 19*9bc01114STero Kristo /* l4_wkup clocks */ 20*9bc01114STero Kristo #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) 21*9bc01114STero Kristo #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 22*9bc01114STero Kristo #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) 23*9bc01114STero Kristo #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) 24*9bc01114STero Kristo #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) 25*9bc01114STero Kristo #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) 26*9bc01114STero Kristo #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) 27*9bc01114STero Kristo #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) 28*9bc01114STero Kristo #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) 29*9bc01114STero Kristo #define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) 30*9bc01114STero Kristo #define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) 31*9bc01114STero Kristo #define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) 32*9bc01114STero Kristo 33*9bc01114STero Kristo /* mpu clocks */ 34*9bc01114STero Kristo #define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 35*9bc01114STero Kristo 36*9bc01114STero Kristo /* gfx_l3 clocks */ 37*9bc01114STero Kristo #define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 38*9bc01114STero Kristo 39*9bc01114STero Kristo /* l4_rtc clocks */ 40*9bc01114STero Kristo #define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 41*9bc01114STero Kristo 42*9bc01114STero Kristo /* l4_per clocks */ 43*9bc01114STero Kristo #define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 44*9bc01114STero Kristo #define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 45*9bc01114STero Kristo #define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 46*9bc01114STero Kristo #define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 47*9bc01114STero Kristo #define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 48*9bc01114STero Kristo #define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 49*9bc01114STero Kristo #define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) 50*9bc01114STero Kristo #define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) 51*9bc01114STero Kristo #define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 52*9bc01114STero Kristo #define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 53*9bc01114STero Kristo #define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 54*9bc01114STero Kristo #define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 55*9bc01114STero Kristo #define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 56*9bc01114STero Kristo #define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 57*9bc01114STero Kristo #define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) 58*9bc01114STero Kristo #define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) 59*9bc01114STero Kristo #define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) 60*9bc01114STero Kristo #define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) 61*9bc01114STero Kristo #define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) 62*9bc01114STero Kristo #define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) 63*9bc01114STero Kristo #define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) 64*9bc01114STero Kristo #define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) 65*9bc01114STero Kristo #define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) 66*9bc01114STero Kristo #define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) 67*9bc01114STero Kristo #define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) 68*9bc01114STero Kristo #define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) 69*9bc01114STero Kristo #define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) 70*9bc01114STero Kristo #define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) 71*9bc01114STero Kristo #define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) 72*9bc01114STero Kristo #define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) 73*9bc01114STero Kristo #define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) 74*9bc01114STero Kristo #define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) 75*9bc01114STero Kristo #define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) 76*9bc01114STero Kristo #define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) 77*9bc01114STero Kristo #define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) 78*9bc01114STero Kristo #define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) 79*9bc01114STero Kristo #define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) 80*9bc01114STero Kristo #define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) 81*9bc01114STero Kristo #define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) 82*9bc01114STero Kristo #define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) 83*9bc01114STero Kristo #define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) 84*9bc01114STero Kristo #define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) 85*9bc01114STero Kristo #define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) 86*9bc01114STero Kristo #define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) 87*9bc01114STero Kristo #define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) 88*9bc01114STero Kristo #define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) 89*9bc01114STero Kristo #define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) 90*9bc01114STero Kristo #define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) 91*9bc01114STero Kristo #define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) 92*9bc01114STero Kristo #define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) 93*9bc01114STero Kristo #define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) 94*9bc01114STero Kristo #define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) 95*9bc01114STero Kristo #define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) 96*9bc01114STero Kristo #define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) 97*9bc01114STero Kristo #define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) 98*9bc01114STero Kristo #define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) 99*9bc01114STero Kristo #define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) 100*9bc01114STero Kristo #define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) 101*9bc01114STero Kristo #define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) 102*9bc01114STero Kristo #define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) 103*9bc01114STero Kristo #define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) 104*9bc01114STero Kristo #define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) 105*9bc01114STero Kristo #define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) 106*9bc01114STero Kristo #define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) 107*9bc01114STero Kristo #define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) 108*9bc01114STero Kristo #define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) 109*9bc01114STero Kristo #define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) 110*9bc01114STero Kristo #define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) 111*9bc01114STero Kristo #define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) 112*9bc01114STero Kristo 113*9bc01114STero Kristo #endif 114