19bc01114STero Kristo /* 29bc01114STero Kristo * Copyright 2017 Texas Instruments, Inc. 39bc01114STero Kristo * 49bc01114STero Kristo * This software is licensed under the terms of the GNU General Public 59bc01114STero Kristo * License version 2, as published by the Free Software Foundation, and 69bc01114STero Kristo * may be copied, distributed, and modified under those terms. 79bc01114STero Kristo * 89bc01114STero Kristo * This program is distributed in the hope that it will be useful, 99bc01114STero Kristo * but WITHOUT ANY WARRANTY; without even the implied warranty of 109bc01114STero Kristo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 119bc01114STero Kristo * GNU General Public License for more details. 129bc01114STero Kristo */ 139bc01114STero Kristo #ifndef __DT_BINDINGS_CLK_AM4_H 149bc01114STero Kristo #define __DT_BINDINGS_CLK_AM4_H 159bc01114STero Kristo 169bc01114STero Kristo #define AM4_CLKCTRL_OFFSET 0x20 179bc01114STero Kristo #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) 189bc01114STero Kristo 19*8cfbdbd9STero Kristo /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 20*8cfbdbd9STero Kristo 219bc01114STero Kristo /* l4_wkup clocks */ 229bc01114STero Kristo #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) 239bc01114STero Kristo #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 249bc01114STero Kristo #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) 259bc01114STero Kristo #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) 269bc01114STero Kristo #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) 279bc01114STero Kristo #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) 289bc01114STero Kristo #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) 299bc01114STero Kristo #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) 309bc01114STero Kristo #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) 319bc01114STero Kristo #define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) 329bc01114STero Kristo #define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) 339bc01114STero Kristo #define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) 349bc01114STero Kristo 359bc01114STero Kristo /* mpu clocks */ 369bc01114STero Kristo #define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 379bc01114STero Kristo 389bc01114STero Kristo /* gfx_l3 clocks */ 399bc01114STero Kristo #define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 409bc01114STero Kristo 419bc01114STero Kristo /* l4_rtc clocks */ 429bc01114STero Kristo #define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 439bc01114STero Kristo 449bc01114STero Kristo /* l4_per clocks */ 459bc01114STero Kristo #define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 469bc01114STero Kristo #define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 479bc01114STero Kristo #define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 489bc01114STero Kristo #define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 499bc01114STero Kristo #define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 509bc01114STero Kristo #define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 519bc01114STero Kristo #define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) 529bc01114STero Kristo #define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) 539bc01114STero Kristo #define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 549bc01114STero Kristo #define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 559bc01114STero Kristo #define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 569bc01114STero Kristo #define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 579bc01114STero Kristo #define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 589bc01114STero Kristo #define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 599bc01114STero Kristo #define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) 609bc01114STero Kristo #define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) 619bc01114STero Kristo #define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) 629bc01114STero Kristo #define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) 639bc01114STero Kristo #define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) 649bc01114STero Kristo #define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) 659bc01114STero Kristo #define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) 669bc01114STero Kristo #define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) 679bc01114STero Kristo #define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) 689bc01114STero Kristo #define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) 699bc01114STero Kristo #define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) 709bc01114STero Kristo #define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) 719bc01114STero Kristo #define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) 729bc01114STero Kristo #define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) 739bc01114STero Kristo #define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) 749bc01114STero Kristo #define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) 759bc01114STero Kristo #define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) 769bc01114STero Kristo #define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) 779bc01114STero Kristo #define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) 789bc01114STero Kristo #define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) 799bc01114STero Kristo #define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) 809bc01114STero Kristo #define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) 819bc01114STero Kristo #define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) 829bc01114STero Kristo #define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) 839bc01114STero Kristo #define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) 849bc01114STero Kristo #define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) 859bc01114STero Kristo #define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) 869bc01114STero Kristo #define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) 879bc01114STero Kristo #define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) 889bc01114STero Kristo #define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) 899bc01114STero Kristo #define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) 909bc01114STero Kristo #define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) 919bc01114STero Kristo #define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) 929bc01114STero Kristo #define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) 939bc01114STero Kristo #define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) 949bc01114STero Kristo #define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) 959bc01114STero Kristo #define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) 969bc01114STero Kristo #define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) 979bc01114STero Kristo #define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) 989bc01114STero Kristo #define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) 999bc01114STero Kristo #define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) 1009bc01114STero Kristo #define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) 1019bc01114STero Kristo #define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) 1029bc01114STero Kristo #define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) 1039bc01114STero Kristo #define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) 1049bc01114STero Kristo #define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) 1059bc01114STero Kristo #define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) 1069bc01114STero Kristo #define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) 1079bc01114STero Kristo #define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) 1089bc01114STero Kristo #define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) 1099bc01114STero Kristo #define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) 1109bc01114STero Kristo #define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) 1119bc01114STero Kristo #define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) 1129bc01114STero Kristo #define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) 1139bc01114STero Kristo #define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) 1149bc01114STero Kristo 115*8cfbdbd9STero Kristo /* XXX: Compatibility part end. */ 116*8cfbdbd9STero Kristo 117*8cfbdbd9STero Kristo /* l3s_tsc clocks */ 118*8cfbdbd9STero Kristo #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 119*8cfbdbd9STero Kristo #define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) 120*8cfbdbd9STero Kristo #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) 121*8cfbdbd9STero Kristo 122*8cfbdbd9STero Kristo /* l4_wkup_aon clocks */ 123*8cfbdbd9STero Kristo #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 124*8cfbdbd9STero Kristo #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) 125*8cfbdbd9STero Kristo #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) 126*8cfbdbd9STero Kristo #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) 127*8cfbdbd9STero Kristo 128*8cfbdbd9STero Kristo /* l4_wkup clocks */ 129*8cfbdbd9STero Kristo #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 130*8cfbdbd9STero Kristo #define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) 131*8cfbdbd9STero Kristo #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) 132*8cfbdbd9STero Kristo #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) 133*8cfbdbd9STero Kristo #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) 134*8cfbdbd9STero Kristo #define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340) 135*8cfbdbd9STero Kristo #define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348) 136*8cfbdbd9STero Kristo #define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350) 137*8cfbdbd9STero Kristo #define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358) 138*8cfbdbd9STero Kristo #define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360) 139*8cfbdbd9STero Kristo #define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368) 140*8cfbdbd9STero Kristo 141*8cfbdbd9STero Kristo /* mpu clocks */ 142*8cfbdbd9STero Kristo #define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 143*8cfbdbd9STero Kristo 144*8cfbdbd9STero Kristo /* gfx_l3 clocks */ 145*8cfbdbd9STero Kristo #define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 146*8cfbdbd9STero Kristo 147*8cfbdbd9STero Kristo /* l4_rtc clocks */ 148*8cfbdbd9STero Kristo #define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 149*8cfbdbd9STero Kristo 150*8cfbdbd9STero Kristo /* l3 clocks */ 151*8cfbdbd9STero Kristo #define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 152*8cfbdbd9STero Kristo #define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 153*8cfbdbd9STero Kristo #define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 154*8cfbdbd9STero Kristo #define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 155*8cfbdbd9STero Kristo #define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 156*8cfbdbd9STero Kristo #define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 157*8cfbdbd9STero Kristo #define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 158*8cfbdbd9STero Kristo #define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 159*8cfbdbd9STero Kristo #define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 160*8cfbdbd9STero Kristo #define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 161*8cfbdbd9STero Kristo #define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 162*8cfbdbd9STero Kristo 163*8cfbdbd9STero Kristo /* l3s clocks */ 164*8cfbdbd9STero Kristo #define AM4_L3S_CLKCTRL_OFFSET 0x68 165*8cfbdbd9STero Kristo #define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) 166*8cfbdbd9STero Kristo #define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) 167*8cfbdbd9STero Kristo #define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) 168*8cfbdbd9STero Kristo #define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) 169*8cfbdbd9STero Kristo #define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) 170*8cfbdbd9STero Kristo #define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) 171*8cfbdbd9STero Kristo #define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) 172*8cfbdbd9STero Kristo #define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258) 173*8cfbdbd9STero Kristo #define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260) 174*8cfbdbd9STero Kristo #define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268) 175*8cfbdbd9STero Kristo 176*8cfbdbd9STero Kristo /* pruss_ocp clocks */ 177*8cfbdbd9STero Kristo #define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320 178*8cfbdbd9STero Kristo #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) 179*8cfbdbd9STero Kristo #define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320) 180*8cfbdbd9STero Kristo 181*8cfbdbd9STero Kristo /* l4ls clocks */ 182*8cfbdbd9STero Kristo #define AM4_L4LS_CLKCTRL_OFFSET 0x420 183*8cfbdbd9STero Kristo #define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) 184*8cfbdbd9STero Kristo #define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420) 185*8cfbdbd9STero Kristo #define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428) 186*8cfbdbd9STero Kristo #define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430) 187*8cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438) 188*8cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440) 189*8cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448) 190*8cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450) 191*8cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458) 192*8cfbdbd9STero Kristo #define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460) 193*8cfbdbd9STero Kristo #define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468) 194*8cfbdbd9STero Kristo #define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478) 195*8cfbdbd9STero Kristo #define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480) 196*8cfbdbd9STero Kristo #define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488) 197*8cfbdbd9STero Kristo #define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490) 198*8cfbdbd9STero Kristo #define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498) 199*8cfbdbd9STero Kristo #define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0) 200*8cfbdbd9STero Kristo #define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8) 201*8cfbdbd9STero Kristo #define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0) 202*8cfbdbd9STero Kristo #define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8) 203*8cfbdbd9STero Kristo #define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0) 204*8cfbdbd9STero Kristo #define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8) 205*8cfbdbd9STero Kristo #define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0) 206*8cfbdbd9STero Kristo #define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500) 207*8cfbdbd9STero Kristo #define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508) 208*8cfbdbd9STero Kristo #define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510) 209*8cfbdbd9STero Kristo #define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518) 210*8cfbdbd9STero Kristo #define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520) 211*8cfbdbd9STero Kristo #define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528) 212*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530) 213*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538) 214*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540) 215*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548) 216*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550) 217*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558) 218*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560) 219*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568) 220*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570) 221*8cfbdbd9STero Kristo #define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578) 222*8cfbdbd9STero Kristo #define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580) 223*8cfbdbd9STero Kristo #define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588) 224*8cfbdbd9STero Kristo #define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590) 225*8cfbdbd9STero Kristo #define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598) 226*8cfbdbd9STero Kristo #define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0) 227*8cfbdbd9STero Kristo #define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8) 228*8cfbdbd9STero Kristo #define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0) 229*8cfbdbd9STero Kristo 230*8cfbdbd9STero Kristo /* emif clocks */ 231*8cfbdbd9STero Kristo #define AM4_EMIF_CLKCTRL_OFFSET 0x720 232*8cfbdbd9STero Kristo #define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) 233*8cfbdbd9STero Kristo #define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720) 234*8cfbdbd9STero Kristo 235*8cfbdbd9STero Kristo /* dss clocks */ 236*8cfbdbd9STero Kristo #define AM4_DSS_CLKCTRL_OFFSET 0xa20 237*8cfbdbd9STero Kristo #define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) 238*8cfbdbd9STero Kristo #define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20) 239*8cfbdbd9STero Kristo 240*8cfbdbd9STero Kristo /* cpsw_125mhz clocks */ 241*8cfbdbd9STero Kristo #define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20 242*8cfbdbd9STero Kristo #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) 243*8cfbdbd9STero Kristo #define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20) 244*8cfbdbd9STero Kristo 2459bc01114STero Kristo #endif 246