1172c48c7STero Kristo /* 2172c48c7STero Kristo * Copyright 2017 Texas Instruments, Inc. 3172c48c7STero Kristo * 4172c48c7STero Kristo * This software is licensed under the terms of the GNU General Public 5172c48c7STero Kristo * License version 2, as published by the Free Software Foundation, and 6172c48c7STero Kristo * may be copied, distributed, and modified under those terms. 7172c48c7STero Kristo * 8172c48c7STero Kristo * This program is distributed in the hope that it will be useful, 9172c48c7STero Kristo * but WITHOUT ANY WARRANTY; without even the implied warranty of 10172c48c7STero Kristo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11172c48c7STero Kristo * GNU General Public License for more details. 12172c48c7STero Kristo */ 13172c48c7STero Kristo #ifndef __DT_BINDINGS_CLK_AM3_H 14172c48c7STero Kristo #define __DT_BINDINGS_CLK_AM3_H 15172c48c7STero Kristo 16172c48c7STero Kristo #define AM3_CLKCTRL_OFFSET 0x0 17172c48c7STero Kristo #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) 18172c48c7STero Kristo 19*e358cf2eSTero Kristo /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 20*e358cf2eSTero Kristo 21172c48c7STero Kristo /* l4_per clocks */ 22172c48c7STero Kristo #define AM3_L4_PER_CLKCTRL_OFFSET 0x14 23172c48c7STero Kristo #define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) 24172c48c7STero Kristo #define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) 25172c48c7STero Kristo #define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) 26172c48c7STero Kristo #define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) 27172c48c7STero Kristo #define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) 28172c48c7STero Kristo #define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) 29172c48c7STero Kristo #define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) 30172c48c7STero Kristo #define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) 31172c48c7STero Kristo #define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) 32172c48c7STero Kristo #define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) 33172c48c7STero Kristo #define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) 34172c48c7STero Kristo #define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) 35172c48c7STero Kristo #define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) 36172c48c7STero Kristo #define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) 37172c48c7STero Kristo #define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) 38172c48c7STero Kristo #define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) 39172c48c7STero Kristo #define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) 40172c48c7STero Kristo #define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) 41172c48c7STero Kristo #define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) 42172c48c7STero Kristo #define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) 43172c48c7STero Kristo #define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) 44172c48c7STero Kristo #define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) 45172c48c7STero Kristo #define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) 46172c48c7STero Kristo #define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) 47172c48c7STero Kristo #define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) 48172c48c7STero Kristo #define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) 49172c48c7STero Kristo #define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) 50172c48c7STero Kristo #define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) 51172c48c7STero Kristo #define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) 52172c48c7STero Kristo #define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) 53172c48c7STero Kristo #define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) 54172c48c7STero Kristo #define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) 55172c48c7STero Kristo #define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) 56172c48c7STero Kristo #define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) 57172c48c7STero Kristo #define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) 58172c48c7STero Kristo #define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) 59172c48c7STero Kristo #define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) 60172c48c7STero Kristo #define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) 61172c48c7STero Kristo #define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) 62172c48c7STero Kristo #define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) 63172c48c7STero Kristo #define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) 64172c48c7STero Kristo #define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) 65172c48c7STero Kristo #define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) 66172c48c7STero Kristo #define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) 67172c48c7STero Kristo #define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) 68172c48c7STero Kristo #define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) 69172c48c7STero Kristo #define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) 70172c48c7STero Kristo #define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) 71172c48c7STero Kristo #define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) 72172c48c7STero Kristo #define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) 73172c48c7STero Kristo #define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) 74172c48c7STero Kristo #define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) 75172c48c7STero Kristo 76172c48c7STero Kristo /* l4_wkup clocks */ 77172c48c7STero Kristo #define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 78172c48c7STero Kristo #define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) 79172c48c7STero Kristo #define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) 80172c48c7STero Kristo #define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) 81172c48c7STero Kristo #define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) 82172c48c7STero Kristo #define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) 83172c48c7STero Kristo #define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) 84172c48c7STero Kristo #define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) 85172c48c7STero Kristo #define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) 86172c48c7STero Kristo #define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) 87172c48c7STero Kristo #define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) 88172c48c7STero Kristo #define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) 89172c48c7STero Kristo #define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) 90172c48c7STero Kristo #define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) 91172c48c7STero Kristo 92172c48c7STero Kristo /* mpu clocks */ 93172c48c7STero Kristo #define AM3_MPU_CLKCTRL_OFFSET 0x4 94172c48c7STero Kristo #define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) 95172c48c7STero Kristo #define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) 96172c48c7STero Kristo 97172c48c7STero Kristo /* l4_rtc clocks */ 98172c48c7STero Kristo #define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) 99172c48c7STero Kristo 100172c48c7STero Kristo /* gfx_l3 clocks */ 101172c48c7STero Kristo #define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 102172c48c7STero Kristo #define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) 103172c48c7STero Kristo #define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) 104172c48c7STero Kristo 105172c48c7STero Kristo /* l4_cefuse clocks */ 106172c48c7STero Kristo #define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 107172c48c7STero Kristo #define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) 108172c48c7STero Kristo #define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) 109172c48c7STero Kristo 110*e358cf2eSTero Kristo /* XXX: Compatibility part end */ 111*e358cf2eSTero Kristo 112*e358cf2eSTero Kristo /* l4ls clocks */ 113*e358cf2eSTero Kristo #define AM3_L4LS_CLKCTRL_OFFSET 0x38 114*e358cf2eSTero Kristo #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) 115*e358cf2eSTero Kristo #define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) 116*e358cf2eSTero Kristo #define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) 117*e358cf2eSTero Kristo #define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) 118*e358cf2eSTero Kristo #define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) 119*e358cf2eSTero Kristo #define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) 120*e358cf2eSTero Kristo #define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) 121*e358cf2eSTero Kristo #define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) 122*e358cf2eSTero Kristo #define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) 123*e358cf2eSTero Kristo #define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) 124*e358cf2eSTero Kristo #define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) 125*e358cf2eSTero Kristo #define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) 126*e358cf2eSTero Kristo #define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) 127*e358cf2eSTero Kristo #define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) 128*e358cf2eSTero Kristo #define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) 129*e358cf2eSTero Kristo #define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) 130*e358cf2eSTero Kristo #define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) 131*e358cf2eSTero Kristo #define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) 132*e358cf2eSTero Kristo #define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) 133*e358cf2eSTero Kristo #define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) 134*e358cf2eSTero Kristo #define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) 135*e358cf2eSTero Kristo #define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) 136*e358cf2eSTero Kristo #define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) 137*e358cf2eSTero Kristo #define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) 138*e358cf2eSTero Kristo #define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) 139*e358cf2eSTero Kristo #define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) 140*e358cf2eSTero Kristo #define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) 141*e358cf2eSTero Kristo #define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) 142*e358cf2eSTero Kristo #define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) 143*e358cf2eSTero Kristo #define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) 144*e358cf2eSTero Kristo #define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) 145*e358cf2eSTero Kristo #define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) 146*e358cf2eSTero Kristo 147*e358cf2eSTero Kristo /* l3s clocks */ 148*e358cf2eSTero Kristo #define AM3_L3S_CLKCTRL_OFFSET 0x1c 149*e358cf2eSTero Kristo #define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) 150*e358cf2eSTero Kristo #define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) 151*e358cf2eSTero Kristo #define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) 152*e358cf2eSTero Kristo #define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) 153*e358cf2eSTero Kristo #define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) 154*e358cf2eSTero Kristo #define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) 155*e358cf2eSTero Kristo 156*e358cf2eSTero Kristo /* l3 clocks */ 157*e358cf2eSTero Kristo #define AM3_L3_CLKCTRL_OFFSET 0x24 158*e358cf2eSTero Kristo #define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) 159*e358cf2eSTero Kristo #define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) 160*e358cf2eSTero Kristo #define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) 161*e358cf2eSTero Kristo #define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) 162*e358cf2eSTero Kristo #define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) 163*e358cf2eSTero Kristo #define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) 164*e358cf2eSTero Kristo #define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) 165*e358cf2eSTero Kristo #define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) 166*e358cf2eSTero Kristo #define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) 167*e358cf2eSTero Kristo #define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) 168*e358cf2eSTero Kristo #define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) 169*e358cf2eSTero Kristo 170*e358cf2eSTero Kristo /* l4hs clocks */ 171*e358cf2eSTero Kristo #define AM3_L4HS_CLKCTRL_OFFSET 0x120 172*e358cf2eSTero Kristo #define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) 173*e358cf2eSTero Kristo #define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) 174*e358cf2eSTero Kristo 175*e358cf2eSTero Kristo /* pruss_ocp clocks */ 176*e358cf2eSTero Kristo #define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 177*e358cf2eSTero Kristo #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) 178*e358cf2eSTero Kristo #define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) 179*e358cf2eSTero Kristo 180*e358cf2eSTero Kristo /* cpsw_125mhz clocks */ 181*e358cf2eSTero Kristo #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) 182*e358cf2eSTero Kristo 183*e358cf2eSTero Kristo /* lcdc clocks */ 184*e358cf2eSTero Kristo #define AM3_LCDC_CLKCTRL_OFFSET 0x18 185*e358cf2eSTero Kristo #define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) 186*e358cf2eSTero Kristo #define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) 187*e358cf2eSTero Kristo 188*e358cf2eSTero Kristo /* clk_24mhz clocks */ 189*e358cf2eSTero Kristo #define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c 190*e358cf2eSTero Kristo #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) 191*e358cf2eSTero Kristo #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) 192*e358cf2eSTero Kristo 193*e358cf2eSTero Kristo /* l4_wkup clocks */ 194*e358cf2eSTero Kristo #define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 195*e358cf2eSTero Kristo #define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) 196*e358cf2eSTero Kristo #define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) 197*e358cf2eSTero Kristo #define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) 198*e358cf2eSTero Kristo #define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) 199*e358cf2eSTero Kristo #define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) 200*e358cf2eSTero Kristo #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) 201*e358cf2eSTero Kristo #define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) 202*e358cf2eSTero Kristo #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) 203*e358cf2eSTero Kristo #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) 204*e358cf2eSTero Kristo 205*e358cf2eSTero Kristo /* l3_aon clocks */ 206*e358cf2eSTero Kristo #define AM3_L3_AON_CLKCTRL_OFFSET 0x14 207*e358cf2eSTero Kristo #define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) 208*e358cf2eSTero Kristo #define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) 209*e358cf2eSTero Kristo 210*e358cf2eSTero Kristo /* l4_wkup_aon clocks */ 211*e358cf2eSTero Kristo #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 212*e358cf2eSTero Kristo #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) 213*e358cf2eSTero Kristo #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) 214*e358cf2eSTero Kristo 215*e358cf2eSTero Kristo /* mpu clocks */ 216*e358cf2eSTero Kristo #define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 217*e358cf2eSTero Kristo 218*e358cf2eSTero Kristo /* l4_rtc clocks */ 219*e358cf2eSTero Kristo #define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) 220*e358cf2eSTero Kristo 221*e358cf2eSTero Kristo /* gfx_l3 clocks */ 222*e358cf2eSTero Kristo #define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 223*e358cf2eSTero Kristo 224*e358cf2eSTero Kristo /* l4_cefuse clocks */ 225*e358cf2eSTero Kristo #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) 226*e358cf2eSTero Kristo 227172c48c7STero Kristo #endif 228