1*9c92ab61SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2172c48c7STero Kristo /* 3172c48c7STero Kristo * Copyright 2017 Texas Instruments, Inc. 4172c48c7STero Kristo */ 5172c48c7STero Kristo #ifndef __DT_BINDINGS_CLK_AM3_H 6172c48c7STero Kristo #define __DT_BINDINGS_CLK_AM3_H 7172c48c7STero Kristo 8172c48c7STero Kristo #define AM3_CLKCTRL_OFFSET 0x0 9172c48c7STero Kristo #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) 10172c48c7STero Kristo 11e358cf2eSTero Kristo /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 12e358cf2eSTero Kristo 13172c48c7STero Kristo /* l4_per clocks */ 14172c48c7STero Kristo #define AM3_L4_PER_CLKCTRL_OFFSET 0x14 15172c48c7STero Kristo #define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) 16172c48c7STero Kristo #define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) 17172c48c7STero Kristo #define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) 18172c48c7STero Kristo #define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) 19172c48c7STero Kristo #define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) 20172c48c7STero Kristo #define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) 21172c48c7STero Kristo #define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) 22172c48c7STero Kristo #define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) 23172c48c7STero Kristo #define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) 24172c48c7STero Kristo #define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) 25172c48c7STero Kristo #define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) 26172c48c7STero Kristo #define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) 27172c48c7STero Kristo #define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) 28172c48c7STero Kristo #define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) 29172c48c7STero Kristo #define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) 30172c48c7STero Kristo #define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) 31172c48c7STero Kristo #define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) 32172c48c7STero Kristo #define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) 33172c48c7STero Kristo #define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) 34172c48c7STero Kristo #define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) 35172c48c7STero Kristo #define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) 36172c48c7STero Kristo #define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) 37172c48c7STero Kristo #define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) 38172c48c7STero Kristo #define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) 39172c48c7STero Kristo #define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) 40172c48c7STero Kristo #define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) 41172c48c7STero Kristo #define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) 42172c48c7STero Kristo #define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) 43172c48c7STero Kristo #define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) 44172c48c7STero Kristo #define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) 45172c48c7STero Kristo #define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) 46172c48c7STero Kristo #define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) 47172c48c7STero Kristo #define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) 48172c48c7STero Kristo #define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) 49172c48c7STero Kristo #define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) 50172c48c7STero Kristo #define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) 51172c48c7STero Kristo #define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) 52172c48c7STero Kristo #define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) 53172c48c7STero Kristo #define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) 54172c48c7STero Kristo #define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) 55172c48c7STero Kristo #define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) 56172c48c7STero Kristo #define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) 57172c48c7STero Kristo #define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) 58172c48c7STero Kristo #define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) 59172c48c7STero Kristo #define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) 60172c48c7STero Kristo #define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) 61172c48c7STero Kristo #define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) 62172c48c7STero Kristo #define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) 63172c48c7STero Kristo #define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) 64172c48c7STero Kristo #define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) 65172c48c7STero Kristo #define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) 66172c48c7STero Kristo #define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) 67172c48c7STero Kristo 68172c48c7STero Kristo /* l4_wkup clocks */ 69172c48c7STero Kristo #define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 70172c48c7STero Kristo #define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) 71172c48c7STero Kristo #define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) 72172c48c7STero Kristo #define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) 73172c48c7STero Kristo #define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) 74172c48c7STero Kristo #define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) 75172c48c7STero Kristo #define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) 76172c48c7STero Kristo #define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) 77172c48c7STero Kristo #define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) 78172c48c7STero Kristo #define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) 79172c48c7STero Kristo #define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) 80172c48c7STero Kristo #define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) 81172c48c7STero Kristo #define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) 82172c48c7STero Kristo #define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) 83172c48c7STero Kristo 84172c48c7STero Kristo /* mpu clocks */ 85172c48c7STero Kristo #define AM3_MPU_CLKCTRL_OFFSET 0x4 86172c48c7STero Kristo #define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) 87172c48c7STero Kristo #define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) 88172c48c7STero Kristo 89172c48c7STero Kristo /* l4_rtc clocks */ 90172c48c7STero Kristo #define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) 91172c48c7STero Kristo 92172c48c7STero Kristo /* gfx_l3 clocks */ 93172c48c7STero Kristo #define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 94172c48c7STero Kristo #define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) 95172c48c7STero Kristo #define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) 96172c48c7STero Kristo 97172c48c7STero Kristo /* l4_cefuse clocks */ 98172c48c7STero Kristo #define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 99172c48c7STero Kristo #define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) 100172c48c7STero Kristo #define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) 101172c48c7STero Kristo 102e358cf2eSTero Kristo /* XXX: Compatibility part end */ 103e358cf2eSTero Kristo 104e358cf2eSTero Kristo /* l4ls clocks */ 105e358cf2eSTero Kristo #define AM3_L4LS_CLKCTRL_OFFSET 0x38 106e358cf2eSTero Kristo #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) 107e358cf2eSTero Kristo #define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) 108e358cf2eSTero Kristo #define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) 109e358cf2eSTero Kristo #define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) 110e358cf2eSTero Kristo #define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) 111e358cf2eSTero Kristo #define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) 112e358cf2eSTero Kristo #define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) 113e358cf2eSTero Kristo #define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) 114e358cf2eSTero Kristo #define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) 115e358cf2eSTero Kristo #define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) 116e358cf2eSTero Kristo #define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) 117e358cf2eSTero Kristo #define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) 118e358cf2eSTero Kristo #define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) 119e358cf2eSTero Kristo #define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) 120e358cf2eSTero Kristo #define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) 121e358cf2eSTero Kristo #define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) 122e358cf2eSTero Kristo #define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) 123e358cf2eSTero Kristo #define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) 124e358cf2eSTero Kristo #define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) 125e358cf2eSTero Kristo #define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) 126e358cf2eSTero Kristo #define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) 127e358cf2eSTero Kristo #define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) 128e358cf2eSTero Kristo #define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) 129e358cf2eSTero Kristo #define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) 130e358cf2eSTero Kristo #define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) 131e358cf2eSTero Kristo #define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) 132e358cf2eSTero Kristo #define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) 133e358cf2eSTero Kristo #define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) 134e358cf2eSTero Kristo #define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) 135e358cf2eSTero Kristo #define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) 136e358cf2eSTero Kristo #define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) 137e358cf2eSTero Kristo #define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) 138e358cf2eSTero Kristo 139e358cf2eSTero Kristo /* l3s clocks */ 140e358cf2eSTero Kristo #define AM3_L3S_CLKCTRL_OFFSET 0x1c 141e358cf2eSTero Kristo #define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) 142e358cf2eSTero Kristo #define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) 143e358cf2eSTero Kristo #define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) 144e358cf2eSTero Kristo #define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) 145e358cf2eSTero Kristo #define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) 146e358cf2eSTero Kristo #define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) 147e358cf2eSTero Kristo 148e358cf2eSTero Kristo /* l3 clocks */ 149e358cf2eSTero Kristo #define AM3_L3_CLKCTRL_OFFSET 0x24 150e358cf2eSTero Kristo #define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) 151e358cf2eSTero Kristo #define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) 152e358cf2eSTero Kristo #define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) 153e358cf2eSTero Kristo #define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) 154e358cf2eSTero Kristo #define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) 155e358cf2eSTero Kristo #define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) 156e358cf2eSTero Kristo #define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) 157e358cf2eSTero Kristo #define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) 158e358cf2eSTero Kristo #define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) 159e358cf2eSTero Kristo #define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) 160e358cf2eSTero Kristo #define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) 161e358cf2eSTero Kristo 162e358cf2eSTero Kristo /* l4hs clocks */ 163e358cf2eSTero Kristo #define AM3_L4HS_CLKCTRL_OFFSET 0x120 164e358cf2eSTero Kristo #define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) 165e358cf2eSTero Kristo #define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) 166e358cf2eSTero Kristo 167e358cf2eSTero Kristo /* pruss_ocp clocks */ 168e358cf2eSTero Kristo #define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 169e358cf2eSTero Kristo #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) 170e358cf2eSTero Kristo #define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) 171e358cf2eSTero Kristo 172e358cf2eSTero Kristo /* cpsw_125mhz clocks */ 173e358cf2eSTero Kristo #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) 174e358cf2eSTero Kristo 175e358cf2eSTero Kristo /* lcdc clocks */ 176e358cf2eSTero Kristo #define AM3_LCDC_CLKCTRL_OFFSET 0x18 177e358cf2eSTero Kristo #define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) 178e358cf2eSTero Kristo #define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) 179e358cf2eSTero Kristo 180e358cf2eSTero Kristo /* clk_24mhz clocks */ 181e358cf2eSTero Kristo #define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c 182e358cf2eSTero Kristo #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) 183e358cf2eSTero Kristo #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) 184e358cf2eSTero Kristo 185e358cf2eSTero Kristo /* l4_wkup clocks */ 186e358cf2eSTero Kristo #define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 187e358cf2eSTero Kristo #define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) 188e358cf2eSTero Kristo #define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) 189e358cf2eSTero Kristo #define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) 190e358cf2eSTero Kristo #define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) 191e358cf2eSTero Kristo #define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) 192e358cf2eSTero Kristo #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) 193e358cf2eSTero Kristo #define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) 194e358cf2eSTero Kristo #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) 195e358cf2eSTero Kristo #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) 196e358cf2eSTero Kristo 197e358cf2eSTero Kristo /* l3_aon clocks */ 198e358cf2eSTero Kristo #define AM3_L3_AON_CLKCTRL_OFFSET 0x14 199e358cf2eSTero Kristo #define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) 200e358cf2eSTero Kristo #define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) 201e358cf2eSTero Kristo 202e358cf2eSTero Kristo /* l4_wkup_aon clocks */ 203e358cf2eSTero Kristo #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 204e358cf2eSTero Kristo #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) 205e358cf2eSTero Kristo #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) 206e358cf2eSTero Kristo 207e358cf2eSTero Kristo /* mpu clocks */ 208e358cf2eSTero Kristo #define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 209e358cf2eSTero Kristo 210e358cf2eSTero Kristo /* l4_rtc clocks */ 211e358cf2eSTero Kristo #define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) 212e358cf2eSTero Kristo 213e358cf2eSTero Kristo /* gfx_l3 clocks */ 214e358cf2eSTero Kristo #define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 215e358cf2eSTero Kristo 216e358cf2eSTero Kristo /* l4_cefuse clocks */ 217e358cf2eSTero Kristo #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) 218e358cf2eSTero Kristo 219172c48c7STero Kristo #endif 220