10af5b6a8STvrtko Ursulin /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 20af5b6a8STvrtko Ursulin /* Copyright (c) 2025 Valve Corporation */ 30af5b6a8STvrtko Ursulin 40af5b6a8STvrtko Ursulin #ifndef _TTM_ALLOCATION_H_ 50af5b6a8STvrtko Ursulin #define _TTM_ALLOCATION_H_ 60af5b6a8STvrtko Ursulin 77e9c548dSTvrtko Ursulin #define TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(n) ((n) & 0xff) /* Max order which caller can benefit from */ 87e9c548dSTvrtko Ursulin #define TTM_ALLOCATION_POOL_USE_DMA_ALLOC BIT(8) /* Use coherent DMA allocations. */ 97e9c548dSTvrtko Ursulin #define TTM_ALLOCATION_POOL_USE_DMA32 BIT(9) /* Use GFP_DMA32 allocations. */ 10*402b3a86STvrtko Ursulin #define TTM_ALLOCATION_PROPAGATE_ENOSPC BIT(10) /* Do not convert ENOSPC from resource managers to ENOMEM. */ 110af5b6a8STvrtko Ursulin 120af5b6a8STvrtko Ursulin #endif 13