1 /* SPDX-License-Identifier: MIT */ 2 /* Copyright © 2026 Intel Corporation */ 3 4 #ifndef _REG_BITS_H_ 5 #define _REG_BITS_H_ 6 7 #include <linux/bitfield.h> 8 #include <linux/bits.h> 9 10 /* 11 * Wrappers over the generic fixed width BIT_U*() and GENMASK_U*() 12 * implementations, for compatibility reasons with previous implementation. 13 */ 14 #define REG_GENMASK(high, low) GENMASK_U32(high, low) 15 #define REG_GENMASK64(high, low) GENMASK_U64(high, low) 16 #define REG_GENMASK16(high, low) GENMASK_U16(high, low) 17 #define REG_GENMASK8(high, low) GENMASK_U8(high, low) 18 19 #define REG_BIT(n) BIT_U32(n) 20 #define REG_BIT64(n) BIT_U64(n) 21 #define REG_BIT16(n) BIT_U16(n) 22 #define REG_BIT8(n) BIT_U8(n) 23 24 /* 25 * Local integer constant expression version of is_power_of_2(). 26 */ 27 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) 28 29 /** 30 * REG_FIELD_PREP8() - Prepare a u8 bitfield value 31 * @__mask: shifted mask defining the field's length and position 32 * @__val: value to put in the field 33 * 34 * Local copy of FIELD_PREP() to generate an integer constant expression, force 35 * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8(). 36 * 37 * @return: @__val masked and shifted into the field defined by @__mask. 38 */ 39 #define REG_FIELD_PREP8(__mask, __val) \ 40 ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ 41 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ 42 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \ 43 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ 44 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) 45 46 /** 47 * REG_FIELD_PREP16() - Prepare a u16 bitfield value 48 * @__mask: shifted mask defining the field's length and position 49 * @__val: value to put in the field 50 * 51 * Local copy of FIELD_PREP16() to generate an integer constant 52 * expression, force u8 and for consistency with 53 * REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16(). 54 * 55 * @return: @__val masked and shifted into the field defined by @__mask. 56 */ 57 #define REG_FIELD_PREP16(__mask, __val) \ 58 ((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ 59 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ 60 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \ 61 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ 62 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) 63 64 /** 65 * REG_FIELD_PREP() - Prepare a u32 bitfield value 66 * @__mask: shifted mask defining the field's length and position 67 * @__val: value to put in the field 68 * 69 * Local copy of FIELD_PREP() to generate an integer constant expression, force 70 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). 71 * 72 * @return: @__val masked and shifted into the field defined by @__mask. 73 */ 74 #define REG_FIELD_PREP(__mask, __val) \ 75 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ 76 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ 77 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ 78 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ 79 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) 80 81 /** 82 * REG_FIELD_GET8() - Extract a u8 bitfield value 83 * @__mask: shifted mask defining the field's length and position 84 * @__val: value to extract the bitfield value from 85 * 86 * Local wrapper for FIELD_GET() to force u8 and for consistency with 87 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). 88 * 89 * @return: Masked and shifted value of the field defined by @__mask in @__val. 90 */ 91 #define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val)) 92 93 /** 94 * REG_FIELD_GET() - Extract a u32 bitfield value 95 * @__mask: shifted mask defining the field's length and position 96 * @__val: value to extract the bitfield value from 97 * 98 * Local wrapper for FIELD_GET() to force u32 and for consistency with 99 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). 100 * 101 * @return: Masked and shifted value of the field defined by @__mask in @__val. 102 */ 103 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) 104 105 /** 106 * REG_FIELD_GET64() - Extract a u64 bitfield value 107 * @__mask: shifted mask defining the field's length and position 108 * @__val: value to extract the bitfield value from 109 * 110 * Local wrapper for FIELD_GET() to force u64 and for consistency with 111 * REG_GENMASK64(). 112 * 113 * @return: Masked and shifted value of the field defined by @__mask in @__val. 114 */ 115 #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) 116 117 /** 118 * REG_FIELD_MAX() - produce the maximum value representable by a field 119 * @__mask: shifted mask defining the field's length and position 120 * 121 * Local wrapper for FIELD_MAX() to return the maximum bit value that can 122 * be held in the field specified by @_mask, cast to u32 for consistency 123 * with other macros. 124 */ 125 #define REG_FIELD_MAX(__mask) ((u32)FIELD_MAX(__mask)) 126 127 #define REG_MASKED_FIELD(mask, value) \ 128 (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ 129 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ 130 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ 131 ((mask) << 16 | (value))) 132 133 #define REG_MASKED_FIELD_ENABLE(a) \ 134 (__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); }))) 135 136 #define REG_MASKED_FIELD_DISABLE(a) \ 137 (REG_MASKED_FIELD((a), 0)) 138 139 #endif 140