1 /* 2 * Copyright 2013 Intel Corporation 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #ifndef __PCIIDS_H__ 26 #define __PCIIDS_H__ 27 28 #ifdef __KERNEL__ 29 #define INTEL_VGA_DEVICE(_id, _info) { \ 30 PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \ 31 .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \ 32 .driver_data = (kernel_ulong_t)(_info), \ 33 } 34 35 #define INTEL_QUANTA_VGA_DEVICE(_info) { \ 36 .vendor = PCI_VENDOR_ID_INTEL, .device = 0x16a, \ 37 .subvendor = 0x152d, .subdevice = 0x8990, \ 38 .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \ 39 .driver_data = (kernel_ulong_t)(_info), \ 40 } 41 #endif 42 43 #define INTEL_I810_IDS(MACRO__, ...) \ 44 MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \ 45 MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \ 46 MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */ 47 48 #define INTEL_I815_IDS(MACRO__, ...) \ 49 MACRO__(0x1132, ## __VA_ARGS__) /* I815*/ 50 51 #define INTEL_I830_IDS(MACRO__, ...) \ 52 MACRO__(0x3577, ## __VA_ARGS__) 53 54 #define INTEL_I845G_IDS(MACRO__, ...) \ 55 MACRO__(0x2562, ## __VA_ARGS__) 56 57 #define INTEL_I85X_IDS(MACRO__, ...) \ 58 MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \ 59 MACRO__(0x358e, ## __VA_ARGS__) 60 61 #define INTEL_I865G_IDS(MACRO__, ...) \ 62 MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */ 63 64 #define INTEL_I915G_IDS(MACRO__, ...) \ 65 MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \ 66 MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */ 67 68 #define INTEL_I915GM_IDS(MACRO__, ...) \ 69 MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */ 70 71 #define INTEL_I945G_IDS(MACRO__, ...) \ 72 MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */ 73 74 #define INTEL_I945GM_IDS(MACRO__, ...) \ 75 MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \ 76 MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */ 77 78 #define INTEL_I965G_IDS(MACRO__, ...) \ 79 MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \ 80 MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \ 81 MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \ 82 MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */ 83 84 #define INTEL_G33_IDS(MACRO__, ...) \ 85 MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \ 86 MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \ 87 MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */ 88 89 #define INTEL_I965GM_IDS(MACRO__, ...) \ 90 MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \ 91 MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */ 92 93 #define INTEL_GM45_IDS(MACRO__, ...) \ 94 MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */ 95 96 #define INTEL_G45_IDS(MACRO__, ...) \ 97 MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \ 98 MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \ 99 MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \ 100 MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \ 101 MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \ 102 MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */ 103 104 #define INTEL_PNV_G_IDS(MACRO__, ...) \ 105 MACRO__(0xa001, ## __VA_ARGS__) 106 107 #define INTEL_PNV_M_IDS(MACRO__, ...) \ 108 MACRO__(0xa011, ## __VA_ARGS__) 109 110 #define INTEL_PNV_IDS(MACRO__, ...) \ 111 INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \ 112 INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__) 113 114 #define INTEL_ILK_D_IDS(MACRO__, ...) \ 115 MACRO__(0x0042, ## __VA_ARGS__) 116 117 #define INTEL_ILK_M_IDS(MACRO__, ...) \ 118 MACRO__(0x0046, ## __VA_ARGS__) 119 120 #define INTEL_ILK_IDS(MACRO__, ...) \ 121 INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \ 122 INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__) 123 124 #define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \ 125 MACRO__(0x0102, ## __VA_ARGS__), \ 126 MACRO__(0x010A, ## __VA_ARGS__) 127 128 #define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \ 129 MACRO__(0x0112, ## __VA_ARGS__), \ 130 MACRO__(0x0122, ## __VA_ARGS__) 131 132 #define INTEL_SNB_D_IDS(MACRO__, ...) \ 133 INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 134 INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) 135 136 #define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \ 137 MACRO__(0x0106, ## __VA_ARGS__) 138 139 #define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \ 140 MACRO__(0x0116, ## __VA_ARGS__), \ 141 MACRO__(0x0126, ## __VA_ARGS__) 142 143 #define INTEL_SNB_M_IDS(MACRO__, ...) \ 144 INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 145 INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) 146 147 #define INTEL_SNB_IDS(MACRO__, ...) \ 148 INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \ 149 INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__) 150 151 #define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \ 152 MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */ 153 154 #define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \ 155 MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */ 156 157 #define INTEL_IVB_M_IDS(MACRO__, ...) \ 158 INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 159 INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) 160 161 #define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \ 162 MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \ 163 MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */ 164 165 #define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \ 166 MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \ 167 MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */ 168 169 #define INTEL_IVB_D_IDS(MACRO__, ...) \ 170 INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 171 INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) 172 173 #define INTEL_IVB_IDS(MACRO__, ...) \ 174 INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \ 175 INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__) 176 177 #define INTEL_IVB_Q_IDS(MACRO__, ...) \ 178 INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */ 179 180 #define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \ 181 MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \ 182 MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \ 183 MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \ 184 MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */ 185 186 #define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \ 187 MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */ 188 189 #define INTEL_HSW_GT1_IDS(MACRO__, ...) \ 190 INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 191 INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 192 MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \ 193 MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \ 194 MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \ 195 MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \ 196 MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \ 197 MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \ 198 MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \ 199 MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \ 200 MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \ 201 MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \ 202 MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \ 203 MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \ 204 MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \ 205 MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \ 206 MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */ 207 208 #define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \ 209 MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \ 210 MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \ 211 MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \ 212 MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \ 213 214 #define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \ 215 MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \ 216 217 #define INTEL_HSW_GT2_IDS(MACRO__, ...) \ 218 INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 219 INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 220 MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \ 221 MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \ 222 MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \ 223 MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \ 224 MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \ 225 MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \ 226 MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \ 227 MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \ 228 MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \ 229 MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \ 230 MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \ 231 MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \ 232 MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \ 233 MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \ 234 MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */ 235 236 #define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \ 237 MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \ 238 MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \ 239 MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \ 240 MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \ 241 MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */ 242 243 #define INTEL_HSW_GT3_IDS(MACRO__, ...) \ 244 INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 245 MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \ 246 MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \ 247 MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \ 248 MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \ 249 MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \ 250 MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \ 251 MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \ 252 MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \ 253 MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \ 254 MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \ 255 MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \ 256 MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \ 257 MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \ 258 MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \ 259 MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */ 260 261 #define INTEL_HSW_IDS(MACRO__, ...) \ 262 INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 263 INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 264 INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__) 265 266 #define INTEL_VLV_IDS(MACRO__, ...) \ 267 MACRO__(0x0f30, ## __VA_ARGS__), \ 268 MACRO__(0x0f31, ## __VA_ARGS__), \ 269 MACRO__(0x0f32, ## __VA_ARGS__), \ 270 MACRO__(0x0f33, ## __VA_ARGS__) 271 272 #define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \ 273 MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \ 274 MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */ 275 276 #define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \ 277 MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */ 278 279 #define INTEL_BDW_GT1_IDS(MACRO__, ...) \ 280 INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 281 INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 282 MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \ 283 MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \ 284 MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */ 285 286 #define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \ 287 MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \ 288 MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */ 289 290 #define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \ 291 MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */ 292 293 #define INTEL_BDW_GT2_IDS(MACRO__, ...) \ 294 INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 295 INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 296 MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \ 297 MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \ 298 MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */ 299 300 #define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \ 301 MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \ 302 MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \ 303 304 #define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \ 305 MACRO__(0x162E, ## __VA_ARGS__) /* ULX */ 306 307 #define INTEL_BDW_GT3_IDS(MACRO__, ...) \ 308 INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 309 INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 310 MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \ 311 MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \ 312 MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */ 313 314 #define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \ 315 MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \ 316 MACRO__(0x163B, ## __VA_ARGS__) /* Iris */ 317 318 #define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \ 319 MACRO__(0x163E, ## __VA_ARGS__) /* ULX */ 320 321 #define INTEL_BDW_RSVD_IDS(MACRO__, ...) \ 322 INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ 323 INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ 324 MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \ 325 MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \ 326 MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */ 327 328 #define INTEL_BDW_IDS(MACRO__, ...) \ 329 INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 330 INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 331 INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 332 INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__) 333 334 #define INTEL_CHV_IDS(MACRO__, ...) \ 335 MACRO__(0x22b0, ## __VA_ARGS__), \ 336 MACRO__(0x22b1, ## __VA_ARGS__), \ 337 MACRO__(0x22b2, ## __VA_ARGS__), \ 338 MACRO__(0x22b3, ## __VA_ARGS__) 339 340 #define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \ 341 MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \ 342 MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */ 343 344 #define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \ 345 MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \ 346 MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */ 347 348 #define INTEL_SKL_GT1_IDS(MACRO__, ...) \ 349 INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 350 INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 351 MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \ 352 MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \ 353 MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \ 354 MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */ 355 356 #define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \ 357 MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \ 358 MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */ 359 360 #define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \ 361 MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */ 362 363 #define INTEL_SKL_GT2_IDS(MACRO__, ...) \ 364 INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 365 INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 366 MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \ 367 MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \ 368 MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \ 369 MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */ 370 371 #define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \ 372 MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \ 373 MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \ 374 MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */ 375 376 #define INTEL_SKL_GT3_IDS(MACRO__, ...) \ 377 INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 378 MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \ 379 MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \ 380 MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */ 381 382 #define INTEL_SKL_GT4_IDS(MACRO__, ...) \ 383 MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \ 384 MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \ 385 MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \ 386 MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */ 387 388 #define INTEL_SKL_IDS(MACRO__, ...) \ 389 INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 390 INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 391 INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 392 INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__) 393 394 #define INTEL_BXT_IDS(MACRO__, ...) \ 395 MACRO__(0x0A84, ## __VA_ARGS__), \ 396 MACRO__(0x1A84, ## __VA_ARGS__), \ 397 MACRO__(0x1A85, ## __VA_ARGS__), \ 398 MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \ 399 MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */ 400 401 #define INTEL_GLK_IDS(MACRO__, ...) \ 402 MACRO__(0x3184, ## __VA_ARGS__), \ 403 MACRO__(0x3185, ## __VA_ARGS__) 404 405 #define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \ 406 MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \ 407 MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */ 408 409 #define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \ 410 MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \ 411 MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */ 412 413 #define INTEL_KBL_GT1_IDS(MACRO__, ...) \ 414 INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 415 INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 416 MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \ 417 MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \ 418 MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \ 419 MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */ 420 421 #define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \ 422 MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \ 423 MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */ 424 425 #define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \ 426 MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */ 427 428 #define INTEL_KBL_GT2_IDS(MACRO__, ...) \ 429 INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 430 INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 431 MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \ 432 MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \ 433 MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \ 434 MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \ 435 MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */ 436 437 #define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \ 438 MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */ 439 440 #define INTEL_KBL_GT3_IDS(MACRO__, ...) \ 441 INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 442 MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \ 443 MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */ 444 445 #define INTEL_KBL_GT4_IDS(MACRO__, ...) \ 446 MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */ 447 448 /* AML/KBL Y GT2 */ 449 #define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \ 450 MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \ 451 MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */ 452 453 /* AML/CFL Y GT2 */ 454 #define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \ 455 MACRO__(0x87CA, ## __VA_ARGS__) 456 457 /* CML GT1 */ 458 #define INTEL_CML_GT1_IDS(MACRO__, ...) \ 459 MACRO__(0x9BA2, ## __VA_ARGS__), \ 460 MACRO__(0x9BA4, ## __VA_ARGS__), \ 461 MACRO__(0x9BA5, ## __VA_ARGS__), \ 462 MACRO__(0x9BA8, ## __VA_ARGS__) 463 464 #define INTEL_CML_U_GT1_IDS(MACRO__, ...) \ 465 MACRO__(0x9B21, ## __VA_ARGS__), \ 466 MACRO__(0x9BAA, ## __VA_ARGS__), \ 467 MACRO__(0x9BAC, ## __VA_ARGS__) 468 469 /* CML GT2 */ 470 #define INTEL_CML_GT2_IDS(MACRO__, ...) \ 471 MACRO__(0x9BC2, ## __VA_ARGS__), \ 472 MACRO__(0x9BC4, ## __VA_ARGS__), \ 473 MACRO__(0x9BC5, ## __VA_ARGS__), \ 474 MACRO__(0x9BC6, ## __VA_ARGS__), \ 475 MACRO__(0x9BC8, ## __VA_ARGS__), \ 476 MACRO__(0x9BE6, ## __VA_ARGS__), \ 477 MACRO__(0x9BF6, ## __VA_ARGS__) 478 479 #define INTEL_CML_U_GT2_IDS(MACRO__, ...) \ 480 MACRO__(0x9B41, ## __VA_ARGS__), \ 481 MACRO__(0x9BCA, ## __VA_ARGS__), \ 482 MACRO__(0x9BCC, ## __VA_ARGS__) 483 484 #define INTEL_CML_IDS(MACRO__, ...) \ 485 INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 486 INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 487 INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 488 INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__) 489 490 #define INTEL_KBL_IDS(MACRO__, ...) \ 491 INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 492 INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 493 INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 494 INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \ 495 INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__) 496 497 /* CFL S */ 498 #define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \ 499 MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \ 500 MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \ 501 MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */ 502 503 #define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \ 504 MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \ 505 MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \ 506 MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \ 507 MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \ 508 MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */ 509 510 /* CFL H */ 511 #define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \ 512 MACRO__(0x3E9C, ## __VA_ARGS__) 513 514 #define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \ 515 MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \ 516 MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */ 517 518 /* CFL U GT2 */ 519 #define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \ 520 MACRO__(0x3EA9, ## __VA_ARGS__) 521 522 /* CFL U GT3 */ 523 #define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \ 524 MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \ 525 MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \ 526 MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \ 527 MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */ 528 529 #define INTEL_CFL_IDS(MACRO__, ...) \ 530 INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 531 INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 532 INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 533 INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 534 INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 535 INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 536 INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__) 537 538 /* WHL/CFL U GT1 */ 539 #define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \ 540 MACRO__(0x3EA1, ## __VA_ARGS__), \ 541 MACRO__(0x3EA4, ## __VA_ARGS__) 542 543 /* WHL/CFL U GT2 */ 544 #define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \ 545 MACRO__(0x3EA0, ## __VA_ARGS__), \ 546 MACRO__(0x3EA3, ## __VA_ARGS__) 547 548 /* WHL/CFL U GT3 */ 549 #define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \ 550 MACRO__(0x3EA2, ## __VA_ARGS__) 551 552 #define INTEL_WHL_IDS(MACRO__, ...) \ 553 INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 554 INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 555 INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__) 556 557 /* CNL */ 558 #define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \ 559 MACRO__(0x5A44, ## __VA_ARGS__), \ 560 MACRO__(0x5A4C, ## __VA_ARGS__), \ 561 MACRO__(0x5A54, ## __VA_ARGS__), \ 562 MACRO__(0x5A5C, ## __VA_ARGS__) 563 564 #define INTEL_CNL_IDS(MACRO__, ...) \ 565 INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ 566 MACRO__(0x5A40, ## __VA_ARGS__), \ 567 MACRO__(0x5A41, ## __VA_ARGS__), \ 568 MACRO__(0x5A42, ## __VA_ARGS__), \ 569 MACRO__(0x5A49, ## __VA_ARGS__), \ 570 MACRO__(0x5A4A, ## __VA_ARGS__), \ 571 MACRO__(0x5A50, ## __VA_ARGS__), \ 572 MACRO__(0x5A51, ## __VA_ARGS__), \ 573 MACRO__(0x5A52, ## __VA_ARGS__), \ 574 MACRO__(0x5A59, ## __VA_ARGS__), \ 575 MACRO__(0x5A5A, ## __VA_ARGS__) 576 577 /* ICL */ 578 #define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \ 579 MACRO__(0x8A50, ## __VA_ARGS__), \ 580 MACRO__(0x8A52, ## __VA_ARGS__), \ 581 MACRO__(0x8A53, ## __VA_ARGS__), \ 582 MACRO__(0x8A54, ## __VA_ARGS__), \ 583 MACRO__(0x8A56, ## __VA_ARGS__), \ 584 MACRO__(0x8A57, ## __VA_ARGS__), \ 585 MACRO__(0x8A58, ## __VA_ARGS__), \ 586 MACRO__(0x8A59, ## __VA_ARGS__), \ 587 MACRO__(0x8A5A, ## __VA_ARGS__), \ 588 MACRO__(0x8A5B, ## __VA_ARGS__), \ 589 MACRO__(0x8A5C, ## __VA_ARGS__), \ 590 MACRO__(0x8A70, ## __VA_ARGS__), \ 591 MACRO__(0x8A71, ## __VA_ARGS__) 592 593 #define INTEL_ICL_IDS(MACRO__, ...) \ 594 INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ 595 MACRO__(0x8A51, ## __VA_ARGS__), \ 596 MACRO__(0x8A5D, ## __VA_ARGS__) 597 598 /* EHL */ 599 #define INTEL_EHL_IDS(MACRO__, ...) \ 600 MACRO__(0x4541, ## __VA_ARGS__), \ 601 MACRO__(0x4551, ## __VA_ARGS__), \ 602 MACRO__(0x4555, ## __VA_ARGS__), \ 603 MACRO__(0x4557, ## __VA_ARGS__), \ 604 MACRO__(0x4570, ## __VA_ARGS__), \ 605 MACRO__(0x4571, ## __VA_ARGS__) 606 607 /* JSL */ 608 #define INTEL_JSL_IDS(MACRO__, ...) \ 609 MACRO__(0x4E51, ## __VA_ARGS__), \ 610 MACRO__(0x4E55, ## __VA_ARGS__), \ 611 MACRO__(0x4E57, ## __VA_ARGS__), \ 612 MACRO__(0x4E61, ## __VA_ARGS__), \ 613 MACRO__(0x4E71, ## __VA_ARGS__) 614 615 /* TGL */ 616 #define INTEL_TGL_GT1_IDS(MACRO__, ...) \ 617 MACRO__(0x9A60, ## __VA_ARGS__), \ 618 MACRO__(0x9A68, ## __VA_ARGS__), \ 619 MACRO__(0x9A70, ## __VA_ARGS__) 620 621 #define INTEL_TGL_GT2_IDS(MACRO__, ...) \ 622 MACRO__(0x9A40, ## __VA_ARGS__), \ 623 MACRO__(0x9A49, ## __VA_ARGS__), \ 624 MACRO__(0x9A59, ## __VA_ARGS__), \ 625 MACRO__(0x9A78, ## __VA_ARGS__), \ 626 MACRO__(0x9AC0, ## __VA_ARGS__), \ 627 MACRO__(0x9AC9, ## __VA_ARGS__), \ 628 MACRO__(0x9AD9, ## __VA_ARGS__), \ 629 MACRO__(0x9AF8, ## __VA_ARGS__) 630 631 #define INTEL_TGL_IDS(MACRO__, ...) \ 632 INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 633 INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__) 634 635 /* RKL */ 636 #define INTEL_RKL_IDS(MACRO__, ...) \ 637 MACRO__(0x4C80, ## __VA_ARGS__), \ 638 MACRO__(0x4C8A, ## __VA_ARGS__), \ 639 MACRO__(0x4C8B, ## __VA_ARGS__), \ 640 MACRO__(0x4C8C, ## __VA_ARGS__), \ 641 MACRO__(0x4C90, ## __VA_ARGS__), \ 642 MACRO__(0x4C9A, ## __VA_ARGS__) 643 644 /* DG1 */ 645 #define INTEL_DG1_IDS(MACRO__, ...) \ 646 MACRO__(0x4905, ## __VA_ARGS__), \ 647 MACRO__(0x4906, ## __VA_ARGS__), \ 648 MACRO__(0x4907, ## __VA_ARGS__), \ 649 MACRO__(0x4908, ## __VA_ARGS__), \ 650 MACRO__(0x4909, ## __VA_ARGS__) 651 652 /* ADL-S */ 653 #define INTEL_ADLS_IDS(MACRO__, ...) \ 654 MACRO__(0x4680, ## __VA_ARGS__), \ 655 MACRO__(0x4682, ## __VA_ARGS__), \ 656 MACRO__(0x4688, ## __VA_ARGS__), \ 657 MACRO__(0x468A, ## __VA_ARGS__), \ 658 MACRO__(0x468B, ## __VA_ARGS__), \ 659 MACRO__(0x4690, ## __VA_ARGS__), \ 660 MACRO__(0x4692, ## __VA_ARGS__), \ 661 MACRO__(0x4693, ## __VA_ARGS__) 662 663 /* ADL-P */ 664 #define INTEL_ADLP_IDS(MACRO__, ...) \ 665 MACRO__(0x46A0, ## __VA_ARGS__), \ 666 MACRO__(0x46A1, ## __VA_ARGS__), \ 667 MACRO__(0x46A2, ## __VA_ARGS__), \ 668 MACRO__(0x46A3, ## __VA_ARGS__), \ 669 MACRO__(0x46A6, ## __VA_ARGS__), \ 670 MACRO__(0x46A8, ## __VA_ARGS__), \ 671 MACRO__(0x46AA, ## __VA_ARGS__), \ 672 MACRO__(0x462A, ## __VA_ARGS__), \ 673 MACRO__(0x4626, ## __VA_ARGS__), \ 674 MACRO__(0x4628, ## __VA_ARGS__), \ 675 MACRO__(0x46B0, ## __VA_ARGS__), \ 676 MACRO__(0x46B1, ## __VA_ARGS__), \ 677 MACRO__(0x46B2, ## __VA_ARGS__), \ 678 MACRO__(0x46B3, ## __VA_ARGS__), \ 679 MACRO__(0x46C0, ## __VA_ARGS__), \ 680 MACRO__(0x46C1, ## __VA_ARGS__), \ 681 MACRO__(0x46C2, ## __VA_ARGS__), \ 682 MACRO__(0x46C3, ## __VA_ARGS__) 683 684 /* ADL-N */ 685 #define INTEL_ADLN_IDS(MACRO__, ...) \ 686 MACRO__(0x46D0, ## __VA_ARGS__), \ 687 MACRO__(0x46D1, ## __VA_ARGS__), \ 688 MACRO__(0x46D2, ## __VA_ARGS__), \ 689 MACRO__(0x46D3, ## __VA_ARGS__), \ 690 MACRO__(0x46D4, ## __VA_ARGS__) 691 692 /* RPL-S */ 693 #define INTEL_RPLS_IDS(MACRO__, ...) \ 694 MACRO__(0xA780, ## __VA_ARGS__), \ 695 MACRO__(0xA781, ## __VA_ARGS__), \ 696 MACRO__(0xA782, ## __VA_ARGS__), \ 697 MACRO__(0xA783, ## __VA_ARGS__), \ 698 MACRO__(0xA788, ## __VA_ARGS__), \ 699 MACRO__(0xA789, ## __VA_ARGS__), \ 700 MACRO__(0xA78A, ## __VA_ARGS__), \ 701 MACRO__(0xA78B, ## __VA_ARGS__) 702 703 /* RPL-U */ 704 #define INTEL_RPLU_IDS(MACRO__, ...) \ 705 MACRO__(0xA721, ## __VA_ARGS__), \ 706 MACRO__(0xA7A1, ## __VA_ARGS__), \ 707 MACRO__(0xA7A9, ## __VA_ARGS__), \ 708 MACRO__(0xA7AC, ## __VA_ARGS__), \ 709 MACRO__(0xA7AD, ## __VA_ARGS__) 710 711 /* RPL-P */ 712 #define INTEL_RPLP_IDS(MACRO__, ...) \ 713 MACRO__(0xA720, ## __VA_ARGS__), \ 714 MACRO__(0xA7A0, ## __VA_ARGS__), \ 715 MACRO__(0xA7A8, ## __VA_ARGS__), \ 716 MACRO__(0xA7AA, ## __VA_ARGS__), \ 717 MACRO__(0xA7AB, ## __VA_ARGS__) 718 719 /* DG2 */ 720 #define INTEL_DG2_G10_IDS(MACRO__, ...) \ 721 MACRO__(0x5690, ## __VA_ARGS__), \ 722 MACRO__(0x5691, ## __VA_ARGS__), \ 723 MACRO__(0x5692, ## __VA_ARGS__), \ 724 MACRO__(0x56A0, ## __VA_ARGS__), \ 725 MACRO__(0x56A1, ## __VA_ARGS__), \ 726 MACRO__(0x56A2, ## __VA_ARGS__), \ 727 MACRO__(0x56BE, ## __VA_ARGS__), \ 728 MACRO__(0x56BF, ## __VA_ARGS__) 729 730 #define INTEL_DG2_G11_IDS(MACRO__, ...) \ 731 MACRO__(0x5693, ## __VA_ARGS__), \ 732 MACRO__(0x5694, ## __VA_ARGS__), \ 733 MACRO__(0x5695, ## __VA_ARGS__), \ 734 MACRO__(0x56A5, ## __VA_ARGS__), \ 735 MACRO__(0x56A6, ## __VA_ARGS__), \ 736 MACRO__(0x56B0, ## __VA_ARGS__), \ 737 MACRO__(0x56B1, ## __VA_ARGS__), \ 738 MACRO__(0x56BA, ## __VA_ARGS__), \ 739 MACRO__(0x56BB, ## __VA_ARGS__), \ 740 MACRO__(0x56BC, ## __VA_ARGS__), \ 741 MACRO__(0x56BD, ## __VA_ARGS__) 742 743 #define INTEL_DG2_G12_IDS(MACRO__, ...) \ 744 MACRO__(0x5696, ## __VA_ARGS__), \ 745 MACRO__(0x5697, ## __VA_ARGS__), \ 746 MACRO__(0x56A3, ## __VA_ARGS__), \ 747 MACRO__(0x56A4, ## __VA_ARGS__), \ 748 MACRO__(0x56B2, ## __VA_ARGS__), \ 749 MACRO__(0x56B3, ## __VA_ARGS__) 750 751 #define INTEL_DG2_IDS(MACRO__, ...) \ 752 INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \ 753 INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \ 754 INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) 755 756 #define INTEL_ATS_M150_IDS(MACRO__, ...) \ 757 MACRO__(0x56C0, ## __VA_ARGS__), \ 758 MACRO__(0x56C2, ## __VA_ARGS__) 759 760 #define INTEL_ATS_M75_IDS(MACRO__, ...) \ 761 MACRO__(0x56C1, ## __VA_ARGS__) 762 763 #define INTEL_ATS_M_IDS(MACRO__, ...) \ 764 INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \ 765 INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) 766 767 /* ARL */ 768 #define INTEL_ARL_IDS(MACRO__, ...) \ 769 MACRO__(0x7D41, ## __VA_ARGS__), \ 770 MACRO__(0x7D51, ## __VA_ARGS__), \ 771 MACRO__(0x7D67, ## __VA_ARGS__), \ 772 MACRO__(0x7DD1, ## __VA_ARGS__), \ 773 MACRO__(0xB640, ## __VA_ARGS__) 774 775 /* MTL */ 776 #define INTEL_MTL_IDS(MACRO__, ...) \ 777 MACRO__(0x7D40, ## __VA_ARGS__), \ 778 MACRO__(0x7D45, ## __VA_ARGS__), \ 779 MACRO__(0x7D55, ## __VA_ARGS__), \ 780 MACRO__(0x7D60, ## __VA_ARGS__), \ 781 MACRO__(0x7DD5, ## __VA_ARGS__) 782 783 /* PVC */ 784 #define INTEL_PVC_IDS(MACRO__, ...) \ 785 MACRO__(0x0B69, ## __VA_ARGS__), \ 786 MACRO__(0x0B6E, ## __VA_ARGS__), \ 787 MACRO__(0x0BD4, ## __VA_ARGS__), \ 788 MACRO__(0x0BD5, ## __VA_ARGS__), \ 789 MACRO__(0x0BD6, ## __VA_ARGS__), \ 790 MACRO__(0x0BD7, ## __VA_ARGS__), \ 791 MACRO__(0x0BD8, ## __VA_ARGS__), \ 792 MACRO__(0x0BD9, ## __VA_ARGS__), \ 793 MACRO__(0x0BDA, ## __VA_ARGS__), \ 794 MACRO__(0x0BDB, ## __VA_ARGS__), \ 795 MACRO__(0x0BE0, ## __VA_ARGS__), \ 796 MACRO__(0x0BE1, ## __VA_ARGS__), \ 797 MACRO__(0x0BE5, ## __VA_ARGS__) 798 799 /* LNL */ 800 #define INTEL_LNL_IDS(MACRO__, ...) \ 801 MACRO__(0x6420, ## __VA_ARGS__), \ 802 MACRO__(0x64A0, ## __VA_ARGS__), \ 803 MACRO__(0x64B0, ## __VA_ARGS__) 804 805 /* BMG */ 806 #define INTEL_BMG_IDS(MACRO__, ...) \ 807 MACRO__(0xE202, ## __VA_ARGS__), \ 808 MACRO__(0xE20B, ## __VA_ARGS__), \ 809 MACRO__(0xE20C, ## __VA_ARGS__), \ 810 MACRO__(0xE20D, ## __VA_ARGS__), \ 811 MACRO__(0xE212, ## __VA_ARGS__) 812 813 /* PTL */ 814 #define INTEL_PTL_IDS(MACRO__, ...) \ 815 MACRO__(0xB080, ## __VA_ARGS__), \ 816 MACRO__(0xB081, ## __VA_ARGS__), \ 817 MACRO__(0xB082, ## __VA_ARGS__), \ 818 MACRO__(0xB090, ## __VA_ARGS__), \ 819 MACRO__(0xB091, ## __VA_ARGS__), \ 820 MACRO__(0xB092, ## __VA_ARGS__), \ 821 MACRO__(0xB0A0, ## __VA_ARGS__), \ 822 MACRO__(0xB0A1, ## __VA_ARGS__), \ 823 MACRO__(0xB0A2, ## __VA_ARGS__) 824 825 #endif /* __PCIIDS_H__ */ 826