1*8b1858aaSJani Nikula /* SPDX-License-Identifier: MIT */ 2*8b1858aaSJani Nikula /* 3*8b1858aaSJani Nikula * Copyright © 2022 Intel Corporation 4*8b1858aaSJani Nikula */ 5*8b1858aaSJani Nikula 6*8b1858aaSJani Nikula #ifndef __INTEL_PCI_CONFIG_H__ 7*8b1858aaSJani Nikula #define __INTEL_PCI_CONFIG_H__ 8*8b1858aaSJani Nikula 9*8b1858aaSJani Nikula /* PCI BARs */ 10*8b1858aaSJani Nikula #define GEN2_GMADR_BAR 0 11*8b1858aaSJani Nikula #define GEN2_MMADR_BAR 1 /* MMIO+GTT, despite the name */ 12*8b1858aaSJani Nikula #define GEN2_IO_BAR 2 /* 85x/865 */ 13*8b1858aaSJani Nikula 14*8b1858aaSJani Nikula #define GEN3_MMADR_BAR 0 /* MMIO only */ 15*8b1858aaSJani Nikula #define GEN3_IO_BAR 1 16*8b1858aaSJani Nikula #define GEN3_GMADR_BAR 2 17*8b1858aaSJani Nikula #define GEN3_GTTADR_BAR 3 /* GTT only */ 18*8b1858aaSJani Nikula 19*8b1858aaSJani Nikula #define GEN4_GTTMMADR_BAR 0 /* MMIO+GTT */ 20*8b1858aaSJani Nikula #define GEN4_GMADR_BAR 2 21*8b1858aaSJani Nikula #define GEN4_IO_BAR 4 22*8b1858aaSJani Nikula 23*8b1858aaSJani Nikula #define GEN12_LMEM_BAR 2 24*8b1858aaSJani Nikula 25*8b1858aaSJani Nikula static inline int intel_mmio_bar(int graphics_ver) 26*8b1858aaSJani Nikula { 27*8b1858aaSJani Nikula switch (graphics_ver) { 28*8b1858aaSJani Nikula case 2: return GEN2_MMADR_BAR; 29*8b1858aaSJani Nikula case 3: return GEN3_MMADR_BAR; 30*8b1858aaSJani Nikula default: return GEN4_GTTMMADR_BAR; 31*8b1858aaSJani Nikula } 32*8b1858aaSJani Nikula } 33*8b1858aaSJani Nikula 34*8b1858aaSJani Nikula /* BSM in include/drm/intel/i915_drm.h */ 35*8b1858aaSJani Nikula 36*8b1858aaSJani Nikula #define MCHBAR_I915 0x44 37*8b1858aaSJani Nikula #define MCHBAR_I965 0x48 38*8b1858aaSJani Nikula #define MCHBAR_SIZE (4 * 4096) 39*8b1858aaSJani Nikula 40*8b1858aaSJani Nikula #define DEVEN 0x54 41*8b1858aaSJani Nikula #define DEVEN_MCHBAR_EN (1 << 28) 42*8b1858aaSJani Nikula 43*8b1858aaSJani Nikula #define HPLLCC 0xc0 /* 85x only */ 44*8b1858aaSJani Nikula #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 45*8b1858aaSJani Nikula #define GC_CLOCK_133_200 (0 << 0) 46*8b1858aaSJani Nikula #define GC_CLOCK_100_200 (1 << 0) 47*8b1858aaSJani Nikula #define GC_CLOCK_100_133 (2 << 0) 48*8b1858aaSJani Nikula #define GC_CLOCK_133_266 (3 << 0) 49*8b1858aaSJani Nikula #define GC_CLOCK_133_200_2 (4 << 0) 50*8b1858aaSJani Nikula #define GC_CLOCK_133_266_2 (5 << 0) 51*8b1858aaSJani Nikula #define GC_CLOCK_166_266 (6 << 0) 52*8b1858aaSJani Nikula #define GC_CLOCK_166_250 (7 << 0) 53*8b1858aaSJani Nikula 54*8b1858aaSJani Nikula #define I915_GDRST 0xc0 55*8b1858aaSJani Nikula #define GRDOM_FULL (0 << 2) 56*8b1858aaSJani Nikula #define GRDOM_RENDER (1 << 2) 57*8b1858aaSJani Nikula #define GRDOM_MEDIA (3 << 2) 58*8b1858aaSJani Nikula #define GRDOM_MASK (3 << 2) 59*8b1858aaSJani Nikula #define GRDOM_RESET_STATUS (1 << 1) 60*8b1858aaSJani Nikula #define GRDOM_RESET_ENABLE (1 << 0) 61*8b1858aaSJani Nikula 62*8b1858aaSJani Nikula /* BSpec only has register offset, PCI device and bit found empirically */ 63*8b1858aaSJani Nikula #define I830_CLOCK_GATE 0xc8 /* device 0 */ 64*8b1858aaSJani Nikula #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) 65*8b1858aaSJani Nikula 66*8b1858aaSJani Nikula #define GCDGMBUS 0xcc 67*8b1858aaSJani Nikula 68*8b1858aaSJani Nikula #define GCFGC2 0xda 69*8b1858aaSJani Nikula #define GCFGC 0xf0 /* 915+ only */ 70*8b1858aaSJani Nikula #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 71*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 72*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 73*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 74*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 75*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 76*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 77*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 78*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 79*8b1858aaSJani Nikula #define GC_DISPLAY_CLOCK_MASK (7 << 4) 80*8b1858aaSJani Nikula #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 81*8b1858aaSJani Nikula #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 82*8b1858aaSJani Nikula #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 83*8b1858aaSJani Nikula #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 84*8b1858aaSJani Nikula #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 85*8b1858aaSJani Nikula #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 86*8b1858aaSJani Nikula #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 87*8b1858aaSJani Nikula #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 88*8b1858aaSJani Nikula #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 89*8b1858aaSJani Nikula #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 90*8b1858aaSJani Nikula #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 91*8b1858aaSJani Nikula #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 92*8b1858aaSJani Nikula #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 93*8b1858aaSJani Nikula #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 94*8b1858aaSJani Nikula #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 95*8b1858aaSJani Nikula #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 96*8b1858aaSJani Nikula #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 97*8b1858aaSJani Nikula #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 98*8b1858aaSJani Nikula #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 99*8b1858aaSJani Nikula 100*8b1858aaSJani Nikula #define ASLE 0xe4 101*8b1858aaSJani Nikula #define ASLS 0xfc 102*8b1858aaSJani Nikula 103*8b1858aaSJani Nikula #define SWSCI 0xe8 104*8b1858aaSJani Nikula #define SWSCI_SCISEL (1 << 15) 105*8b1858aaSJani Nikula #define SWSCI_GSSCIE (1 << 0) 106*8b1858aaSJani Nikula 107*8b1858aaSJani Nikula /* legacy/combination backlight modes, also called LBB */ 108*8b1858aaSJani Nikula #define LBPC 0xf4 109*8b1858aaSJani Nikula 110*8b1858aaSJani Nikula #endif /* __INTEL_PCI_CONFIG_H__ */ 111