1 /* 2 * Copyright © 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __DRM_EDID_H__ 24 #define __DRM_EDID_H__ 25 26 #include <linux/types.h> 27 28 enum hdmi_quantization_range; 29 struct drm_connector; 30 struct drm_device; 31 struct drm_display_mode; 32 struct drm_edid; 33 struct drm_printer; 34 struct hdmi_avi_infoframe; 35 struct hdmi_vendor_infoframe; 36 struct i2c_adapter; 37 38 #define EDID_LENGTH 128 39 #define DDC_ADDR 0x50 40 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 41 42 #define CEA_EXT 0x02 43 #define VTB_EXT 0x10 44 #define DI_EXT 0x40 45 #define LS_EXT 0x50 46 #define MI_EXT 0x60 47 #define DISPLAYID_EXT 0x70 48 49 struct est_timings { 50 u8 t1; 51 u8 t2; 52 u8 mfg_rsvd; 53 } __packed; 54 55 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 56 #define EDID_TIMING_ASPECT_SHIFT 6 57 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 58 59 /* need to add 60 */ 60 #define EDID_TIMING_VFREQ_SHIFT 0 61 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 62 63 struct std_timing { 64 u8 hsize; /* need to multiply by 8 then add 248 */ 65 u8 vfreq_aspect; 66 } __packed; 67 68 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 69 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 70 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 71 #define DRM_EDID_PT_STEREO (1 << 5) 72 #define DRM_EDID_PT_INTERLACED (1 << 7) 73 74 /* If detailed data is pixel timing */ 75 struct detailed_pixel_timing { 76 u8 hactive_lo; 77 u8 hblank_lo; 78 u8 hactive_hblank_hi; 79 u8 vactive_lo; 80 u8 vblank_lo; 81 u8 vactive_vblank_hi; 82 u8 hsync_offset_lo; 83 u8 hsync_pulse_width_lo; 84 u8 vsync_offset_pulse_width_lo; 85 u8 hsync_vsync_offset_pulse_width_hi; 86 u8 width_mm_lo; 87 u8 height_mm_lo; 88 u8 width_height_mm_hi; 89 u8 hborder; 90 u8 vborder; 91 u8 misc; 92 } __packed; 93 94 /* If it's not pixel timing, it'll be one of the below */ 95 struct detailed_data_string { 96 u8 str[13]; 97 } __packed; 98 99 #define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */ 100 #define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */ 101 #define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */ 102 #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ 103 104 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 /* 1.3 */ 105 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 /* 1.4 */ 106 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 /* 1.3 */ 107 #define DRM_EDID_CVT_SUPPORT_FLAG 0x04 /* 1.4 */ 108 109 #define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING (1 << 3) 110 #define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING (1 << 4) 111 112 struct detailed_data_monitor_range { 113 u8 min_vfreq; 114 u8 max_vfreq; 115 u8 min_hfreq_khz; 116 u8 max_hfreq_khz; 117 u8 pixel_clock_mhz; /* need to multiply by 10 */ 118 u8 flags; 119 union { 120 struct { 121 u8 reserved; 122 u8 hfreq_start_khz; /* need to multiply by 2 */ 123 u8 c; /* need to divide by 2 */ 124 __le16 m; 125 u8 k; 126 u8 j; /* need to divide by 2 */ 127 } __packed gtf2; 128 struct { 129 u8 version; 130 u8 data1; /* high 6 bits: extra clock resolution */ 131 u8 data2; /* plus low 2 of above: max hactive */ 132 u8 supported_aspects; 133 u8 flags; /* preferred aspect and blanking support */ 134 u8 supported_scalings; 135 u8 preferred_refresh; 136 } __packed cvt; 137 } __packed formula; 138 } __packed; 139 140 struct detailed_data_wpindex { 141 u8 white_yx_lo; /* Lower 2 bits each */ 142 u8 white_x_hi; 143 u8 white_y_hi; 144 u8 gamma; /* need to divide by 100 then add 1 */ 145 } __packed; 146 147 struct detailed_data_color_point { 148 u8 windex1; 149 u8 wpindex1[3]; 150 u8 windex2; 151 u8 wpindex2[3]; 152 } __packed; 153 154 struct cvt_timing { 155 u8 code[3]; 156 } __packed; 157 158 struct detailed_non_pixel { 159 u8 pad1; 160 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 161 fb=color point data, fa=standard timing data, 162 f9=undefined, f8=mfg. reserved */ 163 u8 pad2; 164 union { 165 struct detailed_data_string str; 166 struct detailed_data_monitor_range range; 167 struct detailed_data_wpindex color; 168 struct std_timing timings[6]; 169 struct cvt_timing cvt[4]; 170 } __packed data; 171 } __packed; 172 173 #define EDID_DETAIL_EST_TIMINGS 0xf7 174 #define EDID_DETAIL_CVT_3BYTE 0xf8 175 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 176 #define EDID_DETAIL_STD_MODES 0xfa 177 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 178 #define EDID_DETAIL_MONITOR_NAME 0xfc 179 #define EDID_DETAIL_MONITOR_RANGE 0xfd 180 #define EDID_DETAIL_MONITOR_STRING 0xfe 181 #define EDID_DETAIL_MONITOR_SERIAL 0xff 182 183 struct detailed_timing { 184 __le16 pixel_clock; /* need to multiply by 10 KHz */ 185 union { 186 struct detailed_pixel_timing pixel_data; 187 struct detailed_non_pixel other_data; 188 } __packed data; 189 } __packed; 190 191 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 192 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 193 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 194 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 195 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 196 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 197 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 198 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ 199 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ 200 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ 201 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ 202 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ 203 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ 204 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ 205 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ 206 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ 207 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ 208 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ 209 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ 210 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ 211 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ 212 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ 213 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ 214 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ 215 216 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) /* 1.2 */ 217 #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ 218 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 219 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 220 /* If analog */ 221 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 222 /* If digital */ 223 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 224 #define DRM_EDID_FEATURE_RGB (0 << 3) 225 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 226 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 227 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 228 229 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 230 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 231 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 232 233 #define DRM_EDID_HDMI_DC_48 (1 << 6) 234 #define DRM_EDID_HDMI_DC_36 (1 << 5) 235 #define DRM_EDID_HDMI_DC_30 (1 << 4) 236 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 237 238 /* YCBCR 420 deep color modes */ 239 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 240 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 241 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 242 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 243 DRM_EDID_YCBCR420_DC_36 | \ 244 DRM_EDID_YCBCR420_DC_30) 245 246 /* HDMI 2.1 additional fields */ 247 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 248 #define DRM_EDID_FAPA_START_LOCATION (1 << 0) 249 #define DRM_EDID_ALLM (1 << 1) 250 #define DRM_EDID_FVA (1 << 2) 251 252 /* Deep Color specific */ 253 #define DRM_EDID_DC_30BIT_420 (1 << 0) 254 #define DRM_EDID_DC_36BIT_420 (1 << 1) 255 #define DRM_EDID_DC_48BIT_420 (1 << 2) 256 257 /* VRR specific */ 258 #define DRM_EDID_CNMVRR (1 << 3) 259 #define DRM_EDID_CINEMA_VRR (1 << 4) 260 #define DRM_EDID_MDELTA (1 << 5) 261 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 262 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff 263 #define DRM_EDID_VRR_MIN_MASK 0x3f 264 265 /* DSC specific */ 266 #define DRM_EDID_DSC_10BPC (1 << 0) 267 #define DRM_EDID_DSC_12BPC (1 << 1) 268 #define DRM_EDID_DSC_16BPC (1 << 2) 269 #define DRM_EDID_DSC_ALL_BPP (1 << 3) 270 #define DRM_EDID_DSC_NATIVE_420 (1 << 6) 271 #define DRM_EDID_DSC_1P2 (1 << 7) 272 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 273 #define DRM_EDID_DSC_MAX_SLICES 0xf 274 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f 275 276 struct drm_edid_product_id { 277 __be16 manufacturer_name; 278 __le16 product_code; 279 __le32 serial_number; 280 u8 week_of_manufacture; 281 u8 year_of_manufacture; 282 } __packed; 283 284 struct edid { 285 u8 header[8]; 286 /* Vendor & product info */ 287 union { 288 struct drm_edid_product_id product_id; 289 struct { 290 u8 mfg_id[2]; 291 u8 prod_code[2]; 292 u32 serial; /* FIXME: byte order */ 293 u8 mfg_week; 294 u8 mfg_year; 295 } __packed; 296 } __packed; 297 /* EDID version */ 298 u8 version; 299 u8 revision; 300 /* Display info: */ 301 u8 input; 302 u8 width_cm; 303 u8 height_cm; 304 u8 gamma; 305 u8 features; 306 /* Color characteristics */ 307 u8 red_green_lo; 308 u8 blue_white_lo; 309 u8 red_x; 310 u8 red_y; 311 u8 green_x; 312 u8 green_y; 313 u8 blue_x; 314 u8 blue_y; 315 u8 white_x; 316 u8 white_y; 317 /* Est. timings and mfg rsvd timings*/ 318 struct est_timings established_timings; 319 /* Standard timings 1-8*/ 320 struct std_timing standard_timings[8]; 321 /* Detailing timings 1-4 */ 322 struct detailed_timing detailed_timings[4]; 323 /* Number of 128 byte ext. blocks */ 324 u8 extensions; 325 /* Checksum */ 326 u8 checksum; 327 } __packed; 328 329 /* EDID matching */ 330 struct drm_edid_ident { 331 /* ID encoded by drm_edid_encode_panel_id() */ 332 u32 panel_id; 333 const char *name; 334 }; 335 336 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 337 338 /* Short Audio Descriptor */ 339 struct cea_sad { 340 u8 format; 341 u8 channels; /* max number of channels - 1 */ 342 u8 freq; 343 u8 byte2; /* meaning depends on format */ 344 }; 345 346 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads); 347 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb); 348 int drm_av_sync_delay(struct drm_connector *connector, 349 const struct drm_display_mode *mode); 350 351 int 352 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 353 const struct drm_connector *connector, 354 const struct drm_display_mode *mode); 355 int 356 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 357 const struct drm_connector *connector, 358 const struct drm_display_mode *mode); 359 360 void 361 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 362 const struct drm_connector *connector, 363 const struct drm_display_mode *mode, 364 enum hdmi_quantization_range rgb_quant_range); 365 366 /** 367 * drm_edid_decode_mfg_id - Decode the manufacturer ID 368 * @mfg_id: The manufacturer ID 369 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 370 * termination 371 */ 372 static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4]) 373 { 374 vend[0] = '@' + ((mfg_id >> 10) & 0x1f); 375 vend[1] = '@' + ((mfg_id >> 5) & 0x1f); 376 vend[2] = '@' + ((mfg_id >> 0) & 0x1f); 377 vend[3] = '\0'; 378 379 return vend; 380 } 381 382 /** 383 * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id() 384 * @vend_chr_0: First character of the vendor string. 385 * @vend_chr_1: Second character of the vendor string. 386 * @vend_chr_2: Third character of the vendor string. 387 * @product_id: The 16-bit product ID. 388 * 389 * This is a macro so that it can be calculated at compile time and used 390 * as an initializer. 391 * 392 * For instance: 393 * drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08 394 * 395 * Return: a 32-bit ID per panel. 396 */ 397 #define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \ 398 ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \ 399 (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \ 400 (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \ 401 ((product_id) & 0xffff)) 402 403 /** 404 * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id() 405 * @panel_id: The panel ID to decode. 406 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 407 * termination 408 * @product_id: The product ID will be returned here. 409 * 410 * For instance, after: 411 * drm_edid_decode_panel_id(0x09e52d08, vend, &product_id) 412 * These will be true: 413 * vend[0] = 'B' 414 * vend[1] = 'O' 415 * vend[2] = 'E' 416 * vend[3] = '\0' 417 * product_id = 0x2d08 418 */ 419 static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id) 420 { 421 *product_id = (u16)(panel_id & 0xffff); 422 drm_edid_decode_mfg_id(panel_id >> 16, vend); 423 } 424 425 bool drm_probe_ddc(struct i2c_adapter *adapter); 426 struct edid *drm_do_get_edid(struct drm_connector *connector, 427 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 428 size_t len), 429 void *data); 430 struct edid *drm_get_edid(struct drm_connector *connector, 431 struct i2c_adapter *adapter); 432 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 433 struct i2c_adapter *adapter); 434 struct edid *drm_edid_duplicate(const struct edid *edid); 435 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 436 int drm_edid_override_connector_update(struct drm_connector *connector); 437 438 u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 439 bool drm_detect_hdmi_monitor(const struct edid *edid); 440 bool drm_detect_monitor_audio(const struct edid *edid); 441 enum hdmi_quantization_range 442 drm_default_rgb_quant_range(const struct drm_display_mode *mode); 443 int drm_add_modes_noedid(struct drm_connector *connector, 444 int hdisplay, int vdisplay); 445 446 int drm_edid_header_is_valid(const void *edid); 447 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 448 bool *edid_corrupt); 449 bool drm_edid_is_valid(struct edid *edid); 450 void drm_edid_get_monitor_name(const struct edid *edid, char *name, 451 int buflen); 452 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 453 int hsize, int vsize, int fresh, 454 bool rb); 455 struct drm_display_mode * 456 drm_display_mode_from_cea_vic(struct drm_device *dev, 457 u8 video_code); 458 459 /* Interface based on struct drm_edid */ 460 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size); 461 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid); 462 void drm_edid_free(const struct drm_edid *drm_edid); 463 bool drm_edid_valid(const struct drm_edid *drm_edid); 464 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid); 465 const struct drm_edid *drm_edid_read(struct drm_connector *connector); 466 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 467 struct i2c_adapter *adapter); 468 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 469 int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len), 470 void *context); 471 const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter); 472 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 473 struct i2c_adapter *adapter); 474 int drm_edid_connector_update(struct drm_connector *connector, 475 const struct drm_edid *edid); 476 int drm_edid_connector_add_modes(struct drm_connector *connector); 477 bool drm_edid_is_digital(const struct drm_edid *drm_edid); 478 void drm_edid_get_product_id(const struct drm_edid *drm_edid, 479 struct drm_edid_product_id *id); 480 void drm_edid_print_product_id(struct drm_printer *p, 481 const struct drm_edid_product_id *id, bool raw); 482 u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid); 483 bool drm_edid_match(const struct drm_edid *drm_edid, 484 const struct drm_edid_ident *ident); 485 486 #endif /* __DRM_EDID_H__ */ 487