1 /* 2 * Copyright © 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __DRM_EDID_H__ 24 #define __DRM_EDID_H__ 25 26 #include <linux/types.h> 27 #include <linux/hdmi.h> 28 #include <drm/drm_mode.h> 29 30 struct drm_device; 31 struct drm_edid; 32 struct i2c_adapter; 33 34 #define EDID_LENGTH 128 35 #define DDC_ADDR 0x50 36 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 37 38 #define CEA_EXT 0x02 39 #define VTB_EXT 0x10 40 #define DI_EXT 0x40 41 #define LS_EXT 0x50 42 #define MI_EXT 0x60 43 #define DISPLAYID_EXT 0x70 44 45 struct est_timings { 46 u8 t1; 47 u8 t2; 48 u8 mfg_rsvd; 49 } __attribute__((packed)); 50 51 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 52 #define EDID_TIMING_ASPECT_SHIFT 6 53 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 54 55 /* need to add 60 */ 56 #define EDID_TIMING_VFREQ_SHIFT 0 57 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 58 59 struct std_timing { 60 u8 hsize; /* need to multiply by 8 then add 248 */ 61 u8 vfreq_aspect; 62 } __attribute__((packed)); 63 64 #define DRM_EDID_PT_SYNC_MASK (3 << 3) 65 # define DRM_EDID_PT_ANALOG_CSYNC (0 << 3) 66 # define DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC (1 << 3) 67 # define DRM_EDID_PT_DIGITAL_CSYNC (2 << 3) 68 # define DRM_EDID_PT_CSYNC_ON_RGB (1 << 1) /* analog csync only */ 69 # define DRM_EDID_PT_CSYNC_SERRATE (1 << 2) 70 # define DRM_EDID_PT_DIGITAL_SEPARATE_SYNC (3 << 3) 71 # define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) /* also digital csync */ 72 # define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 73 #define DRM_EDID_PT_STEREO (1 << 5) 74 #define DRM_EDID_PT_INTERLACED (1 << 7) 75 76 /* If detailed data is pixel timing */ 77 struct detailed_pixel_timing { 78 u8 hactive_lo; 79 u8 hblank_lo; 80 u8 hactive_hblank_hi; 81 u8 vactive_lo; 82 u8 vblank_lo; 83 u8 vactive_vblank_hi; 84 u8 hsync_offset_lo; 85 u8 hsync_pulse_width_lo; 86 u8 vsync_offset_pulse_width_lo; 87 u8 hsync_vsync_offset_pulse_width_hi; 88 u8 width_mm_lo; 89 u8 height_mm_lo; 90 u8 width_height_mm_hi; 91 u8 hborder; 92 u8 vborder; 93 u8 misc; 94 } __attribute__((packed)); 95 96 /* If it's not pixel timing, it'll be one of the below */ 97 struct detailed_data_string { 98 u8 str[13]; 99 } __attribute__((packed)); 100 101 #define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */ 102 #define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */ 103 #define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */ 104 #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ 105 106 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 /* 1.3 */ 107 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 /* 1.4 */ 108 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 /* 1.3 */ 109 #define DRM_EDID_CVT_SUPPORT_FLAG 0x04 /* 1.4 */ 110 111 #define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING (1 << 3) 112 #define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING (1 << 4) 113 114 struct detailed_data_monitor_range { 115 u8 min_vfreq; 116 u8 max_vfreq; 117 u8 min_hfreq_khz; 118 u8 max_hfreq_khz; 119 u8 pixel_clock_mhz; /* need to multiply by 10 */ 120 u8 flags; 121 union { 122 struct { 123 u8 reserved; 124 u8 hfreq_start_khz; /* need to multiply by 2 */ 125 u8 c; /* need to divide by 2 */ 126 __le16 m; 127 u8 k; 128 u8 j; /* need to divide by 2 */ 129 } __attribute__((packed)) gtf2; 130 struct { 131 u8 version; 132 u8 data1; /* high 6 bits: extra clock resolution */ 133 u8 data2; /* plus low 2 of above: max hactive */ 134 u8 supported_aspects; 135 u8 flags; /* preferred aspect and blanking support */ 136 u8 supported_scalings; 137 u8 preferred_refresh; 138 } __attribute__((packed)) cvt; 139 } __attribute__((packed)) formula; 140 } __attribute__((packed)); 141 142 struct detailed_data_wpindex { 143 u8 white_yx_lo; /* Lower 2 bits each */ 144 u8 white_x_hi; 145 u8 white_y_hi; 146 u8 gamma; /* need to divide by 100 then add 1 */ 147 } __attribute__((packed)); 148 149 struct detailed_data_color_point { 150 u8 windex1; 151 u8 wpindex1[3]; 152 u8 windex2; 153 u8 wpindex2[3]; 154 } __attribute__((packed)); 155 156 struct cvt_timing { 157 u8 code[3]; 158 } __attribute__((packed)); 159 160 struct detailed_non_pixel { 161 u8 pad1; 162 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 163 fb=color point data, fa=standard timing data, 164 f9=undefined, f8=mfg. reserved */ 165 u8 pad2; 166 union { 167 struct detailed_data_string str; 168 struct detailed_data_monitor_range range; 169 struct detailed_data_wpindex color; 170 struct std_timing timings[6]; 171 struct cvt_timing cvt[4]; 172 } __attribute__((packed)) data; 173 } __attribute__((packed)); 174 175 #define EDID_DETAIL_EST_TIMINGS 0xf7 176 #define EDID_DETAIL_CVT_3BYTE 0xf8 177 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 178 #define EDID_DETAIL_STD_MODES 0xfa 179 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 180 #define EDID_DETAIL_MONITOR_NAME 0xfc 181 #define EDID_DETAIL_MONITOR_RANGE 0xfd 182 #define EDID_DETAIL_MONITOR_STRING 0xfe 183 #define EDID_DETAIL_MONITOR_SERIAL 0xff 184 185 struct detailed_timing { 186 __le16 pixel_clock; /* need to multiply by 10 KHz */ 187 union { 188 struct detailed_pixel_timing pixel_data; 189 struct detailed_non_pixel other_data; 190 } __attribute__((packed)) data; 191 } __attribute__((packed)); 192 193 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 194 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 195 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 196 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 197 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 198 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 199 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 200 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ 201 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ 202 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ 203 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ 204 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ 205 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ 206 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ 207 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ 208 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ 209 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ 210 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ 211 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ 212 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ 213 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ 214 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ 215 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ 216 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ 217 218 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) /* 1.2 */ 219 #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ 220 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 221 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 222 /* If analog */ 223 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 224 /* If digital */ 225 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 226 #define DRM_EDID_FEATURE_RGB (0 << 3) 227 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 228 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 229 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 230 231 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 232 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 233 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 234 235 #define DRM_EDID_HDMI_DC_48 (1 << 6) 236 #define DRM_EDID_HDMI_DC_36 (1 << 5) 237 #define DRM_EDID_HDMI_DC_30 (1 << 4) 238 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 239 240 /* YCBCR 420 deep color modes */ 241 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 242 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 243 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 244 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 245 DRM_EDID_YCBCR420_DC_36 | \ 246 DRM_EDID_YCBCR420_DC_30) 247 248 /* HDMI 2.1 additional fields */ 249 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 250 #define DRM_EDID_FAPA_START_LOCATION (1 << 0) 251 #define DRM_EDID_ALLM (1 << 1) 252 #define DRM_EDID_FVA (1 << 2) 253 254 /* Deep Color specific */ 255 #define DRM_EDID_DC_30BIT_420 (1 << 0) 256 #define DRM_EDID_DC_36BIT_420 (1 << 1) 257 #define DRM_EDID_DC_48BIT_420 (1 << 2) 258 259 /* VRR specific */ 260 #define DRM_EDID_CNMVRR (1 << 3) 261 #define DRM_EDID_CINEMA_VRR (1 << 4) 262 #define DRM_EDID_MDELTA (1 << 5) 263 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 264 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff 265 #define DRM_EDID_VRR_MIN_MASK 0x3f 266 267 /* DSC specific */ 268 #define DRM_EDID_DSC_10BPC (1 << 0) 269 #define DRM_EDID_DSC_12BPC (1 << 1) 270 #define DRM_EDID_DSC_16BPC (1 << 2) 271 #define DRM_EDID_DSC_ALL_BPP (1 << 3) 272 #define DRM_EDID_DSC_NATIVE_420 (1 << 6) 273 #define DRM_EDID_DSC_1P2 (1 << 7) 274 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 275 #define DRM_EDID_DSC_MAX_SLICES 0xf 276 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f 277 278 /* ELD Header Block */ 279 #define DRM_ELD_HEADER_BLOCK_SIZE 4 280 281 #define DRM_ELD_VER 0 282 # define DRM_ELD_VER_SHIFT 3 283 # define DRM_ELD_VER_MASK (0x1f << 3) 284 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 285 # define DRM_ELD_VER_CANNED (0x1f << 3) 286 287 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 288 289 /* ELD Baseline Block for ELD_Ver == 2 */ 290 #define DRM_ELD_CEA_EDID_VER_MNL 4 291 # define DRM_ELD_CEA_EDID_VER_SHIFT 5 292 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 293 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 294 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 295 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 296 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 297 # define DRM_ELD_MNL_SHIFT 0 298 # define DRM_ELD_MNL_MASK (0x1f << 0) 299 300 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 301 # define DRM_ELD_SAD_COUNT_SHIFT 4 302 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 303 # define DRM_ELD_CONN_TYPE_SHIFT 2 304 # define DRM_ELD_CONN_TYPE_MASK (3 << 2) 305 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 306 # define DRM_ELD_CONN_TYPE_DP (1 << 2) 307 # define DRM_ELD_SUPPORTS_AI (1 << 1) 308 # define DRM_ELD_SUPPORTS_HDCP (1 << 0) 309 310 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 311 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 312 313 #define DRM_ELD_SPEAKER 7 314 # define DRM_ELD_SPEAKER_MASK 0x7f 315 # define DRM_ELD_SPEAKER_RLRC (1 << 6) 316 # define DRM_ELD_SPEAKER_FLRC (1 << 5) 317 # define DRM_ELD_SPEAKER_RC (1 << 4) 318 # define DRM_ELD_SPEAKER_RLR (1 << 3) 319 # define DRM_ELD_SPEAKER_FC (1 << 2) 320 # define DRM_ELD_SPEAKER_LFE (1 << 1) 321 # define DRM_ELD_SPEAKER_FLR (1 << 0) 322 323 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 324 # define DRM_ELD_PORT_ID_LEN 8 325 326 #define DRM_ELD_MANUFACTURER_NAME0 16 327 #define DRM_ELD_MANUFACTURER_NAME1 17 328 329 #define DRM_ELD_PRODUCT_CODE0 18 330 #define DRM_ELD_PRODUCT_CODE1 19 331 332 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 333 334 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 335 336 struct edid { 337 u8 header[8]; 338 /* Vendor & product info */ 339 u8 mfg_id[2]; 340 u8 prod_code[2]; 341 u32 serial; /* FIXME: byte order */ 342 u8 mfg_week; 343 u8 mfg_year; 344 /* EDID version */ 345 u8 version; 346 u8 revision; 347 /* Display info: */ 348 u8 input; 349 u8 width_cm; 350 u8 height_cm; 351 u8 gamma; 352 u8 features; 353 /* Color characteristics */ 354 u8 red_green_lo; 355 u8 blue_white_lo; 356 u8 red_x; 357 u8 red_y; 358 u8 green_x; 359 u8 green_y; 360 u8 blue_x; 361 u8 blue_y; 362 u8 white_x; 363 u8 white_y; 364 /* Est. timings and mfg rsvd timings*/ 365 struct est_timings established_timings; 366 /* Standard timings 1-8*/ 367 struct std_timing standard_timings[8]; 368 /* Detailing timings 1-4 */ 369 struct detailed_timing detailed_timings[4]; 370 /* Number of 128 byte ext. blocks */ 371 u8 extensions; 372 /* Checksum */ 373 u8 checksum; 374 } __attribute__((packed)); 375 376 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 377 378 /* Short Audio Descriptor */ 379 struct cea_sad { 380 u8 format; 381 u8 channels; /* max number of channels - 1 */ 382 u8 freq; 383 u8 byte2; /* meaning depends on format */ 384 }; 385 386 struct drm_encoder; 387 struct drm_connector; 388 struct drm_connector_state; 389 struct drm_display_mode; 390 391 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads); 392 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb); 393 int drm_av_sync_delay(struct drm_connector *connector, 394 const struct drm_display_mode *mode); 395 396 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE 397 int __drm_set_edid_firmware_path(const char *path); 398 int __drm_get_edid_firmware_path(char *buf, size_t bufsize); 399 #endif 400 401 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); 402 403 int 404 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 405 const struct drm_connector *connector, 406 const struct drm_display_mode *mode); 407 int 408 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 409 const struct drm_connector *connector, 410 const struct drm_display_mode *mode); 411 412 void 413 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 414 const struct drm_connector *connector, 415 const struct drm_display_mode *mode, 416 enum hdmi_quantization_range rgb_quant_range); 417 418 /** 419 * drm_eld_mnl - Get ELD monitor name length in bytes. 420 * @eld: pointer to an eld memory structure with mnl set 421 */ 422 static inline int drm_eld_mnl(const uint8_t *eld) 423 { 424 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 425 } 426 427 /** 428 * drm_eld_sad - Get ELD SAD structures. 429 * @eld: pointer to an eld memory structure with sad_count set 430 */ 431 static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 432 { 433 unsigned int ver, mnl; 434 435 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 436 if (ver != 2 && ver != 31) 437 return NULL; 438 439 mnl = drm_eld_mnl(eld); 440 if (mnl > 16) 441 return NULL; 442 443 return eld + DRM_ELD_CEA_SAD(mnl, 0); 444 } 445 446 /** 447 * drm_eld_sad_count - Get ELD SAD count. 448 * @eld: pointer to an eld memory structure with sad_count set 449 */ 450 static inline int drm_eld_sad_count(const uint8_t *eld) 451 { 452 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 453 DRM_ELD_SAD_COUNT_SHIFT; 454 } 455 456 /** 457 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 458 * @eld: pointer to an eld memory structure with mnl and sad_count set 459 * 460 * This is a helper for determining the payload size of the baseline block, in 461 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 462 */ 463 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 464 { 465 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 466 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 467 } 468 469 /** 470 * drm_eld_size - Get ELD size in bytes 471 * @eld: pointer to a complete eld memory structure 472 * 473 * The returned value does not include the vendor block. It's vendor specific, 474 * and comprises of the remaining bytes in the ELD memory buffer after 475 * drm_eld_size() bytes of header and baseline block. 476 * 477 * The returned value is guaranteed to be a multiple of 4. 478 */ 479 static inline int drm_eld_size(const uint8_t *eld) 480 { 481 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 482 } 483 484 /** 485 * drm_eld_get_spk_alloc - Get speaker allocation 486 * @eld: pointer to an ELD memory structure 487 * 488 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER 489 * field definitions to identify speakers. 490 */ 491 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld) 492 { 493 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK; 494 } 495 496 /** 497 * drm_eld_get_conn_type - Get device type hdmi/dp connected 498 * @eld: pointer to an ELD memory structure 499 * 500 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to 501 * identify the display type connected. 502 */ 503 static inline u8 drm_eld_get_conn_type(const uint8_t *eld) 504 { 505 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; 506 } 507 508 /** 509 * drm_edid_decode_mfg_id - Decode the manufacturer ID 510 * @mfg_id: The manufacturer ID 511 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 512 * termination 513 */ 514 static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4]) 515 { 516 vend[0] = '@' + ((mfg_id >> 10) & 0x1f); 517 vend[1] = '@' + ((mfg_id >> 5) & 0x1f); 518 vend[2] = '@' + ((mfg_id >> 0) & 0x1f); 519 vend[3] = '\0'; 520 521 return vend; 522 } 523 524 /** 525 * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id() 526 * @vend_chr_0: First character of the vendor string. 527 * @vend_chr_1: Second character of the vendor string. 528 * @vend_chr_2: Third character of the vendor string. 529 * @product_id: The 16-bit product ID. 530 * 531 * This is a macro so that it can be calculated at compile time and used 532 * as an initializer. 533 * 534 * For instance: 535 * drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08 536 * 537 * Return: a 32-bit ID per panel. 538 */ 539 #define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \ 540 ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \ 541 (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \ 542 (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \ 543 ((product_id) & 0xffff)) 544 545 /** 546 * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id() 547 * @panel_id: The panel ID to decode. 548 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 549 * termination 550 * @product_id: The product ID will be returned here. 551 * 552 * For instance, after: 553 * drm_edid_decode_panel_id(0x09e52d08, vend, &product_id) 554 * These will be true: 555 * vend[0] = 'B' 556 * vend[1] = 'O' 557 * vend[2] = 'E' 558 * vend[3] = '\0' 559 * product_id = 0x2d08 560 */ 561 static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id) 562 { 563 *product_id = (u16)(panel_id & 0xffff); 564 drm_edid_decode_mfg_id(panel_id >> 16, vend); 565 } 566 567 bool drm_probe_ddc(struct i2c_adapter *adapter); 568 struct edid *drm_do_get_edid(struct drm_connector *connector, 569 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 570 size_t len), 571 void *data); 572 struct edid *drm_get_edid(struct drm_connector *connector, 573 struct i2c_adapter *adapter); 574 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter); 575 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 576 struct i2c_adapter *adapter); 577 struct edid *drm_edid_duplicate(const struct edid *edid); 578 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 579 int drm_edid_override_connector_update(struct drm_connector *connector); 580 581 u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 582 bool drm_detect_hdmi_monitor(const struct edid *edid); 583 bool drm_detect_monitor_audio(const struct edid *edid); 584 enum hdmi_quantization_range 585 drm_default_rgb_quant_range(const struct drm_display_mode *mode); 586 int drm_add_modes_noedid(struct drm_connector *connector, 587 int hdisplay, int vdisplay); 588 void drm_set_preferred_mode(struct drm_connector *connector, 589 int hpref, int vpref); 590 591 int drm_edid_header_is_valid(const void *edid); 592 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 593 bool *edid_corrupt); 594 bool drm_edid_is_valid(struct edid *edid); 595 void drm_edid_get_monitor_name(const struct edid *edid, char *name, 596 int buflen); 597 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 598 int hsize, int vsize, int fresh, 599 bool rb); 600 struct drm_display_mode * 601 drm_display_mode_from_cea_vic(struct drm_device *dev, 602 u8 video_code); 603 604 /* Interface based on struct drm_edid */ 605 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size); 606 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid); 607 void drm_edid_free(const struct drm_edid *drm_edid); 608 bool drm_edid_valid(const struct drm_edid *drm_edid); 609 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid); 610 const struct drm_edid *drm_edid_read(struct drm_connector *connector); 611 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 612 struct i2c_adapter *adapter); 613 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 614 int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len), 615 void *context); 616 int drm_edid_connector_update(struct drm_connector *connector, 617 const struct drm_edid *edid); 618 int drm_edid_connector_add_modes(struct drm_connector *connector); 619 620 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 621 int ext_id, int *ext_index); 622 623 #endif /* __DRM_EDID_H__ */ 624