1 /* 2 * Copyright © 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __DRM_EDID_H__ 24 #define __DRM_EDID_H__ 25 26 #include <linux/types.h> 27 #include <linux/hdmi.h> 28 #include <drm/drm_mode.h> 29 30 struct drm_device; 31 struct i2c_adapter; 32 33 #define EDID_LENGTH 128 34 #define DDC_ADDR 0x50 35 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 36 37 #define CEA_EXT 0x02 38 #define VTB_EXT 0x10 39 #define DI_EXT 0x40 40 #define LS_EXT 0x50 41 #define MI_EXT 0x60 42 #define DISPLAYID_EXT 0x70 43 44 struct est_timings { 45 u8 t1; 46 u8 t2; 47 u8 mfg_rsvd; 48 } __attribute__((packed)); 49 50 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 51 #define EDID_TIMING_ASPECT_SHIFT 6 52 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 53 54 /* need to add 60 */ 55 #define EDID_TIMING_VFREQ_SHIFT 0 56 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 57 58 struct std_timing { 59 u8 hsize; /* need to multiply by 8 then add 248 */ 60 u8 vfreq_aspect; 61 } __attribute__((packed)); 62 63 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 64 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 65 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 66 #define DRM_EDID_PT_STEREO (1 << 5) 67 #define DRM_EDID_PT_INTERLACED (1 << 7) 68 69 /* If detailed data is pixel timing */ 70 struct detailed_pixel_timing { 71 u8 hactive_lo; 72 u8 hblank_lo; 73 u8 hactive_hblank_hi; 74 u8 vactive_lo; 75 u8 vblank_lo; 76 u8 vactive_vblank_hi; 77 u8 hsync_offset_lo; 78 u8 hsync_pulse_width_lo; 79 u8 vsync_offset_pulse_width_lo; 80 u8 hsync_vsync_offset_pulse_width_hi; 81 u8 width_mm_lo; 82 u8 height_mm_lo; 83 u8 width_height_mm_hi; 84 u8 hborder; 85 u8 vborder; 86 u8 misc; 87 } __attribute__((packed)); 88 89 /* If it's not pixel timing, it'll be one of the below */ 90 struct detailed_data_string { 91 u8 str[13]; 92 } __attribute__((packed)); 93 94 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 95 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 96 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 97 #define DRM_EDID_CVT_SUPPORT_FLAG 0x04 98 99 struct detailed_data_monitor_range { 100 u8 min_vfreq; 101 u8 max_vfreq; 102 u8 min_hfreq_khz; 103 u8 max_hfreq_khz; 104 u8 pixel_clock_mhz; /* need to multiply by 10 */ 105 u8 flags; 106 union { 107 struct { 108 u8 reserved; 109 u8 hfreq_start_khz; /* need to multiply by 2 */ 110 u8 c; /* need to divide by 2 */ 111 __le16 m; 112 u8 k; 113 u8 j; /* need to divide by 2 */ 114 } __attribute__((packed)) gtf2; 115 struct { 116 u8 version; 117 u8 data1; /* high 6 bits: extra clock resolution */ 118 u8 data2; /* plus low 2 of above: max hactive */ 119 u8 supported_aspects; 120 u8 flags; /* preferred aspect and blanking support */ 121 u8 supported_scalings; 122 u8 preferred_refresh; 123 } __attribute__((packed)) cvt; 124 } __attribute__((packed)) formula; 125 } __attribute__((packed)); 126 127 struct detailed_data_wpindex { 128 u8 white_yx_lo; /* Lower 2 bits each */ 129 u8 white_x_hi; 130 u8 white_y_hi; 131 u8 gamma; /* need to divide by 100 then add 1 */ 132 } __attribute__((packed)); 133 134 struct detailed_data_color_point { 135 u8 windex1; 136 u8 wpindex1[3]; 137 u8 windex2; 138 u8 wpindex2[3]; 139 } __attribute__((packed)); 140 141 struct cvt_timing { 142 u8 code[3]; 143 } __attribute__((packed)); 144 145 struct detailed_non_pixel { 146 u8 pad1; 147 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 148 fb=color point data, fa=standard timing data, 149 f9=undefined, f8=mfg. reserved */ 150 u8 pad2; 151 union { 152 struct detailed_data_string str; 153 struct detailed_data_monitor_range range; 154 struct detailed_data_wpindex color; 155 struct std_timing timings[6]; 156 struct cvt_timing cvt[4]; 157 } __attribute__((packed)) data; 158 } __attribute__((packed)); 159 160 #define EDID_DETAIL_EST_TIMINGS 0xf7 161 #define EDID_DETAIL_CVT_3BYTE 0xf8 162 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 163 #define EDID_DETAIL_STD_MODES 0xfa 164 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 165 #define EDID_DETAIL_MONITOR_NAME 0xfc 166 #define EDID_DETAIL_MONITOR_RANGE 0xfd 167 #define EDID_DETAIL_MONITOR_STRING 0xfe 168 #define EDID_DETAIL_MONITOR_SERIAL 0xff 169 170 struct detailed_timing { 171 __le16 pixel_clock; /* need to multiply by 10 KHz */ 172 union { 173 struct detailed_pixel_timing pixel_data; 174 struct detailed_non_pixel other_data; 175 } __attribute__((packed)) data; 176 } __attribute__((packed)); 177 178 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 179 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 180 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 181 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 182 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 183 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 184 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 185 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ 186 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ 187 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ 188 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ 189 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ 190 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ 191 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ 192 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ 193 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ 194 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ 195 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ 196 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ 197 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ 198 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ 199 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ 200 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ 201 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ 202 203 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 204 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 205 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 206 /* If analog */ 207 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 208 /* If digital */ 209 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 210 #define DRM_EDID_FEATURE_RGB (0 << 3) 211 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 212 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 213 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 214 215 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 216 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 217 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 218 219 #define DRM_EDID_HDMI_DC_48 (1 << 6) 220 #define DRM_EDID_HDMI_DC_36 (1 << 5) 221 #define DRM_EDID_HDMI_DC_30 (1 << 4) 222 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 223 224 /* YCBCR 420 deep color modes */ 225 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 226 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 227 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 228 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 229 DRM_EDID_YCBCR420_DC_36 | \ 230 DRM_EDID_YCBCR420_DC_30) 231 232 /* HDMI 2.1 additional fields */ 233 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 234 #define DRM_EDID_FAPA_START_LOCATION (1 << 0) 235 #define DRM_EDID_ALLM (1 << 1) 236 #define DRM_EDID_FVA (1 << 2) 237 238 /* Deep Color specific */ 239 #define DRM_EDID_DC_30BIT_420 (1 << 0) 240 #define DRM_EDID_DC_36BIT_420 (1 << 1) 241 #define DRM_EDID_DC_48BIT_420 (1 << 2) 242 243 /* VRR specific */ 244 #define DRM_EDID_CNMVRR (1 << 3) 245 #define DRM_EDID_CINEMA_VRR (1 << 4) 246 #define DRM_EDID_MDELTA (1 << 5) 247 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 248 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff 249 #define DRM_EDID_VRR_MIN_MASK 0x3f 250 251 /* DSC specific */ 252 #define DRM_EDID_DSC_10BPC (1 << 0) 253 #define DRM_EDID_DSC_12BPC (1 << 1) 254 #define DRM_EDID_DSC_16BPC (1 << 2) 255 #define DRM_EDID_DSC_ALL_BPP (1 << 3) 256 #define DRM_EDID_DSC_NATIVE_420 (1 << 6) 257 #define DRM_EDID_DSC_1P2 (1 << 7) 258 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 259 #define DRM_EDID_DSC_MAX_SLICES 0xf 260 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f 261 262 /* ELD Header Block */ 263 #define DRM_ELD_HEADER_BLOCK_SIZE 4 264 265 #define DRM_ELD_VER 0 266 # define DRM_ELD_VER_SHIFT 3 267 # define DRM_ELD_VER_MASK (0x1f << 3) 268 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 269 # define DRM_ELD_VER_CANNED (0x1f << 3) 270 271 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 272 273 /* ELD Baseline Block for ELD_Ver == 2 */ 274 #define DRM_ELD_CEA_EDID_VER_MNL 4 275 # define DRM_ELD_CEA_EDID_VER_SHIFT 5 276 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 277 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 278 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 279 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 280 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 281 # define DRM_ELD_MNL_SHIFT 0 282 # define DRM_ELD_MNL_MASK (0x1f << 0) 283 284 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 285 # define DRM_ELD_SAD_COUNT_SHIFT 4 286 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 287 # define DRM_ELD_CONN_TYPE_SHIFT 2 288 # define DRM_ELD_CONN_TYPE_MASK (3 << 2) 289 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 290 # define DRM_ELD_CONN_TYPE_DP (1 << 2) 291 # define DRM_ELD_SUPPORTS_AI (1 << 1) 292 # define DRM_ELD_SUPPORTS_HDCP (1 << 0) 293 294 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 295 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 296 297 #define DRM_ELD_SPEAKER 7 298 # define DRM_ELD_SPEAKER_MASK 0x7f 299 # define DRM_ELD_SPEAKER_RLRC (1 << 6) 300 # define DRM_ELD_SPEAKER_FLRC (1 << 5) 301 # define DRM_ELD_SPEAKER_RC (1 << 4) 302 # define DRM_ELD_SPEAKER_RLR (1 << 3) 303 # define DRM_ELD_SPEAKER_FC (1 << 2) 304 # define DRM_ELD_SPEAKER_LFE (1 << 1) 305 # define DRM_ELD_SPEAKER_FLR (1 << 0) 306 307 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 308 # define DRM_ELD_PORT_ID_LEN 8 309 310 #define DRM_ELD_MANUFACTURER_NAME0 16 311 #define DRM_ELD_MANUFACTURER_NAME1 17 312 313 #define DRM_ELD_PRODUCT_CODE0 18 314 #define DRM_ELD_PRODUCT_CODE1 19 315 316 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 317 318 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 319 320 struct edid { 321 u8 header[8]; 322 /* Vendor & product info */ 323 u8 mfg_id[2]; 324 u8 prod_code[2]; 325 u32 serial; /* FIXME: byte order */ 326 u8 mfg_week; 327 u8 mfg_year; 328 /* EDID version */ 329 u8 version; 330 u8 revision; 331 /* Display info: */ 332 u8 input; 333 u8 width_cm; 334 u8 height_cm; 335 u8 gamma; 336 u8 features; 337 /* Color characteristics */ 338 u8 red_green_lo; 339 u8 blue_white_lo; 340 u8 red_x; 341 u8 red_y; 342 u8 green_x; 343 u8 green_y; 344 u8 blue_x; 345 u8 blue_y; 346 u8 white_x; 347 u8 white_y; 348 /* Est. timings and mfg rsvd timings*/ 349 struct est_timings established_timings; 350 /* Standard timings 1-8*/ 351 struct std_timing standard_timings[8]; 352 /* Detailing timings 1-4 */ 353 struct detailed_timing detailed_timings[4]; 354 /* Number of 128 byte ext. blocks */ 355 u8 extensions; 356 /* Checksum */ 357 u8 checksum; 358 } __attribute__((packed)); 359 360 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 361 362 /* Short Audio Descriptor */ 363 struct cea_sad { 364 u8 format; 365 u8 channels; /* max number of channels - 1 */ 366 u8 freq; 367 u8 byte2; /* meaning depends on format */ 368 }; 369 370 struct drm_encoder; 371 struct drm_connector; 372 struct drm_connector_state; 373 struct drm_display_mode; 374 375 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads); 376 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb); 377 int drm_av_sync_delay(struct drm_connector *connector, 378 const struct drm_display_mode *mode); 379 380 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE 381 struct edid *drm_load_edid_firmware(struct drm_connector *connector); 382 int __drm_set_edid_firmware_path(const char *path); 383 int __drm_get_edid_firmware_path(char *buf, size_t bufsize); 384 #else 385 static inline struct edid * 386 drm_load_edid_firmware(struct drm_connector *connector) 387 { 388 return ERR_PTR(-ENOENT); 389 } 390 #endif 391 392 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); 393 394 int 395 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 396 const struct drm_connector *connector, 397 const struct drm_display_mode *mode); 398 int 399 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 400 const struct drm_connector *connector, 401 const struct drm_display_mode *mode); 402 403 void 404 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 405 const struct drm_connector *connector, 406 const struct drm_display_mode *mode, 407 enum hdmi_quantization_range rgb_quant_range); 408 409 /** 410 * drm_eld_mnl - Get ELD monitor name length in bytes. 411 * @eld: pointer to an eld memory structure with mnl set 412 */ 413 static inline int drm_eld_mnl(const uint8_t *eld) 414 { 415 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 416 } 417 418 /** 419 * drm_eld_sad - Get ELD SAD structures. 420 * @eld: pointer to an eld memory structure with sad_count set 421 */ 422 static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 423 { 424 unsigned int ver, mnl; 425 426 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 427 if (ver != 2 && ver != 31) 428 return NULL; 429 430 mnl = drm_eld_mnl(eld); 431 if (mnl > 16) 432 return NULL; 433 434 return eld + DRM_ELD_CEA_SAD(mnl, 0); 435 } 436 437 /** 438 * drm_eld_sad_count - Get ELD SAD count. 439 * @eld: pointer to an eld memory structure with sad_count set 440 */ 441 static inline int drm_eld_sad_count(const uint8_t *eld) 442 { 443 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 444 DRM_ELD_SAD_COUNT_SHIFT; 445 } 446 447 /** 448 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 449 * @eld: pointer to an eld memory structure with mnl and sad_count set 450 * 451 * This is a helper for determining the payload size of the baseline block, in 452 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 453 */ 454 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 455 { 456 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 457 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 458 } 459 460 /** 461 * drm_eld_size - Get ELD size in bytes 462 * @eld: pointer to a complete eld memory structure 463 * 464 * The returned value does not include the vendor block. It's vendor specific, 465 * and comprises of the remaining bytes in the ELD memory buffer after 466 * drm_eld_size() bytes of header and baseline block. 467 * 468 * The returned value is guaranteed to be a multiple of 4. 469 */ 470 static inline int drm_eld_size(const uint8_t *eld) 471 { 472 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 473 } 474 475 /** 476 * drm_eld_get_spk_alloc - Get speaker allocation 477 * @eld: pointer to an ELD memory structure 478 * 479 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER 480 * field definitions to identify speakers. 481 */ 482 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld) 483 { 484 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK; 485 } 486 487 /** 488 * drm_eld_get_conn_type - Get device type hdmi/dp connected 489 * @eld: pointer to an ELD memory structure 490 * 491 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to 492 * identify the display type connected. 493 */ 494 static inline u8 drm_eld_get_conn_type(const uint8_t *eld) 495 { 496 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; 497 } 498 499 /** 500 * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id() 501 * @vend_chr_0: First character of the vendor string. 502 * @vend_chr_1: Second character of the vendor string. 503 * @vend_chr_2: Third character of the vendor string. 504 * @product_id: The 16-bit product ID. 505 * 506 * This is a macro so that it can be calculated at compile time and used 507 * as an initializer. 508 * 509 * For instance: 510 * drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08 511 * 512 * Return: a 32-bit ID per panel. 513 */ 514 #define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \ 515 ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \ 516 (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \ 517 (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \ 518 ((product_id) & 0xffff)) 519 520 /** 521 * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id() 522 * @panel_id: The panel ID to decode. 523 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 524 * termination 525 * @product_id: The product ID will be returned here. 526 * 527 * For instance, after: 528 * drm_edid_decode_panel_id(0x09e52d08, vend, &product_id) 529 * These will be true: 530 * vend[0] = 'B' 531 * vend[1] = 'O' 532 * vend[2] = 'E' 533 * vend[3] = '\0' 534 * product_id = 0x2d08 535 */ 536 static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id) 537 { 538 *product_id = (u16)(panel_id & 0xffff); 539 vend[0] = '@' + ((panel_id >> 26) & 0x1f); 540 vend[1] = '@' + ((panel_id >> 21) & 0x1f); 541 vend[2] = '@' + ((panel_id >> 16) & 0x1f); 542 vend[3] = '\0'; 543 } 544 545 bool drm_probe_ddc(struct i2c_adapter *adapter); 546 struct edid *drm_do_get_edid(struct drm_connector *connector, 547 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 548 size_t len), 549 void *data); 550 struct edid *drm_get_edid(struct drm_connector *connector, 551 struct i2c_adapter *adapter); 552 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter); 553 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 554 struct i2c_adapter *adapter); 555 struct edid *drm_edid_duplicate(const struct edid *edid); 556 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 557 int drm_add_override_edid_modes(struct drm_connector *connector); 558 559 u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 560 bool drm_detect_hdmi_monitor(const struct edid *edid); 561 bool drm_detect_monitor_audio(const struct edid *edid); 562 enum hdmi_quantization_range 563 drm_default_rgb_quant_range(const struct drm_display_mode *mode); 564 int drm_add_modes_noedid(struct drm_connector *connector, 565 int hdisplay, int vdisplay); 566 void drm_set_preferred_mode(struct drm_connector *connector, 567 int hpref, int vpref); 568 569 int drm_edid_header_is_valid(const void *edid); 570 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 571 bool *edid_corrupt); 572 bool drm_edid_is_valid(struct edid *edid); 573 void drm_edid_get_monitor_name(const struct edid *edid, char *name, 574 int buflen); 575 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 576 int hsize, int vsize, int fresh, 577 bool rb); 578 struct drm_display_mode * 579 drm_display_mode_from_cea_vic(struct drm_device *dev, 580 u8 video_code); 581 const u8 *drm_find_edid_extension(const struct edid *edid, 582 int ext_id, int *ext_index); 583 584 585 #endif /* __DRM_EDID_H__ */ 586