1c9c97b8cSDave Airlie /************************************************************************** 2c9c97b8cSDave Airlie * 3c9c97b8cSDave Airlie * Copyright 2009 Red Hat Inc. 4c9c97b8cSDave Airlie * All Rights Reserved. 5c9c97b8cSDave Airlie * 6c9c97b8cSDave Airlie * Permission is hereby granted, free of charge, to any person obtaining a 7c9c97b8cSDave Airlie * copy of this software and associated documentation files (the 8c9c97b8cSDave Airlie * "Software"), to deal in the Software without restriction, including 9c9c97b8cSDave Airlie * without limitation the rights to use, copy, modify, merge, publish, 10c9c97b8cSDave Airlie * distribute, sub license, and/or sell copies of the Software, and to 11c9c97b8cSDave Airlie * permit persons to whom the Software is furnished to do so, subject to 12c9c97b8cSDave Airlie * the following conditions: 13c9c97b8cSDave Airlie * 14c9c97b8cSDave Airlie * The above copyright notice and this permission notice (including the 15c9c97b8cSDave Airlie * next paragraph) shall be included in all copies or substantial portions 16c9c97b8cSDave Airlie * of the Software. 17c9c97b8cSDave Airlie * 18c9c97b8cSDave Airlie * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19c9c97b8cSDave Airlie * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20c9c97b8cSDave Airlie * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21c9c97b8cSDave Airlie * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22c9c97b8cSDave Airlie * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23c9c97b8cSDave Airlie * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24c9c97b8cSDave Airlie * USE OR OTHER DEALINGS IN THE SOFTWARE. 25c9c97b8cSDave Airlie * 26c9c97b8cSDave Airlie * 27c9c97b8cSDave Airlie **************************************************************************/ 28c9c97b8cSDave Airlie /* 29c9c97b8cSDave Airlie * Authors: 30c9c97b8cSDave Airlie * Dave Airlie <airlied@redhat.com> 31c9c97b8cSDave Airlie */ 32c9c97b8cSDave Airlie 33c9c97b8cSDave Airlie #ifndef _DRM_CACHE_H_ 34c9c97b8cSDave Airlie #define _DRM_CACHE_H_ 35c9c97b8cSDave Airlie 36f9a87bd7SGabriel Krisman Bertazi #include <linux/scatterlist.h> 37f9a87bd7SGabriel Krisman Bertazi 38*7938f421SLucas De Marchi struct iosys_map; 39b7e32befSThomas Hellström 40c9c97b8cSDave Airlie void drm_clflush_pages(struct page *pages[], unsigned long num_pages); 41f9a87bd7SGabriel Krisman Bertazi void drm_clflush_sg(struct sg_table *st); 42f9a87bd7SGabriel Krisman Bertazi void drm_clflush_virt_range(void *addr, unsigned long length); 43913b2cb7SMichael D Labriola bool drm_need_swiotlb(int dma_bits); 4482626363SChunming Zhou 45c9c97b8cSDave Airlie 464b0e4e4aSDave Airlie static inline bool drm_arch_can_wc_memory(void) 474b0e4e4aSDave Airlie { 484b0e4e4aSDave Airlie #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) 494b0e4e4aSDave Airlie return false; 50268a2d60SJiaxun Yang #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64) 51221004c6SHuacai Chen return false; 52e02f5c1bSArd Biesheuvel #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) 53e02f5c1bSArd Biesheuvel /* 54e02f5c1bSArd Biesheuvel * The DRM driver stack is designed to work with cache coherent devices 55e02f5c1bSArd Biesheuvel * only, but permits an optimization to be enabled in some cases, where 56e02f5c1bSArd Biesheuvel * for some buffers, both the CPU and the GPU use uncached mappings, 57e02f5c1bSArd Biesheuvel * removing the need for DMA snooping and allocation in the CPU caches. 58e02f5c1bSArd Biesheuvel * 59e02f5c1bSArd Biesheuvel * The use of uncached GPU mappings relies on the correct implementation 60e02f5c1bSArd Biesheuvel * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU 61e02f5c1bSArd Biesheuvel * will use cached mappings nonetheless. On x86 platforms, this does not 62e02f5c1bSArd Biesheuvel * seem to matter, as uncached CPU mappings will snoop the caches in any 63e02f5c1bSArd Biesheuvel * case. However, on ARM and arm64, enabling this optimization on a 64e02f5c1bSArd Biesheuvel * platform where NoSnoop is ignored results in loss of coherency, which 65e02f5c1bSArd Biesheuvel * breaks correct operation of the device. Since we have no way of 66e02f5c1bSArd Biesheuvel * detecting whether NoSnoop works or not, just disable this 67e02f5c1bSArd Biesheuvel * optimization entirely for ARM and arm64. 68e02f5c1bSArd Biesheuvel */ 69e02f5c1bSArd Biesheuvel return false; 704b0e4e4aSDave Airlie #else 714b0e4e4aSDave Airlie return true; 724b0e4e4aSDave Airlie #endif 734b0e4e4aSDave Airlie } 744b0e4e4aSDave Airlie 75b7e32befSThomas Hellström void drm_memcpy_init_early(void); 76b7e32befSThomas Hellström 77*7938f421SLucas De Marchi void drm_memcpy_from_wc(struct iosys_map *dst, 78*7938f421SLucas De Marchi const struct iosys_map *src, 79b7e32befSThomas Hellström unsigned long len); 80c9c97b8cSDave Airlie #endif 81