1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/delay.h> 27 #include <linux/i2c.h> 28 29 #include <drm/display/drm_dp.h> 30 #include <drm/drm_connector.h> 31 32 struct drm_device; 33 struct drm_dp_aux; 34 struct drm_panel; 35 36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40 bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]); 41 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 42 int lane); 43 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 44 int lane); 45 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 46 int lane); 47 48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 49 enum drm_dp_phy dp_phy, bool uhbr); 50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 51 enum drm_dp_phy dp_phy, bool uhbr); 52 53 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 55 void drm_dp_lttpr_link_train_clock_recovery_delay(void); 56 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 58 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 59 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 60 61 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 62 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 63 int lane_count); 64 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 65 int lane_count); 66 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 69 70 u8 drm_dp_link_rate_to_bw_code(int link_rate); 71 int drm_dp_bw_code_to_link_rate(u8 link_bw); 72 73 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 74 75 /** 76 * struct drm_dp_vsc_sdp - drm DP VSC SDP 77 * 78 * This structure represents a DP VSC SDP of drm 79 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 80 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 81 * 82 * @sdp_type: secondary-data packet type 83 * @revision: revision number 84 * @length: number of valid data bytes 85 * @pixelformat: pixel encoding format 86 * @colorimetry: colorimetry format 87 * @bpc: bit per color 88 * @dynamic_range: dynamic range information 89 * @content_type: CTA-861-G defines content types and expected processing by a sink device 90 */ 91 struct drm_dp_vsc_sdp { 92 unsigned char sdp_type; 93 unsigned char revision; 94 unsigned char length; 95 enum dp_pixelformat pixelformat; 96 enum dp_colorimetry colorimetry; 97 int bpc; 98 enum dp_dynamic_range dynamic_range; 99 enum dp_content_type content_type; 100 }; 101 102 /** 103 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP 104 * 105 * This structure represents a DP AS SDP of drm 106 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and 107 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] 108 * 109 * @sdp_type: Secondary-data packet type 110 * @revision: Revision Number 111 * @length: Number of valid data bytes 112 * @vtotal: Minimum Vertical Vtotal 113 * @target_rr: Target Refresh 114 * @duration_incr_ms: Successive frame duration increase 115 * @duration_decr_ms: Successive frame duration decrease 116 * @target_rr_divider: Target refresh rate divider 117 * @mode: Adaptive Sync Operation Mode 118 */ 119 struct drm_dp_as_sdp { 120 unsigned char sdp_type; 121 unsigned char revision; 122 unsigned char length; 123 int vtotal; 124 int target_rr; 125 int duration_incr_ms; 126 int duration_decr_ms; 127 bool target_rr_divider; 128 enum operation_mode mode; 129 }; 130 131 void drm_dp_as_sdp_log(struct drm_printer *p, 132 const struct drm_dp_as_sdp *as_sdp); 133 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); 134 135 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 136 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 137 138 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 139 140 static inline int 141 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 142 { 143 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 144 } 145 146 static inline u8 147 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 148 { 149 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 150 } 151 152 static inline bool 153 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 154 { 155 return dpcd[DP_DPCD_REV] >= 0x11 && 156 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 157 } 158 159 static inline bool 160 drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 161 { 162 return dpcd[DP_DPCD_REV] >= 0x13 && 163 (dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED); 164 } 165 166 static inline bool 167 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 168 { 169 return dpcd[DP_DPCD_REV] >= 0x11 && 170 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 171 } 172 173 static inline bool 174 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 175 { 176 return dpcd[DP_DPCD_REV] >= 0x12 && 177 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 178 } 179 180 static inline bool 181 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 182 { 183 return dpcd[DP_DPCD_REV] >= 0x11 || 184 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 185 } 186 187 static inline bool 188 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 189 { 190 return dpcd[DP_DPCD_REV] >= 0x14 && 191 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 192 } 193 194 static inline u8 195 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 196 { 197 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 198 DP_TRAINING_PATTERN_MASK; 199 } 200 201 static inline bool 202 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 203 { 204 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 205 } 206 207 /* DP/eDP DSC support */ 208 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 209 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 210 bool is_edp); 211 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 212 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 213 u8 dsc_bpc[3]); 214 215 static inline bool 216 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 217 { 218 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 219 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 220 } 221 222 static inline u16 223 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 224 { 225 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 226 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 227 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 228 } 229 230 static inline u32 231 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 232 { 233 /* Max Slicewidth = Number of Pixels * 320 */ 234 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 235 DP_DSC_SLICE_WIDTH_MULTIPLIER; 236 } 237 238 /** 239 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 240 * @dsc_dpcd : DSC-capability DPCDs of the sink 241 * @output_format: output_format which is to be checked 242 * 243 * Returns true if the sink supports DSC with the given output_format, false otherwise. 244 */ 245 static inline bool 246 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 247 { 248 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 249 } 250 251 /* Forward Error Correction Support on DP 1.4 */ 252 static inline bool 253 drm_dp_sink_supports_fec(const u8 fec_capable) 254 { 255 return fec_capable & DP_FEC_CAPABLE; 256 } 257 258 static inline bool 259 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 260 { 261 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 262 } 263 264 static inline bool 265 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 266 { 267 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; 268 } 269 270 static inline bool 271 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 272 { 273 return dpcd[DP_EDP_CONFIGURATION_CAP] & 274 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 275 } 276 277 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 278 static inline bool 279 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 280 { 281 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 282 DP_MSA_TIMING_PAR_IGNORED; 283 } 284 285 /** 286 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 287 * @edp_dpcd: The DPCD to check 288 * 289 * Note that currently this function will return %false for panels which support various DPCD 290 * backlight features but which require the brightness be set through PWM, and don't support setting 291 * the brightness level via the DPCD. 292 * 293 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 294 * otherwise 295 */ 296 static inline bool 297 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 298 { 299 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 300 } 301 302 /** 303 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR 304 * @link_rate: link rate in 10kbits/s units 305 * 306 * Determine if the provided link rate is an UHBR rate. 307 * 308 * Returns: %True if @link_rate is an UHBR rate. 309 */ 310 static inline bool drm_dp_is_uhbr_rate(int link_rate) 311 { 312 return link_rate >= 1000000; 313 } 314 315 /* 316 * DisplayPort AUX channel 317 */ 318 319 /** 320 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 321 * @address: address of the (first) register to access 322 * @request: contains the type of transaction (see DP_AUX_* macros) 323 * @reply: upon completion, contains the reply type of the transaction 324 * @buffer: pointer to a transmission or reception buffer 325 * @size: size of @buffer 326 */ 327 struct drm_dp_aux_msg { 328 unsigned int address; 329 u8 request; 330 u8 reply; 331 void *buffer; 332 size_t size; 333 }; 334 335 struct cec_adapter; 336 struct drm_connector; 337 struct drm_edid; 338 339 /** 340 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 341 * @lock: mutex protecting this struct 342 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 343 * @connector: the connector this CEC adapter is associated with 344 * @unregister_work: unregister the CEC adapter 345 */ 346 struct drm_dp_aux_cec { 347 struct mutex lock; 348 struct cec_adapter *adap; 349 struct drm_connector *connector; 350 struct delayed_work unregister_work; 351 }; 352 353 /** 354 * struct drm_dp_aux - DisplayPort AUX channel 355 * 356 * An AUX channel can also be used to transport I2C messages to a sink. A 357 * typical application of that is to access an EDID that's present in the sink 358 * device. The @transfer() function can also be used to execute such 359 * transactions. The drm_dp_aux_register() function registers an I2C adapter 360 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 361 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 362 * transfers by default; if a partial response is received, the adapter will 363 * drop down to the size given by the partial response for this transaction 364 * only. 365 */ 366 struct drm_dp_aux { 367 /** 368 * @name: user-visible name of this AUX channel and the 369 * I2C-over-AUX adapter. 370 * 371 * It's also used to specify the name of the I2C adapter. If set 372 * to %NULL, dev_name() of @dev will be used. 373 */ 374 const char *name; 375 376 /** 377 * @ddc: I2C adapter that can be used for I2C-over-AUX 378 * communication 379 */ 380 struct i2c_adapter ddc; 381 382 /** 383 * @dev: pointer to struct device that is the parent for this 384 * AUX channel. 385 */ 386 struct device *dev; 387 388 /** 389 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 390 * Beware, this may be %NULL before drm_dp_aux_register() has been 391 * called. 392 * 393 * It should be set to the &drm_device that will be using this AUX 394 * channel as early as possible. For many graphics drivers this should 395 * happen before drm_dp_aux_init(), however it's perfectly fine to set 396 * this field later so long as it's assigned before calling 397 * drm_dp_aux_register(). 398 */ 399 struct drm_device *drm_dev; 400 401 /** 402 * @crtc: backpointer to the crtc that is currently using this 403 * AUX channel 404 */ 405 struct drm_crtc *crtc; 406 407 /** 408 * @hw_mutex: internal mutex used for locking transfers. 409 * 410 * Note that if the underlying hardware is shared among multiple 411 * channels, the driver needs to do additional locking to 412 * prevent concurrent access. 413 */ 414 struct mutex hw_mutex; 415 416 /** 417 * @crc_work: worker that captures CRCs for each frame 418 */ 419 struct work_struct crc_work; 420 421 /** 422 * @crc_count: counter of captured frame CRCs 423 */ 424 u8 crc_count; 425 426 /** 427 * @transfer: transfers a message representing a single AUX 428 * transaction. 429 * 430 * This is a hardware-specific implementation of how 431 * transactions are executed that the drivers must provide. 432 * 433 * A pointer to a &drm_dp_aux_msg structure describing the 434 * transaction is passed into this function. Upon success, the 435 * implementation should return the number of payload bytes that 436 * were transferred, or a negative error-code on failure. 437 * 438 * Helpers will propagate these errors, with the exception of 439 * the %-EBUSY error, which causes a transaction to be retried. 440 * On a short, helpers will return %-EPROTO to make it simpler 441 * to check for failure. 442 * 443 * The @transfer() function must only modify the reply field of 444 * the &drm_dp_aux_msg structure. The retry logic and i2c 445 * helpers assume this is the case. 446 * 447 * Also note that this callback can be called no matter the 448 * state @dev is in and also no matter what state the panel is 449 * in. It's expected: 450 * 451 * - If the @dev providing the AUX bus is currently unpowered then 452 * it will power itself up for the transfer. 453 * 454 * - If we're on eDP (using a drm_panel) and the panel is not in a 455 * state where it can respond (it's not powered or it's in a 456 * low power state) then this function may return an error, but 457 * not crash. It's up to the caller of this code to make sure that 458 * the panel is powered on if getting an error back is not OK. If a 459 * drm_panel driver is initiating a DP AUX transfer it may power 460 * itself up however it wants. All other code should ensure that 461 * the pre_enable() bridge chain (which eventually calls the 462 * drm_panel prepare function) has powered the panel. 463 */ 464 ssize_t (*transfer)(struct drm_dp_aux *aux, 465 struct drm_dp_aux_msg *msg); 466 467 /** 468 * @wait_hpd_asserted: wait for HPD to be asserted 469 * 470 * This is mainly useful for eDP panels drivers to wait for an eDP 471 * panel to finish powering on. It is optional for DP AUX controllers 472 * to implement this function. It is required for DP AUX endpoints 473 * (panel drivers) to call this function after powering up but before 474 * doing AUX transfers unless the DP AUX endpoint driver knows that 475 * we're not using the AUX controller's HPD. One example of the panel 476 * driver not needing to call this is if HPD is hooked up to a GPIO 477 * that the panel driver can read directly. 478 * 479 * If a DP AUX controller does not implement this function then it 480 * may still support eDP panels that use the AUX controller's built-in 481 * HPD signal by implementing a long wait for HPD in the transfer() 482 * callback, though this is deprecated. 483 * 484 * This function will efficiently wait for the HPD signal to be 485 * asserted. The `wait_us` parameter that is passed in says that we 486 * know that the HPD signal is expected to be asserted within `wait_us` 487 * microseconds. This function could wait for longer than `wait_us` if 488 * the logic in the DP controller has a long debouncing time. The 489 * important thing is that if this function returns success that the 490 * DP controller is ready to send AUX transactions. 491 * 492 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 493 * expired and HPD wasn't asserted. This function should not print 494 * timeout errors to the log. 495 * 496 * The semantics of this function are designed to match the 497 * readx_poll_timeout() function. That means a `wait_us` of 0 means 498 * to wait forever. Like readx_poll_timeout(), this function may sleep. 499 * 500 * NOTE: this function specifically reports the state of the HPD pin 501 * that's associated with the DP AUX channel. This is different from 502 * the HPD concept in much of the rest of DRM which is more about 503 * physical presence of a display. For eDP, for instance, a display is 504 * assumed always present even if the HPD pin is deasserted. 505 */ 506 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 507 508 /** 509 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 510 */ 511 unsigned i2c_nack_count; 512 /** 513 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 514 */ 515 unsigned i2c_defer_count; 516 /** 517 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 518 */ 519 struct drm_dp_aux_cec cec; 520 /** 521 * @is_remote: Is this AUX CH actually using sideband messaging. 522 */ 523 bool is_remote; 524 525 /** 526 * @powered_down: If true then the remote endpoint is powered down. 527 */ 528 bool powered_down; 529 530 /** 531 * @no_zero_sized: If the hw can't use zero sized transfers (NVIDIA) 532 */ 533 bool no_zero_sized; 534 535 /** 536 * @dpcd_probe_disabled: If probing before a DPCD access is disabled. 537 */ 538 bool dpcd_probe_disabled; 539 }; 540 541 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 542 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered); 543 void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable); 544 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 545 void *buffer, size_t size); 546 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 547 void *buffer, size_t size); 548 549 /** 550 * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD 551 * @aux: DisplayPort AUX channel (SST or MST) 552 * @offset: address of the (first) register to read 553 * @buffer: buffer to store the register values 554 * @size: number of bytes in @buffer 555 * 556 * Returns zero (0) on success, or a negative error 557 * code on failure. -EIO is returned if the request was NAKed by the sink or 558 * if the retry count was exceeded. If not all bytes were transferred, this 559 * function returns -EPROTO. Errors from the underlying AUX channel transfer 560 * function, with the exception of -EBUSY (which causes the transaction to 561 * be retried), are propagated to the caller. 562 */ 563 static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux, 564 unsigned int offset, 565 void *buffer, size_t size) 566 { 567 int ret; 568 569 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 570 if (ret < 0) 571 return ret; 572 if (ret < size) 573 return -EPROTO; 574 575 return 0; 576 } 577 578 /** 579 * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD 580 * @aux: DisplayPort AUX channel (SST or MST) 581 * @offset: address of the (first) register to write 582 * @buffer: buffer containing the values to write 583 * @size: number of bytes in @buffer 584 * 585 * Returns zero (0) on success, or a negative error 586 * code on failure. -EIO is returned if the request was NAKed by the sink or 587 * if the retry count was exceeded. If not all bytes were transferred, this 588 * function returns -EPROTO. Errors from the underlying AUX channel transfer 589 * function, with the exception of -EBUSY (which causes the transaction to 590 * be retried), are propagated to the caller. 591 */ 592 static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux, 593 unsigned int offset, 594 void *buffer, size_t size) 595 { 596 int ret; 597 598 ret = drm_dp_dpcd_write(aux, offset, buffer, size); 599 if (ret < 0) 600 return ret; 601 if (ret < size) 602 return -EPROTO; 603 604 return 0; 605 } 606 607 /** 608 * drm_dp_dpcd_readb() - read a single byte from the DPCD 609 * @aux: DisplayPort AUX channel 610 * @offset: address of the register to read 611 * @valuep: location where the value of the register will be stored 612 * 613 * Returns the number of bytes transferred (1) on success, or a negative 614 * error code on failure. In most of the cases you should be using 615 * drm_dp_dpcd_read_byte() instead. 616 */ 617 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 618 unsigned int offset, u8 *valuep) 619 { 620 return drm_dp_dpcd_read(aux, offset, valuep, 1); 621 } 622 623 /** 624 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 625 * @aux: DisplayPort AUX channel 626 * @offset: address of the register to write 627 * @value: value to write to the register 628 * 629 * Returns the number of bytes transferred (1) on success, or a negative 630 * error code on failure. In most of the cases you should be using 631 * drm_dp_dpcd_write_byte() instead. 632 */ 633 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 634 unsigned int offset, u8 value) 635 { 636 return drm_dp_dpcd_write(aux, offset, &value, 1); 637 } 638 639 /** 640 * drm_dp_dpcd_read_byte() - read a single byte from the DPCD 641 * @aux: DisplayPort AUX channel 642 * @offset: address of the register to read 643 * @valuep: location where the value of the register will be stored 644 * 645 * Returns zero (0) on success, or a negative error code on failure. 646 */ 647 static inline int drm_dp_dpcd_read_byte(struct drm_dp_aux *aux, 648 unsigned int offset, u8 *valuep) 649 { 650 return drm_dp_dpcd_read_data(aux, offset, valuep, 1); 651 } 652 653 /** 654 * drm_dp_dpcd_write_byte() - write a single byte to the DPCD 655 * @aux: DisplayPort AUX channel 656 * @offset: address of the register to write 657 * @value: value to write to the register 658 * 659 * Returns zero (0) on success, or a negative error code on failure. 660 */ 661 static inline int drm_dp_dpcd_write_byte(struct drm_dp_aux *aux, 662 unsigned int offset, u8 value) 663 { 664 return drm_dp_dpcd_write_data(aux, offset, &value, 1); 665 } 666 667 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 668 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 669 670 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 671 u8 status[DP_LINK_STATUS_SIZE]); 672 673 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 674 enum drm_dp_phy dp_phy, 675 u8 link_status[DP_LINK_STATUS_SIZE]); 676 int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision); 677 int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision); 678 679 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux, 680 int vcpid, u8 start_time_slot, u8 time_slot_count); 681 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux); 682 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms); 683 684 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 685 u8 real_edid_checksum); 686 687 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 688 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 689 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 690 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 691 const u8 port_cap[4], u8 type); 692 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 693 const u8 port_cap[4], 694 const struct drm_edid *drm_edid); 695 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 696 const u8 port_cap[4]); 697 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 698 const u8 port_cap[4], 699 const struct drm_edid *drm_edid); 700 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 701 const u8 port_cap[4], 702 const struct drm_edid *drm_edid); 703 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 704 const u8 port_cap[4], 705 const struct drm_edid *drm_edid); 706 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 707 const u8 port_cap[4]); 708 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 709 const u8 port_cap[4]); 710 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 711 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 712 const u8 port_cap[4]); 713 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 714 void drm_dp_downstream_debug(struct seq_file *m, 715 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 716 const u8 port_cap[4], 717 const struct drm_edid *drm_edid, 718 struct drm_dp_aux *aux); 719 enum drm_mode_subconnector 720 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 721 const u8 port_cap[4]); 722 void drm_dp_set_subconnector_property(struct drm_connector *connector, 723 enum drm_connector_status status, 724 const u8 *dpcd, 725 const u8 port_cap[4]); 726 727 struct drm_dp_desc; 728 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 729 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 730 const struct drm_dp_desc *desc); 731 int drm_dp_read_sink_count(struct drm_dp_aux *aux); 732 733 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 734 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 735 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 736 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 737 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 738 enum drm_dp_phy dp_phy, 739 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 740 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 741 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 742 int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable); 743 int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count); 744 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 745 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 746 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 747 void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode); 748 749 void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 750 void drm_dp_aux_init(struct drm_dp_aux *aux); 751 int drm_dp_aux_register(struct drm_dp_aux *aux); 752 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 753 754 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 755 int drm_dp_stop_crc(struct drm_dp_aux *aux); 756 757 struct drm_dp_dpcd_ident { 758 u8 oui[3]; 759 u8 device_id[6]; 760 u8 hw_rev; 761 u8 sw_major_rev; 762 u8 sw_minor_rev; 763 } __packed; 764 765 /** 766 * struct drm_dp_desc - DP branch/sink device descriptor 767 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 768 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 769 */ 770 struct drm_dp_desc { 771 struct drm_dp_dpcd_ident ident; 772 u32 quirks; 773 }; 774 775 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 776 bool is_branch); 777 778 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy); 779 780 /** 781 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 782 * 783 * Display Port sink and branch devices in the wild have a variety of bugs, try 784 * to collect them here. The quirks are shared, but it's up to the drivers to 785 * implement workarounds for them. 786 */ 787 enum drm_dp_quirk { 788 /** 789 * @DP_DPCD_QUIRK_CONSTANT_N: 790 * 791 * The device requires main link attributes Mvid and Nvid to be limited 792 * to 16 bits. So will give a constant value (0x8000) for compatability. 793 */ 794 DP_DPCD_QUIRK_CONSTANT_N, 795 /** 796 * @DP_DPCD_QUIRK_NO_PSR: 797 * 798 * The device does not support PSR even if reports that it supports or 799 * driver still need to implement proper handling for such device. 800 */ 801 DP_DPCD_QUIRK_NO_PSR, 802 /** 803 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 804 * 805 * The device does not set SINK_COUNT to a non-zero value. 806 * The driver should ignore SINK_COUNT during detection. Note that 807 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 808 */ 809 DP_DPCD_QUIRK_NO_SINK_COUNT, 810 /** 811 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 812 * 813 * The device supports MST DSC despite not supporting Virtual DPCD. 814 * The DSC caps can be read from the physical aux instead. 815 */ 816 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 817 /** 818 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 819 * 820 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 821 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 822 */ 823 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 824 /** 825 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: 826 * 827 * The device applies HBLANK expansion for some modes, but this 828 * requires enabling DSC. 829 */ 830 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, 831 }; 832 833 /** 834 * drm_dp_has_quirk() - does the DP device have a specific quirk 835 * @desc: Device descriptor filled by drm_dp_read_desc() 836 * @quirk: Quirk to query for 837 * 838 * Return true if DP device identified by @desc has @quirk. 839 */ 840 static inline bool 841 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 842 { 843 return desc->quirks & BIT(quirk); 844 } 845 846 /** 847 * struct drm_edp_backlight_info - Probed eDP backlight info struct 848 * @pwmgen_bit_count: The pwmgen bit count 849 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 850 * @max: The maximum backlight level that may be set 851 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 852 * @aux_enable: Does the panel support the AUX enable cap? 853 * @aux_set: Does the panel support setting the brightness through AUX? 854 * @luminance_set: Does the panel support setting the brightness through AUX using luminance values? 855 * 856 * This structure contains various data about an eDP backlight, which can be populated by using 857 * drm_edp_backlight_init(). 858 */ 859 struct drm_edp_backlight_info { 860 u8 pwmgen_bit_count; 861 u8 pwm_freq_pre_divider; 862 u32 max; 863 864 bool lsb_reg_used : 1; 865 bool aux_enable : 1; 866 bool aux_set : 1; 867 bool luminance_set : 1; 868 }; 869 870 int 871 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 872 u32 max_luminance, 873 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 874 u32 *current_level, u8 *current_mode, bool need_luminance); 875 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 876 u32 level); 877 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 878 u32 level); 879 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 880 881 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 882 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 883 884 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 885 886 #else 887 888 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 889 struct drm_dp_aux *aux) 890 { 891 return 0; 892 } 893 894 #endif 895 896 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC 897 void drm_dp_cec_irq(struct drm_dp_aux *aux); 898 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 899 struct drm_connector *connector); 900 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 901 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); 902 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 903 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 904 #else 905 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 906 { 907 } 908 909 static inline void 910 drm_dp_cec_register_connector(struct drm_dp_aux *aux, 911 struct drm_connector *connector) 912 { 913 } 914 915 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 916 { 917 } 918 919 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, 920 u16 source_physical_address) 921 { 922 } 923 924 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 925 const struct edid *edid) 926 { 927 } 928 929 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 930 { 931 } 932 933 #endif 934 935 /** 936 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 937 * @link_rate: Requested Link rate from DPCD 0x219 938 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 939 * @phy_pattern: DP Phy test pattern from DPCD 0x248 940 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 941 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 942 * @enhanced_frame_cap: flag for enhanced frame capability. 943 */ 944 struct drm_dp_phy_test_params { 945 int link_rate; 946 u8 num_lanes; 947 u8 phy_pattern; 948 u8 hbr2_reset[2]; 949 u8 custom80[10]; 950 bool enhanced_frame_cap; 951 }; 952 953 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 954 struct drm_dp_phy_test_params *data); 955 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 956 struct drm_dp_phy_test_params *data, u8 dp_rev); 957 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 958 const u8 port_cap[4]); 959 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 960 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 961 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 962 u8 frl_mode); 963 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 964 u8 frl_type); 965 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 966 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 967 968 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 969 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 970 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 971 struct drm_connector *connector); 972 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 973 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 974 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 975 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 976 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 977 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 978 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 979 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 980 const u8 port_cap[4], u8 color_spc); 981 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 982 983 #define DRM_DP_BW_OVERHEAD_MST BIT(0) 984 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1) 985 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) 986 #define DRM_DP_BW_OVERHEAD_FEC BIT(3) 987 #define DRM_DP_BW_OVERHEAD_DSC BIT(4) 988 989 int drm_dp_bw_overhead(int lane_count, int hactive, 990 int dsc_slice_count, 991 int bpp_x16, unsigned long flags); 992 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); 993 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); 994 995 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp); 996 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count, 997 int bpp_x16, int symbol_size, bool is_mst); 998 999 #endif /* _DRM_DP_HELPER_H_ */ 1000