1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/delay.h> 27 #include <linux/i2c.h> 28 29 #include <drm/display/drm_dp.h> 30 #include <drm/drm_connector.h> 31 32 struct drm_device; 33 struct drm_dp_aux; 34 struct drm_panel; 35 36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40 bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]); 41 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 42 int lane); 43 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 44 int lane); 45 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 46 int lane); 47 48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 49 enum drm_dp_phy dp_phy, bool uhbr); 50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 51 enum drm_dp_phy dp_phy, bool uhbr); 52 53 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 55 void drm_dp_lttpr_link_train_clock_recovery_delay(void); 56 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 58 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 59 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 60 61 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 62 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 63 int lane_count); 64 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 65 int lane_count); 66 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 69 70 u8 drm_dp_link_rate_to_bw_code(int link_rate); 71 int drm_dp_bw_code_to_link_rate(u8 link_bw); 72 73 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 74 75 /** 76 * struct drm_dp_vsc_sdp - drm DP VSC SDP 77 * 78 * This structure represents a DP VSC SDP of drm 79 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 80 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 81 * 82 * @sdp_type: secondary-data packet type 83 * @revision: revision number 84 * @length: number of valid data bytes 85 * @pixelformat: pixel encoding format 86 * @colorimetry: colorimetry format 87 * @bpc: bit per color 88 * @dynamic_range: dynamic range information 89 * @content_type: CTA-861-G defines content types and expected processing by a sink device 90 */ 91 struct drm_dp_vsc_sdp { 92 unsigned char sdp_type; 93 unsigned char revision; 94 unsigned char length; 95 enum dp_pixelformat pixelformat; 96 enum dp_colorimetry colorimetry; 97 int bpc; 98 enum dp_dynamic_range dynamic_range; 99 enum dp_content_type content_type; 100 }; 101 102 /** 103 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP 104 * 105 * This structure represents a DP AS SDP of drm 106 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and 107 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] 108 * 109 * @sdp_type: Secondary-data packet type 110 * @revision: Revision Number 111 * @length: Number of valid data bytes 112 * @vtotal: Minimum Vertical Vtotal 113 * @target_rr: Target Refresh 114 * @duration_incr_ms: Successive frame duration increase 115 * @duration_decr_ms: Successive frame duration decrease 116 * @target_rr_divider: Target refresh rate divider 117 * @mode: Adaptive Sync Operation Mode 118 */ 119 struct drm_dp_as_sdp { 120 unsigned char sdp_type; 121 unsigned char revision; 122 unsigned char length; 123 int vtotal; 124 int target_rr; 125 int duration_incr_ms; 126 int duration_decr_ms; 127 bool target_rr_divider; 128 enum operation_mode mode; 129 }; 130 131 void drm_dp_as_sdp_log(struct drm_printer *p, 132 const struct drm_dp_as_sdp *as_sdp); 133 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); 134 135 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 136 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 137 138 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 139 140 static inline int 141 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 142 { 143 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 144 } 145 146 static inline u8 147 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 148 { 149 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 150 } 151 152 static inline bool 153 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 154 { 155 return dpcd[DP_DPCD_REV] >= 0x11 && 156 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 157 } 158 159 static inline bool 160 drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 161 { 162 return dpcd[DP_DPCD_REV] >= 0x13 && 163 (dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED); 164 } 165 166 static inline bool 167 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 168 { 169 return dpcd[DP_DPCD_REV] >= 0x11 && 170 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 171 } 172 173 static inline bool 174 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 175 { 176 return dpcd[DP_DPCD_REV] >= 0x12 && 177 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 178 } 179 180 static inline bool 181 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 182 { 183 return dpcd[DP_DPCD_REV] >= 0x11 || 184 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 185 } 186 187 static inline bool 188 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 189 { 190 return dpcd[DP_DPCD_REV] >= 0x14 && 191 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 192 } 193 194 static inline u8 195 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 196 { 197 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 198 DP_TRAINING_PATTERN_MASK; 199 } 200 201 static inline bool 202 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 203 { 204 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 205 } 206 207 /* DP/eDP DSC support */ 208 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 209 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 210 bool is_edp); 211 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 212 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 213 u8 dsc_bpc[3]); 214 int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 215 int peak_pixel_rate, bool is_rgb_yuv444); 216 int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE], 217 bool is_rgb_yuv444); 218 int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]); 219 220 static inline bool 221 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 222 { 223 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 224 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 225 } 226 227 static inline u16 228 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 229 { 230 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 231 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 232 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 233 } 234 235 static inline u32 236 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 237 { 238 /* Max Slicewidth = Number of Pixels * 320 */ 239 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 240 DP_DSC_SLICE_WIDTH_MULTIPLIER; 241 } 242 243 /** 244 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 245 * @dsc_dpcd : DSC-capability DPCDs of the sink 246 * @output_format: output_format which is to be checked 247 * 248 * Returns true if the sink supports DSC with the given output_format, false otherwise. 249 */ 250 static inline bool 251 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 252 { 253 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 254 } 255 256 /* Forward Error Correction Support on DP 1.4 */ 257 static inline bool 258 drm_dp_sink_supports_fec(const u8 fec_capable) 259 { 260 return fec_capable & DP_FEC_CAPABLE; 261 } 262 263 static inline bool 264 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 265 { 266 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 267 } 268 269 static inline bool 270 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 271 { 272 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; 273 } 274 275 static inline bool 276 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 277 { 278 return dpcd[DP_EDP_CONFIGURATION_CAP] & 279 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 280 } 281 282 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 283 static inline bool 284 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 285 { 286 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 287 DP_MSA_TIMING_PAR_IGNORED; 288 } 289 290 /** 291 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 292 * @edp_dpcd: The DPCD to check 293 * 294 * Note that currently this function will return %false for panels which support various DPCD 295 * backlight features but which require the brightness be set through PWM, and don't support setting 296 * the brightness level via the DPCD. 297 * 298 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 299 * otherwise 300 */ 301 static inline bool 302 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 303 { 304 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 305 } 306 307 /** 308 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR 309 * @link_rate: link rate in 10kbits/s units 310 * 311 * Determine if the provided link rate is an UHBR rate. 312 * 313 * Returns: %True if @link_rate is an UHBR rate. 314 */ 315 static inline bool drm_dp_is_uhbr_rate(int link_rate) 316 { 317 return link_rate >= 1000000; 318 } 319 320 /* 321 * DisplayPort AUX channel 322 */ 323 324 /** 325 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 326 * @address: address of the (first) register to access 327 * @request: contains the type of transaction (see DP_AUX_* macros) 328 * @reply: upon completion, contains the reply type of the transaction 329 * @buffer: pointer to a transmission or reception buffer 330 * @size: size of @buffer 331 */ 332 struct drm_dp_aux_msg { 333 unsigned int address; 334 u8 request; 335 u8 reply; 336 void *buffer; 337 size_t size; 338 }; 339 340 struct cec_adapter; 341 struct drm_connector; 342 struct drm_edid; 343 344 /** 345 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 346 * @lock: mutex protecting this struct 347 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 348 * @connector: the connector this CEC adapter is associated with 349 * @unregister_work: unregister the CEC adapter 350 */ 351 struct drm_dp_aux_cec { 352 struct mutex lock; 353 struct cec_adapter *adap; 354 struct drm_connector *connector; 355 struct delayed_work unregister_work; 356 }; 357 358 /** 359 * struct drm_dp_aux - DisplayPort AUX channel 360 * 361 * An AUX channel can also be used to transport I2C messages to a sink. A 362 * typical application of that is to access an EDID that's present in the sink 363 * device. The @transfer() function can also be used to execute such 364 * transactions. The drm_dp_aux_register() function registers an I2C adapter 365 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 366 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 367 * transfers by default; if a partial response is received, the adapter will 368 * drop down to the size given by the partial response for this transaction 369 * only. 370 */ 371 struct drm_dp_aux { 372 /** 373 * @name: user-visible name of this AUX channel and the 374 * I2C-over-AUX adapter. 375 * 376 * It's also used to specify the name of the I2C adapter. If set 377 * to %NULL, dev_name() of @dev will be used. 378 */ 379 const char *name; 380 381 /** 382 * @ddc: I2C adapter that can be used for I2C-over-AUX 383 * communication 384 */ 385 struct i2c_adapter ddc; 386 387 /** 388 * @dev: pointer to struct device that is the parent for this 389 * AUX channel. 390 */ 391 struct device *dev; 392 393 /** 394 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 395 * Beware, this may be %NULL before drm_dp_aux_register() has been 396 * called. 397 * 398 * It should be set to the &drm_device that will be using this AUX 399 * channel as early as possible. For many graphics drivers this should 400 * happen before drm_dp_aux_init(), however it's perfectly fine to set 401 * this field later so long as it's assigned before calling 402 * drm_dp_aux_register(). 403 */ 404 struct drm_device *drm_dev; 405 406 /** 407 * @crtc: backpointer to the crtc that is currently using this 408 * AUX channel 409 */ 410 struct drm_crtc *crtc; 411 412 /** 413 * @hw_mutex: internal mutex used for locking transfers. 414 * 415 * Note that if the underlying hardware is shared among multiple 416 * channels, the driver needs to do additional locking to 417 * prevent concurrent access. 418 */ 419 struct mutex hw_mutex; 420 421 /** 422 * @crc_work: worker that captures CRCs for each frame 423 */ 424 struct work_struct crc_work; 425 426 /** 427 * @crc_count: counter of captured frame CRCs 428 */ 429 u8 crc_count; 430 431 /** 432 * @transfer: transfers a message representing a single AUX 433 * transaction. 434 * 435 * This is a hardware-specific implementation of how 436 * transactions are executed that the drivers must provide. 437 * 438 * A pointer to a &drm_dp_aux_msg structure describing the 439 * transaction is passed into this function. Upon success, the 440 * implementation should return the number of payload bytes that 441 * were transferred, or a negative error-code on failure. 442 * 443 * Helpers will propagate these errors, with the exception of 444 * the %-EBUSY error, which causes a transaction to be retried. 445 * On a short, helpers will return %-EPROTO to make it simpler 446 * to check for failure. 447 * 448 * The @transfer() function must only modify the reply field of 449 * the &drm_dp_aux_msg structure. The retry logic and i2c 450 * helpers assume this is the case. 451 * 452 * Also note that this callback can be called no matter the 453 * state @dev is in and also no matter what state the panel is 454 * in. It's expected: 455 * 456 * - If the @dev providing the AUX bus is currently unpowered then 457 * it will power itself up for the transfer. 458 * 459 * - If we're on eDP (using a drm_panel) and the panel is not in a 460 * state where it can respond (it's not powered or it's in a 461 * low power state) then this function may return an error, but 462 * not crash. It's up to the caller of this code to make sure that 463 * the panel is powered on if getting an error back is not OK. If a 464 * drm_panel driver is initiating a DP AUX transfer it may power 465 * itself up however it wants. All other code should ensure that 466 * the pre_enable() bridge chain (which eventually calls the 467 * drm_panel prepare function) has powered the panel. 468 */ 469 ssize_t (*transfer)(struct drm_dp_aux *aux, 470 struct drm_dp_aux_msg *msg); 471 472 /** 473 * @wait_hpd_asserted: wait for HPD to be asserted 474 * 475 * This is mainly useful for eDP panels drivers to wait for an eDP 476 * panel to finish powering on. It is optional for DP AUX controllers 477 * to implement this function. It is required for DP AUX endpoints 478 * (panel drivers) to call this function after powering up but before 479 * doing AUX transfers unless the DP AUX endpoint driver knows that 480 * we're not using the AUX controller's HPD. One example of the panel 481 * driver not needing to call this is if HPD is hooked up to a GPIO 482 * that the panel driver can read directly. 483 * 484 * If a DP AUX controller does not implement this function then it 485 * may still support eDP panels that use the AUX controller's built-in 486 * HPD signal by implementing a long wait for HPD in the transfer() 487 * callback, though this is deprecated. 488 * 489 * This function will efficiently wait for the HPD signal to be 490 * asserted. The `wait_us` parameter that is passed in says that we 491 * know that the HPD signal is expected to be asserted within `wait_us` 492 * microseconds. This function could wait for longer than `wait_us` if 493 * the logic in the DP controller has a long debouncing time. The 494 * important thing is that if this function returns success that the 495 * DP controller is ready to send AUX transactions. 496 * 497 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 498 * expired and HPD wasn't asserted. This function should not print 499 * timeout errors to the log. 500 * 501 * The semantics of this function are designed to match the 502 * readx_poll_timeout() function. That means a `wait_us` of 0 means 503 * to wait forever. Like readx_poll_timeout(), this function may sleep. 504 * 505 * NOTE: this function specifically reports the state of the HPD pin 506 * that's associated with the DP AUX channel. This is different from 507 * the HPD concept in much of the rest of DRM which is more about 508 * physical presence of a display. For eDP, for instance, a display is 509 * assumed always present even if the HPD pin is deasserted. 510 */ 511 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 512 513 /** 514 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 515 */ 516 unsigned i2c_nack_count; 517 /** 518 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 519 */ 520 unsigned i2c_defer_count; 521 /** 522 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 523 */ 524 struct drm_dp_aux_cec cec; 525 /** 526 * @is_remote: Is this AUX CH actually using sideband messaging. 527 */ 528 bool is_remote; 529 530 /** 531 * @powered_down: If true then the remote endpoint is powered down. 532 */ 533 bool powered_down; 534 535 /** 536 * @no_zero_sized: If the hw can't use zero sized transfers (NVIDIA) 537 */ 538 bool no_zero_sized; 539 540 /** 541 * @dpcd_probe_disabled: If probing before a DPCD access is disabled. 542 */ 543 bool dpcd_probe_disabled; 544 }; 545 546 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 547 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered); 548 void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable); 549 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 550 void *buffer, size_t size); 551 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 552 void *buffer, size_t size); 553 554 /** 555 * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD 556 * @aux: DisplayPort AUX channel (SST or MST) 557 * @offset: address of the (first) register to read 558 * @buffer: buffer to store the register values 559 * @size: number of bytes in @buffer 560 * 561 * Returns zero (0) on success, or a negative error 562 * code on failure. -EIO is returned if the request was NAKed by the sink or 563 * if the retry count was exceeded. If not all bytes were transferred, this 564 * function returns -EPROTO. Errors from the underlying AUX channel transfer 565 * function, with the exception of -EBUSY (which causes the transaction to 566 * be retried), are propagated to the caller. 567 */ 568 static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux, 569 unsigned int offset, 570 void *buffer, size_t size) 571 { 572 int ret; 573 574 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 575 if (ret < 0) 576 return ret; 577 if (ret < size) 578 return -EPROTO; 579 580 return 0; 581 } 582 583 /** 584 * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD 585 * @aux: DisplayPort AUX channel (SST or MST) 586 * @offset: address of the (first) register to write 587 * @buffer: buffer containing the values to write 588 * @size: number of bytes in @buffer 589 * 590 * Returns zero (0) on success, or a negative error 591 * code on failure. -EIO is returned if the request was NAKed by the sink or 592 * if the retry count was exceeded. If not all bytes were transferred, this 593 * function returns -EPROTO. Errors from the underlying AUX channel transfer 594 * function, with the exception of -EBUSY (which causes the transaction to 595 * be retried), are propagated to the caller. 596 */ 597 static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux, 598 unsigned int offset, 599 void *buffer, size_t size) 600 { 601 int ret; 602 603 ret = drm_dp_dpcd_write(aux, offset, buffer, size); 604 if (ret < 0) 605 return ret; 606 if (ret < size) 607 return -EPROTO; 608 609 return 0; 610 } 611 612 /** 613 * drm_dp_dpcd_readb() - read a single byte from the DPCD 614 * @aux: DisplayPort AUX channel 615 * @offset: address of the register to read 616 * @valuep: location where the value of the register will be stored 617 * 618 * Returns the number of bytes transferred (1) on success, or a negative 619 * error code on failure. In most of the cases you should be using 620 * drm_dp_dpcd_read_byte() instead. 621 */ 622 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 623 unsigned int offset, u8 *valuep) 624 { 625 return drm_dp_dpcd_read(aux, offset, valuep, 1); 626 } 627 628 /** 629 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 630 * @aux: DisplayPort AUX channel 631 * @offset: address of the register to write 632 * @value: value to write to the register 633 * 634 * Returns the number of bytes transferred (1) on success, or a negative 635 * error code on failure. In most of the cases you should be using 636 * drm_dp_dpcd_write_byte() instead. 637 */ 638 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 639 unsigned int offset, u8 value) 640 { 641 return drm_dp_dpcd_write(aux, offset, &value, 1); 642 } 643 644 /** 645 * drm_dp_dpcd_read_byte() - read a single byte from the DPCD 646 * @aux: DisplayPort AUX channel 647 * @offset: address of the register to read 648 * @valuep: location where the value of the register will be stored 649 * 650 * Returns zero (0) on success, or a negative error code on failure. 651 */ 652 static inline int drm_dp_dpcd_read_byte(struct drm_dp_aux *aux, 653 unsigned int offset, u8 *valuep) 654 { 655 return drm_dp_dpcd_read_data(aux, offset, valuep, 1); 656 } 657 658 /** 659 * drm_dp_dpcd_write_byte() - write a single byte to the DPCD 660 * @aux: DisplayPort AUX channel 661 * @offset: address of the register to write 662 * @value: value to write to the register 663 * 664 * Returns zero (0) on success, or a negative error code on failure. 665 */ 666 static inline int drm_dp_dpcd_write_byte(struct drm_dp_aux *aux, 667 unsigned int offset, u8 value) 668 { 669 return drm_dp_dpcd_write_data(aux, offset, &value, 1); 670 } 671 672 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 673 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 674 675 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 676 u8 status[DP_LINK_STATUS_SIZE]); 677 678 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 679 enum drm_dp_phy dp_phy, 680 u8 link_status[DP_LINK_STATUS_SIZE]); 681 int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision); 682 int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision); 683 684 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux, 685 int vcpid, u8 start_time_slot, u8 time_slot_count); 686 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux); 687 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms); 688 689 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 690 u8 real_edid_checksum); 691 692 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 693 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 694 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 695 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 696 const u8 port_cap[4], u8 type); 697 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 698 const u8 port_cap[4], 699 const struct drm_edid *drm_edid); 700 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 701 const u8 port_cap[4]); 702 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 703 const u8 port_cap[4], 704 const struct drm_edid *drm_edid); 705 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 706 const u8 port_cap[4], 707 const struct drm_edid *drm_edid); 708 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 709 const u8 port_cap[4], 710 const struct drm_edid *drm_edid); 711 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 712 const u8 port_cap[4]); 713 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 714 const u8 port_cap[4]); 715 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 716 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 717 const u8 port_cap[4]); 718 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 719 void drm_dp_downstream_debug(struct seq_file *m, 720 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 721 const u8 port_cap[4], 722 const struct drm_edid *drm_edid, 723 struct drm_dp_aux *aux); 724 enum drm_mode_subconnector 725 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 726 const u8 port_cap[4]); 727 void drm_dp_set_subconnector_property(struct drm_connector *connector, 728 enum drm_connector_status status, 729 const u8 *dpcd, 730 const u8 port_cap[4]); 731 732 struct drm_dp_desc; 733 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 734 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 735 const struct drm_dp_desc *desc); 736 int drm_dp_read_sink_count(struct drm_dp_aux *aux); 737 738 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 739 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 740 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 741 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 742 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 743 enum drm_dp_phy dp_phy, 744 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 745 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 746 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 747 int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable); 748 int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count); 749 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 750 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 751 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 752 void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode); 753 754 void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 755 void drm_dp_aux_init(struct drm_dp_aux *aux); 756 int drm_dp_aux_register(struct drm_dp_aux *aux); 757 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 758 759 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 760 int drm_dp_stop_crc(struct drm_dp_aux *aux); 761 762 struct drm_dp_dpcd_ident { 763 u8 oui[3]; 764 u8 device_id[6]; 765 u8 hw_rev; 766 u8 sw_major_rev; 767 u8 sw_minor_rev; 768 } __packed; 769 770 /** 771 * struct drm_dp_desc - DP branch/sink device descriptor 772 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 773 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 774 */ 775 struct drm_dp_desc { 776 struct drm_dp_dpcd_ident ident; 777 u32 quirks; 778 }; 779 780 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 781 bool is_branch); 782 783 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy); 784 785 /** 786 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 787 * 788 * Display Port sink and branch devices in the wild have a variety of bugs, try 789 * to collect them here. The quirks are shared, but it's up to the drivers to 790 * implement workarounds for them. 791 */ 792 enum drm_dp_quirk { 793 /** 794 * @DP_DPCD_QUIRK_CONSTANT_N: 795 * 796 * The device requires main link attributes Mvid and Nvid to be limited 797 * to 16 bits. So will give a constant value (0x8000) for compatability. 798 */ 799 DP_DPCD_QUIRK_CONSTANT_N, 800 /** 801 * @DP_DPCD_QUIRK_NO_PSR: 802 * 803 * The device does not support PSR even if reports that it supports or 804 * driver still need to implement proper handling for such device. 805 */ 806 DP_DPCD_QUIRK_NO_PSR, 807 /** 808 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 809 * 810 * The device does not set SINK_COUNT to a non-zero value. 811 * The driver should ignore SINK_COUNT during detection. Note that 812 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 813 */ 814 DP_DPCD_QUIRK_NO_SINK_COUNT, 815 /** 816 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 817 * 818 * The device supports MST DSC despite not supporting Virtual DPCD. 819 * The DSC caps can be read from the physical aux instead. 820 */ 821 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 822 /** 823 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 824 * 825 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 826 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 827 */ 828 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 829 /** 830 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: 831 * 832 * The device applies HBLANK expansion for some modes, but this 833 * requires enabling DSC. 834 */ 835 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, 836 /** 837 * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT: 838 * 839 * The device doesn't support DSC decompression at the maximum DSC 840 * pixel throughput and compressed bpp it indicates via its DPCD DSC 841 * capabilities. The compressed bpp must be limited above a device 842 * specific DSC pixel throughput. 843 */ 844 DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT, 845 }; 846 847 /** 848 * drm_dp_has_quirk() - does the DP device have a specific quirk 849 * @desc: Device descriptor filled by drm_dp_read_desc() 850 * @quirk: Quirk to query for 851 * 852 * Return true if DP device identified by @desc has @quirk. 853 */ 854 static inline bool 855 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 856 { 857 return desc->quirks & BIT(quirk); 858 } 859 860 /** 861 * struct drm_edp_backlight_info - Probed eDP backlight info struct 862 * @pwmgen_bit_count: The pwmgen bit count 863 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 864 * @max: The maximum backlight level that may be set 865 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 866 * @aux_enable: Does the panel support the AUX enable cap? 867 * @aux_set: Does the panel support setting the brightness through AUX? 868 * @luminance_set: Does the panel support setting the brightness through AUX using luminance values? 869 * 870 * This structure contains various data about an eDP backlight, which can be populated by using 871 * drm_edp_backlight_init(). 872 */ 873 struct drm_edp_backlight_info { 874 u8 pwmgen_bit_count; 875 u8 pwm_freq_pre_divider; 876 u32 max; 877 878 bool lsb_reg_used : 1; 879 bool aux_enable : 1; 880 bool aux_set : 1; 881 bool luminance_set : 1; 882 }; 883 884 int 885 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 886 u32 max_luminance, 887 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 888 u32 *current_level, u8 *current_mode, bool need_luminance); 889 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 890 u32 level); 891 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 892 u32 level); 893 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 894 895 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 896 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 897 898 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 899 900 #else 901 902 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 903 struct drm_dp_aux *aux) 904 { 905 return 0; 906 } 907 908 #endif 909 910 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC 911 void drm_dp_cec_irq(struct drm_dp_aux *aux); 912 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 913 struct drm_connector *connector); 914 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 915 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); 916 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 917 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 918 #else 919 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 920 { 921 } 922 923 static inline void 924 drm_dp_cec_register_connector(struct drm_dp_aux *aux, 925 struct drm_connector *connector) 926 { 927 } 928 929 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 930 { 931 } 932 933 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, 934 u16 source_physical_address) 935 { 936 } 937 938 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 939 const struct edid *edid) 940 { 941 } 942 943 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 944 { 945 } 946 947 #endif 948 949 /** 950 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 951 * @link_rate: Requested Link rate from DPCD 0x219 952 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 953 * @phy_pattern: DP Phy test pattern from DPCD 0x248 954 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 955 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 956 * @enhanced_frame_cap: flag for enhanced frame capability. 957 */ 958 struct drm_dp_phy_test_params { 959 int link_rate; 960 u8 num_lanes; 961 u8 phy_pattern; 962 u8 hbr2_reset[2]; 963 u8 custom80[10]; 964 bool enhanced_frame_cap; 965 }; 966 967 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 968 struct drm_dp_phy_test_params *data); 969 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 970 struct drm_dp_phy_test_params *data, u8 dp_rev); 971 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 972 const u8 port_cap[4]); 973 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 974 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 975 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 976 u8 frl_mode); 977 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 978 u8 frl_type); 979 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 980 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 981 982 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 983 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 984 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 985 struct drm_connector *connector); 986 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 987 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 988 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 989 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 990 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 991 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 992 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 993 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 994 const u8 port_cap[4], u8 color_spc); 995 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 996 997 #define DRM_DP_BW_OVERHEAD_MST BIT(0) 998 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1) 999 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) 1000 #define DRM_DP_BW_OVERHEAD_FEC BIT(3) 1001 #define DRM_DP_BW_OVERHEAD_DSC BIT(4) 1002 1003 int drm_dp_bw_overhead(int lane_count, int hactive, 1004 int dsc_slice_count, 1005 int bpp_x16, unsigned long flags); 1006 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); 1007 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); 1008 1009 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp); 1010 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count, 1011 int bpp_x16, int symbol_size, bool is_mst); 1012 1013 #endif /* _DRM_DP_HELPER_H_ */ 1014