1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/delay.h> 27 #include <linux/i2c.h> 28 29 #include <drm/display/drm_dp.h> 30 #include <drm/drm_connector.h> 31 32 struct drm_device; 33 struct drm_dp_aux; 34 struct drm_panel; 35 36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 41 int lane); 42 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 43 int lane); 44 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 45 int lane); 46 47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 48 enum drm_dp_phy dp_phy, bool uhbr); 49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 50 enum drm_dp_phy dp_phy, bool uhbr); 51 52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 54 void drm_dp_lttpr_link_train_clock_recovery_delay(void); 55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 59 60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 61 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 62 int lane_count); 63 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 64 int lane_count); 65 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 66 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 69 u8 drm_dp_link_rate_to_bw_code(int link_rate); 70 int drm_dp_bw_code_to_link_rate(u8 link_bw); 71 72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 73 74 /** 75 * struct drm_dp_vsc_sdp - drm DP VSC SDP 76 * 77 * This structure represents a DP VSC SDP of drm 78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 79 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 80 * 81 * @sdp_type: secondary-data packet type 82 * @revision: revision number 83 * @length: number of valid data bytes 84 * @pixelformat: pixel encoding format 85 * @colorimetry: colorimetry format 86 * @bpc: bit per color 87 * @dynamic_range: dynamic range information 88 * @content_type: CTA-861-G defines content types and expected processing by a sink device 89 */ 90 struct drm_dp_vsc_sdp { 91 unsigned char sdp_type; 92 unsigned char revision; 93 unsigned char length; 94 enum dp_pixelformat pixelformat; 95 enum dp_colorimetry colorimetry; 96 int bpc; 97 enum dp_dynamic_range dynamic_range; 98 enum dp_content_type content_type; 99 }; 100 101 /** 102 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP 103 * 104 * This structure represents a DP AS SDP of drm 105 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and 106 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] 107 * 108 * @sdp_type: Secondary-data packet type 109 * @revision: Revision Number 110 * @length: Number of valid data bytes 111 * @vtotal: Minimum Vertical Vtotal 112 * @target_rr: Target Refresh 113 * @duration_incr_ms: Successive frame duration increase 114 * @duration_decr_ms: Successive frame duration decrease 115 * @mode: Adaptive Sync Operation Mode 116 */ 117 struct drm_dp_as_sdp { 118 unsigned char sdp_type; 119 unsigned char revision; 120 unsigned char length; 121 int vtotal; 122 int target_rr; 123 int duration_incr_ms; 124 int duration_decr_ms; 125 bool target_rr_divider; 126 enum operation_mode mode; 127 }; 128 129 void drm_dp_as_sdp_log(struct drm_printer *p, 130 const struct drm_dp_as_sdp *as_sdp); 131 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); 132 133 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 134 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 135 136 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 137 138 static inline int 139 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 140 { 141 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 142 } 143 144 static inline u8 145 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 146 { 147 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 148 } 149 150 static inline bool 151 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 152 { 153 return dpcd[DP_DPCD_REV] >= 0x11 && 154 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 155 } 156 157 static inline bool 158 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 159 { 160 return dpcd[DP_DPCD_REV] >= 0x11 && 161 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 162 } 163 164 static inline bool 165 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 166 { 167 return dpcd[DP_DPCD_REV] >= 0x12 && 168 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 169 } 170 171 static inline bool 172 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 173 { 174 return dpcd[DP_DPCD_REV] >= 0x11 || 175 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 176 } 177 178 static inline bool 179 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 180 { 181 return dpcd[DP_DPCD_REV] >= 0x14 && 182 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 183 } 184 185 static inline u8 186 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 187 { 188 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 189 DP_TRAINING_PATTERN_MASK; 190 } 191 192 static inline bool 193 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 194 { 195 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 196 } 197 198 /* DP/eDP DSC support */ 199 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 200 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 201 bool is_edp); 202 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 203 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 204 u8 dsc_bpc[3]); 205 206 static inline bool 207 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 208 { 209 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 210 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 211 } 212 213 static inline u16 214 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 215 { 216 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 217 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 218 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 219 } 220 221 static inline u32 222 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 223 { 224 /* Max Slicewidth = Number of Pixels * 320 */ 225 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 226 DP_DSC_SLICE_WIDTH_MULTIPLIER; 227 } 228 229 /** 230 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 231 * @dsc_dpcd : DSC-capability DPCDs of the sink 232 * @output_format: output_format which is to be checked 233 * 234 * Returns true if the sink supports DSC with the given output_format, false otherwise. 235 */ 236 static inline bool 237 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 238 { 239 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 240 } 241 242 /* Forward Error Correction Support on DP 1.4 */ 243 static inline bool 244 drm_dp_sink_supports_fec(const u8 fec_capable) 245 { 246 return fec_capable & DP_FEC_CAPABLE; 247 } 248 249 static inline bool 250 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 251 { 252 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 253 } 254 255 static inline bool 256 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 257 { 258 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; 259 } 260 261 static inline bool 262 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 263 { 264 return dpcd[DP_EDP_CONFIGURATION_CAP] & 265 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 266 } 267 268 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 269 static inline bool 270 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 271 { 272 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 273 DP_MSA_TIMING_PAR_IGNORED; 274 } 275 276 /** 277 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 278 * @edp_dpcd: The DPCD to check 279 * 280 * Note that currently this function will return %false for panels which support various DPCD 281 * backlight features but which require the brightness be set through PWM, and don't support setting 282 * the brightness level via the DPCD. 283 * 284 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 285 * otherwise 286 */ 287 static inline bool 288 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 289 { 290 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 291 } 292 293 /** 294 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR 295 * @link_rate: link rate in 10kbits/s units 296 * 297 * Determine if the provided link rate is an UHBR rate. 298 * 299 * Returns: %True if @link_rate is an UHBR rate. 300 */ 301 static inline bool drm_dp_is_uhbr_rate(int link_rate) 302 { 303 return link_rate >= 1000000; 304 } 305 306 /* 307 * DisplayPort AUX channel 308 */ 309 310 /** 311 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 312 * @address: address of the (first) register to access 313 * @request: contains the type of transaction (see DP_AUX_* macros) 314 * @reply: upon completion, contains the reply type of the transaction 315 * @buffer: pointer to a transmission or reception buffer 316 * @size: size of @buffer 317 */ 318 struct drm_dp_aux_msg { 319 unsigned int address; 320 u8 request; 321 u8 reply; 322 void *buffer; 323 size_t size; 324 }; 325 326 struct cec_adapter; 327 struct drm_connector; 328 struct drm_edid; 329 330 /** 331 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 332 * @lock: mutex protecting this struct 333 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 334 * @connector: the connector this CEC adapter is associated with 335 * @unregister_work: unregister the CEC adapter 336 */ 337 struct drm_dp_aux_cec { 338 struct mutex lock; 339 struct cec_adapter *adap; 340 struct drm_connector *connector; 341 struct delayed_work unregister_work; 342 }; 343 344 /** 345 * struct drm_dp_aux - DisplayPort AUX channel 346 * 347 * An AUX channel can also be used to transport I2C messages to a sink. A 348 * typical application of that is to access an EDID that's present in the sink 349 * device. The @transfer() function can also be used to execute such 350 * transactions. The drm_dp_aux_register() function registers an I2C adapter 351 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 352 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 353 * transfers by default; if a partial response is received, the adapter will 354 * drop down to the size given by the partial response for this transaction 355 * only. 356 */ 357 struct drm_dp_aux { 358 /** 359 * @name: user-visible name of this AUX channel and the 360 * I2C-over-AUX adapter. 361 * 362 * It's also used to specify the name of the I2C adapter. If set 363 * to %NULL, dev_name() of @dev will be used. 364 */ 365 const char *name; 366 367 /** 368 * @ddc: I2C adapter that can be used for I2C-over-AUX 369 * communication 370 */ 371 struct i2c_adapter ddc; 372 373 /** 374 * @dev: pointer to struct device that is the parent for this 375 * AUX channel. 376 */ 377 struct device *dev; 378 379 /** 380 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 381 * Beware, this may be %NULL before drm_dp_aux_register() has been 382 * called. 383 * 384 * It should be set to the &drm_device that will be using this AUX 385 * channel as early as possible. For many graphics drivers this should 386 * happen before drm_dp_aux_init(), however it's perfectly fine to set 387 * this field later so long as it's assigned before calling 388 * drm_dp_aux_register(). 389 */ 390 struct drm_device *drm_dev; 391 392 /** 393 * @crtc: backpointer to the crtc that is currently using this 394 * AUX channel 395 */ 396 struct drm_crtc *crtc; 397 398 /** 399 * @hw_mutex: internal mutex used for locking transfers. 400 * 401 * Note that if the underlying hardware is shared among multiple 402 * channels, the driver needs to do additional locking to 403 * prevent concurrent access. 404 */ 405 struct mutex hw_mutex; 406 407 /** 408 * @crc_work: worker that captures CRCs for each frame 409 */ 410 struct work_struct crc_work; 411 412 /** 413 * @crc_count: counter of captured frame CRCs 414 */ 415 u8 crc_count; 416 417 /** 418 * @transfer: transfers a message representing a single AUX 419 * transaction. 420 * 421 * This is a hardware-specific implementation of how 422 * transactions are executed that the drivers must provide. 423 * 424 * A pointer to a &drm_dp_aux_msg structure describing the 425 * transaction is passed into this function. Upon success, the 426 * implementation should return the number of payload bytes that 427 * were transferred, or a negative error-code on failure. 428 * 429 * Helpers will propagate these errors, with the exception of 430 * the %-EBUSY error, which causes a transaction to be retried. 431 * On a short, helpers will return %-EPROTO to make it simpler 432 * to check for failure. 433 * 434 * The @transfer() function must only modify the reply field of 435 * the &drm_dp_aux_msg structure. The retry logic and i2c 436 * helpers assume this is the case. 437 * 438 * Also note that this callback can be called no matter the 439 * state @dev is in and also no matter what state the panel is 440 * in. It's expected: 441 * 442 * - If the @dev providing the AUX bus is currently unpowered then 443 * it will power itself up for the transfer. 444 * 445 * - If we're on eDP (using a drm_panel) and the panel is not in a 446 * state where it can respond (it's not powered or it's in a 447 * low power state) then this function may return an error, but 448 * not crash. It's up to the caller of this code to make sure that 449 * the panel is powered on if getting an error back is not OK. If a 450 * drm_panel driver is initiating a DP AUX transfer it may power 451 * itself up however it wants. All other code should ensure that 452 * the pre_enable() bridge chain (which eventually calls the 453 * drm_panel prepare function) has powered the panel. 454 */ 455 ssize_t (*transfer)(struct drm_dp_aux *aux, 456 struct drm_dp_aux_msg *msg); 457 458 /** 459 * @wait_hpd_asserted: wait for HPD to be asserted 460 * 461 * This is mainly useful for eDP panels drivers to wait for an eDP 462 * panel to finish powering on. It is optional for DP AUX controllers 463 * to implement this function. It is required for DP AUX endpoints 464 * (panel drivers) to call this function after powering up but before 465 * doing AUX transfers unless the DP AUX endpoint driver knows that 466 * we're not using the AUX controller's HPD. One example of the panel 467 * driver not needing to call this is if HPD is hooked up to a GPIO 468 * that the panel driver can read directly. 469 * 470 * If a DP AUX controller does not implement this function then it 471 * may still support eDP panels that use the AUX controller's built-in 472 * HPD signal by implementing a long wait for HPD in the transfer() 473 * callback, though this is deprecated. 474 * 475 * This function will efficiently wait for the HPD signal to be 476 * asserted. The `wait_us` parameter that is passed in says that we 477 * know that the HPD signal is expected to be asserted within `wait_us` 478 * microseconds. This function could wait for longer than `wait_us` if 479 * the logic in the DP controller has a long debouncing time. The 480 * important thing is that if this function returns success that the 481 * DP controller is ready to send AUX transactions. 482 * 483 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 484 * expired and HPD wasn't asserted. This function should not print 485 * timeout errors to the log. 486 * 487 * The semantics of this function are designed to match the 488 * readx_poll_timeout() function. That means a `wait_us` of 0 means 489 * to wait forever. Like readx_poll_timeout(), this function may sleep. 490 * 491 * NOTE: this function specifically reports the state of the HPD pin 492 * that's associated with the DP AUX channel. This is different from 493 * the HPD concept in much of the rest of DRM which is more about 494 * physical presence of a display. For eDP, for instance, a display is 495 * assumed always present even if the HPD pin is deasserted. 496 */ 497 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 498 499 /** 500 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 501 */ 502 unsigned i2c_nack_count; 503 /** 504 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 505 */ 506 unsigned i2c_defer_count; 507 /** 508 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 509 */ 510 struct drm_dp_aux_cec cec; 511 /** 512 * @is_remote: Is this AUX CH actually using sideband messaging. 513 */ 514 bool is_remote; 515 516 /** 517 * @powered_down: If true then the remote endpoint is powered down. 518 */ 519 bool powered_down; 520 }; 521 522 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 523 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered); 524 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 525 void *buffer, size_t size); 526 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 527 void *buffer, size_t size); 528 529 /** 530 * drm_dp_dpcd_readb() - read a single byte from the DPCD 531 * @aux: DisplayPort AUX channel 532 * @offset: address of the register to read 533 * @valuep: location where the value of the register will be stored 534 * 535 * Returns the number of bytes transferred (1) on success, or a negative 536 * error code on failure. 537 */ 538 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 539 unsigned int offset, u8 *valuep) 540 { 541 return drm_dp_dpcd_read(aux, offset, valuep, 1); 542 } 543 544 /** 545 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 546 * @aux: DisplayPort AUX channel 547 * @offset: address of the register to write 548 * @value: value to write to the register 549 * 550 * Returns the number of bytes transferred (1) on success, or a negative 551 * error code on failure. 552 */ 553 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 554 unsigned int offset, u8 value) 555 { 556 return drm_dp_dpcd_write(aux, offset, &value, 1); 557 } 558 559 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 560 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 561 562 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 563 u8 status[DP_LINK_STATUS_SIZE]); 564 565 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 566 enum drm_dp_phy dp_phy, 567 u8 link_status[DP_LINK_STATUS_SIZE]); 568 569 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 570 u8 real_edid_checksum); 571 572 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 573 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 574 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 575 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 576 const u8 port_cap[4], u8 type); 577 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 578 const u8 port_cap[4], 579 const struct drm_edid *drm_edid); 580 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 581 const u8 port_cap[4]); 582 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 583 const u8 port_cap[4], 584 const struct drm_edid *drm_edid); 585 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 586 const u8 port_cap[4], 587 const struct drm_edid *drm_edid); 588 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 589 const u8 port_cap[4], 590 const struct drm_edid *drm_edid); 591 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 592 const u8 port_cap[4]); 593 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 594 const u8 port_cap[4]); 595 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 596 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 597 const u8 port_cap[4]); 598 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 599 void drm_dp_downstream_debug(struct seq_file *m, 600 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 601 const u8 port_cap[4], 602 const struct drm_edid *drm_edid, 603 struct drm_dp_aux *aux); 604 enum drm_mode_subconnector 605 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 606 const u8 port_cap[4]); 607 void drm_dp_set_subconnector_property(struct drm_connector *connector, 608 enum drm_connector_status status, 609 const u8 *dpcd, 610 const u8 port_cap[4]); 611 612 struct drm_dp_desc; 613 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 614 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 615 const struct drm_dp_desc *desc); 616 int drm_dp_read_sink_count(struct drm_dp_aux *aux); 617 618 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 619 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 620 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 621 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 622 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 623 enum drm_dp_phy dp_phy, 624 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 625 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 626 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 627 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 628 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 629 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 630 631 void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 632 void drm_dp_aux_init(struct drm_dp_aux *aux); 633 int drm_dp_aux_register(struct drm_dp_aux *aux); 634 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 635 636 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 637 int drm_dp_stop_crc(struct drm_dp_aux *aux); 638 639 struct drm_dp_dpcd_ident { 640 u8 oui[3]; 641 u8 device_id[6]; 642 u8 hw_rev; 643 u8 sw_major_rev; 644 u8 sw_minor_rev; 645 } __packed; 646 647 /** 648 * struct drm_dp_desc - DP branch/sink device descriptor 649 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 650 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 651 */ 652 struct drm_dp_desc { 653 struct drm_dp_dpcd_ident ident; 654 u32 quirks; 655 }; 656 657 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 658 bool is_branch); 659 660 /** 661 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 662 * 663 * Display Port sink and branch devices in the wild have a variety of bugs, try 664 * to collect them here. The quirks are shared, but it's up to the drivers to 665 * implement workarounds for them. 666 */ 667 enum drm_dp_quirk { 668 /** 669 * @DP_DPCD_QUIRK_CONSTANT_N: 670 * 671 * The device requires main link attributes Mvid and Nvid to be limited 672 * to 16 bits. So will give a constant value (0x8000) for compatability. 673 */ 674 DP_DPCD_QUIRK_CONSTANT_N, 675 /** 676 * @DP_DPCD_QUIRK_NO_PSR: 677 * 678 * The device does not support PSR even if reports that it supports or 679 * driver still need to implement proper handling for such device. 680 */ 681 DP_DPCD_QUIRK_NO_PSR, 682 /** 683 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 684 * 685 * The device does not set SINK_COUNT to a non-zero value. 686 * The driver should ignore SINK_COUNT during detection. Note that 687 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 688 */ 689 DP_DPCD_QUIRK_NO_SINK_COUNT, 690 /** 691 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 692 * 693 * The device supports MST DSC despite not supporting Virtual DPCD. 694 * The DSC caps can be read from the physical aux instead. 695 */ 696 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 697 /** 698 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 699 * 700 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 701 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 702 */ 703 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 704 /** 705 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: 706 * 707 * The device applies HBLANK expansion for some modes, but this 708 * requires enabling DSC. 709 */ 710 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, 711 }; 712 713 /** 714 * drm_dp_has_quirk() - does the DP device have a specific quirk 715 * @desc: Device descriptor filled by drm_dp_read_desc() 716 * @quirk: Quirk to query for 717 * 718 * Return true if DP device identified by @desc has @quirk. 719 */ 720 static inline bool 721 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 722 { 723 return desc->quirks & BIT(quirk); 724 } 725 726 /** 727 * struct drm_edp_backlight_info - Probed eDP backlight info struct 728 * @pwmgen_bit_count: The pwmgen bit count 729 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 730 * @max: The maximum backlight level that may be set 731 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 732 * @aux_enable: Does the panel support the AUX enable cap? 733 * @aux_set: Does the panel support setting the brightness through AUX? 734 * 735 * This structure contains various data about an eDP backlight, which can be populated by using 736 * drm_edp_backlight_init(). 737 */ 738 struct drm_edp_backlight_info { 739 u8 pwmgen_bit_count; 740 u8 pwm_freq_pre_divider; 741 u16 max; 742 743 bool lsb_reg_used : 1; 744 bool aux_enable : 1; 745 bool aux_set : 1; 746 }; 747 748 int 749 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 750 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 751 u16 *current_level, u8 *current_mode); 752 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 753 u16 level); 754 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 755 u16 level); 756 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 757 758 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 759 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 760 761 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 762 763 #else 764 765 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 766 struct drm_dp_aux *aux) 767 { 768 return 0; 769 } 770 771 #endif 772 773 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC 774 void drm_dp_cec_irq(struct drm_dp_aux *aux); 775 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 776 struct drm_connector *connector); 777 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 778 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); 779 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 780 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 781 #else 782 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 783 { 784 } 785 786 static inline void 787 drm_dp_cec_register_connector(struct drm_dp_aux *aux, 788 struct drm_connector *connector) 789 { 790 } 791 792 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 793 { 794 } 795 796 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, 797 u16 source_physical_address) 798 { 799 } 800 801 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 802 const struct edid *edid) 803 { 804 } 805 806 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 807 { 808 } 809 810 #endif 811 812 /** 813 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 814 * @link_rate: Requested Link rate from DPCD 0x219 815 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 816 * @phy_pattern: DP Phy test pattern from DPCD 0x248 817 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 818 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 819 * @enhanced_frame_cap: flag for enhanced frame capability. 820 */ 821 struct drm_dp_phy_test_params { 822 int link_rate; 823 u8 num_lanes; 824 u8 phy_pattern; 825 u8 hbr2_reset[2]; 826 u8 custom80[10]; 827 bool enhanced_frame_cap; 828 }; 829 830 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 831 struct drm_dp_phy_test_params *data); 832 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 833 struct drm_dp_phy_test_params *data, u8 dp_rev); 834 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 835 const u8 port_cap[4]); 836 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 837 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 838 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 839 u8 frl_mode); 840 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 841 u8 frl_type); 842 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 843 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 844 845 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 846 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 847 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 848 struct drm_connector *connector); 849 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 850 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 851 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 852 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 853 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 854 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 855 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 856 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 857 const u8 port_cap[4], u8 color_spc); 858 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 859 860 #define DRM_DP_BW_OVERHEAD_MST BIT(0) 861 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1) 862 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) 863 #define DRM_DP_BW_OVERHEAD_FEC BIT(3) 864 #define DRM_DP_BW_OVERHEAD_DSC BIT(4) 865 866 int drm_dp_bw_overhead(int lane_count, int hactive, 867 int dsc_slice_count, 868 int bpp_x16, unsigned long flags); 869 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); 870 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); 871 872 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp); 873 874 #endif /* _DRM_DP_HELPER_H_ */ 875