1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/delay.h> 27 #include <linux/i2c.h> 28 29 #include <drm/display/drm_dp.h> 30 #include <drm/drm_connector.h> 31 32 struct drm_device; 33 struct drm_dp_aux; 34 struct drm_panel; 35 36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 41 int lane); 42 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 43 int lane); 44 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 45 int lane); 46 47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 48 enum drm_dp_phy dp_phy, bool uhbr); 49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 50 enum drm_dp_phy dp_phy, bool uhbr); 51 52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 54 void drm_dp_lttpr_link_train_clock_recovery_delay(void); 55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 59 60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 61 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 62 int lane_count); 63 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 64 int lane_count); 65 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 66 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 69 u8 drm_dp_link_rate_to_bw_code(int link_rate); 70 int drm_dp_bw_code_to_link_rate(u8 link_bw); 71 72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 73 74 /** 75 * struct drm_dp_vsc_sdp - drm DP VSC SDP 76 * 77 * This structure represents a DP VSC SDP of drm 78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 79 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 80 * 81 * @sdp_type: secondary-data packet type 82 * @revision: revision number 83 * @length: number of valid data bytes 84 * @pixelformat: pixel encoding format 85 * @colorimetry: colorimetry format 86 * @bpc: bit per color 87 * @dynamic_range: dynamic range information 88 * @content_type: CTA-861-G defines content types and expected processing by a sink device 89 */ 90 struct drm_dp_vsc_sdp { 91 unsigned char sdp_type; 92 unsigned char revision; 93 unsigned char length; 94 enum dp_pixelformat pixelformat; 95 enum dp_colorimetry colorimetry; 96 int bpc; 97 enum dp_dynamic_range dynamic_range; 98 enum dp_content_type content_type; 99 }; 100 101 /** 102 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP 103 * 104 * This structure represents a DP AS SDP of drm 105 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and 106 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] 107 * 108 * @sdp_type: Secondary-data packet type 109 * @revision: Revision Number 110 * @length: Number of valid data bytes 111 * @vtotal: Minimum Vertical Vtotal 112 * @target_rr: Target Refresh 113 * @duration_incr_ms: Successive frame duration increase 114 * @duration_decr_ms: Successive frame duration decrease 115 * @operation_mode: Adaptive Sync Operation Mode 116 */ 117 struct drm_dp_as_sdp { 118 unsigned char sdp_type; 119 unsigned char revision; 120 unsigned char length; 121 int vtotal; 122 int target_rr; 123 int duration_incr_ms; 124 int duration_decr_ms; 125 enum operation_mode mode; 126 }; 127 128 void drm_dp_as_sdp_log(struct drm_printer *p, 129 const struct drm_dp_as_sdp *as_sdp); 130 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); 131 132 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 133 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 134 135 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 136 137 static inline int 138 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 139 { 140 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 141 } 142 143 static inline u8 144 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 145 { 146 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 147 } 148 149 static inline bool 150 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 151 { 152 return dpcd[DP_DPCD_REV] >= 0x11 && 153 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 154 } 155 156 static inline bool 157 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 158 { 159 return dpcd[DP_DPCD_REV] >= 0x11 && 160 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 161 } 162 163 static inline bool 164 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 165 { 166 return dpcd[DP_DPCD_REV] >= 0x12 && 167 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 168 } 169 170 static inline bool 171 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 172 { 173 return dpcd[DP_DPCD_REV] >= 0x11 || 174 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 175 } 176 177 static inline bool 178 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 179 { 180 return dpcd[DP_DPCD_REV] >= 0x14 && 181 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 182 } 183 184 static inline u8 185 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 186 { 187 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 188 DP_TRAINING_PATTERN_MASK; 189 } 190 191 static inline bool 192 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 193 { 194 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 195 } 196 197 /* DP/eDP DSC support */ 198 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 199 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 200 bool is_edp); 201 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 202 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 203 u8 dsc_bpc[3]); 204 205 static inline bool 206 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 207 { 208 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 209 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 210 } 211 212 static inline u16 213 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 214 { 215 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 216 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 217 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 218 } 219 220 static inline u32 221 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 222 { 223 /* Max Slicewidth = Number of Pixels * 320 */ 224 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 225 DP_DSC_SLICE_WIDTH_MULTIPLIER; 226 } 227 228 /** 229 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 230 * @dsc_dpcd : DSC-capability DPCDs of the sink 231 * @output_format: output_format which is to be checked 232 * 233 * Returns true if the sink supports DSC with the given output_format, false otherwise. 234 */ 235 static inline bool 236 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 237 { 238 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 239 } 240 241 /* Forward Error Correction Support on DP 1.4 */ 242 static inline bool 243 drm_dp_sink_supports_fec(const u8 fec_capable) 244 { 245 return fec_capable & DP_FEC_CAPABLE; 246 } 247 248 static inline bool 249 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 250 { 251 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 252 } 253 254 static inline bool 255 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 256 { 257 return dpcd[DP_EDP_CONFIGURATION_CAP] & 258 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 259 } 260 261 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 262 static inline bool 263 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 264 { 265 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 266 DP_MSA_TIMING_PAR_IGNORED; 267 } 268 269 /** 270 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 271 * @edp_dpcd: The DPCD to check 272 * 273 * Note that currently this function will return %false for panels which support various DPCD 274 * backlight features but which require the brightness be set through PWM, and don't support setting 275 * the brightness level via the DPCD. 276 * 277 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 278 * otherwise 279 */ 280 static inline bool 281 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 282 { 283 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 284 } 285 286 /** 287 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR 288 * @link_rate: link rate in 10kbits/s units 289 * 290 * Determine if the provided link rate is an UHBR rate. 291 * 292 * Returns: %True if @link_rate is an UHBR rate. 293 */ 294 static inline bool drm_dp_is_uhbr_rate(int link_rate) 295 { 296 return link_rate >= 1000000; 297 } 298 299 /* 300 * DisplayPort AUX channel 301 */ 302 303 /** 304 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 305 * @address: address of the (first) register to access 306 * @request: contains the type of transaction (see DP_AUX_* macros) 307 * @reply: upon completion, contains the reply type of the transaction 308 * @buffer: pointer to a transmission or reception buffer 309 * @size: size of @buffer 310 */ 311 struct drm_dp_aux_msg { 312 unsigned int address; 313 u8 request; 314 u8 reply; 315 void *buffer; 316 size_t size; 317 }; 318 319 struct cec_adapter; 320 struct drm_connector; 321 struct drm_edid; 322 323 /** 324 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 325 * @lock: mutex protecting this struct 326 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 327 * @connector: the connector this CEC adapter is associated with 328 * @unregister_work: unregister the CEC adapter 329 */ 330 struct drm_dp_aux_cec { 331 struct mutex lock; 332 struct cec_adapter *adap; 333 struct drm_connector *connector; 334 struct delayed_work unregister_work; 335 }; 336 337 /** 338 * struct drm_dp_aux - DisplayPort AUX channel 339 * 340 * An AUX channel can also be used to transport I2C messages to a sink. A 341 * typical application of that is to access an EDID that's present in the sink 342 * device. The @transfer() function can also be used to execute such 343 * transactions. The drm_dp_aux_register() function registers an I2C adapter 344 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 345 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 346 * transfers by default; if a partial response is received, the adapter will 347 * drop down to the size given by the partial response for this transaction 348 * only. 349 */ 350 struct drm_dp_aux { 351 /** 352 * @name: user-visible name of this AUX channel and the 353 * I2C-over-AUX adapter. 354 * 355 * It's also used to specify the name of the I2C adapter. If set 356 * to %NULL, dev_name() of @dev will be used. 357 */ 358 const char *name; 359 360 /** 361 * @ddc: I2C adapter that can be used for I2C-over-AUX 362 * communication 363 */ 364 struct i2c_adapter ddc; 365 366 /** 367 * @dev: pointer to struct device that is the parent for this 368 * AUX channel. 369 */ 370 struct device *dev; 371 372 /** 373 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 374 * Beware, this may be %NULL before drm_dp_aux_register() has been 375 * called. 376 * 377 * It should be set to the &drm_device that will be using this AUX 378 * channel as early as possible. For many graphics drivers this should 379 * happen before drm_dp_aux_init(), however it's perfectly fine to set 380 * this field later so long as it's assigned before calling 381 * drm_dp_aux_register(). 382 */ 383 struct drm_device *drm_dev; 384 385 /** 386 * @crtc: backpointer to the crtc that is currently using this 387 * AUX channel 388 */ 389 struct drm_crtc *crtc; 390 391 /** 392 * @hw_mutex: internal mutex used for locking transfers. 393 * 394 * Note that if the underlying hardware is shared among multiple 395 * channels, the driver needs to do additional locking to 396 * prevent concurrent access. 397 */ 398 struct mutex hw_mutex; 399 400 /** 401 * @crc_work: worker that captures CRCs for each frame 402 */ 403 struct work_struct crc_work; 404 405 /** 406 * @crc_count: counter of captured frame CRCs 407 */ 408 u8 crc_count; 409 410 /** 411 * @transfer: transfers a message representing a single AUX 412 * transaction. 413 * 414 * This is a hardware-specific implementation of how 415 * transactions are executed that the drivers must provide. 416 * 417 * A pointer to a &drm_dp_aux_msg structure describing the 418 * transaction is passed into this function. Upon success, the 419 * implementation should return the number of payload bytes that 420 * were transferred, or a negative error-code on failure. 421 * 422 * Helpers will propagate these errors, with the exception of 423 * the %-EBUSY error, which causes a transaction to be retried. 424 * On a short, helpers will return %-EPROTO to make it simpler 425 * to check for failure. 426 * 427 * The @transfer() function must only modify the reply field of 428 * the &drm_dp_aux_msg structure. The retry logic and i2c 429 * helpers assume this is the case. 430 * 431 * Also note that this callback can be called no matter the 432 * state @dev is in and also no matter what state the panel is 433 * in. It's expected: 434 * 435 * - If the @dev providing the AUX bus is currently unpowered then 436 * it will power itself up for the transfer. 437 * 438 * - If we're on eDP (using a drm_panel) and the panel is not in a 439 * state where it can respond (it's not powered or it's in a 440 * low power state) then this function may return an error, but 441 * not crash. It's up to the caller of this code to make sure that 442 * the panel is powered on if getting an error back is not OK. If a 443 * drm_panel driver is initiating a DP AUX transfer it may power 444 * itself up however it wants. All other code should ensure that 445 * the pre_enable() bridge chain (which eventually calls the 446 * drm_panel prepare function) has powered the panel. 447 */ 448 ssize_t (*transfer)(struct drm_dp_aux *aux, 449 struct drm_dp_aux_msg *msg); 450 451 /** 452 * @wait_hpd_asserted: wait for HPD to be asserted 453 * 454 * This is mainly useful for eDP panels drivers to wait for an eDP 455 * panel to finish powering on. It is optional for DP AUX controllers 456 * to implement this function. It is required for DP AUX endpoints 457 * (panel drivers) to call this function after powering up but before 458 * doing AUX transfers unless the DP AUX endpoint driver knows that 459 * we're not using the AUX controller's HPD. One example of the panel 460 * driver not needing to call this is if HPD is hooked up to a GPIO 461 * that the panel driver can read directly. 462 * 463 * If a DP AUX controller does not implement this function then it 464 * may still support eDP panels that use the AUX controller's built-in 465 * HPD signal by implementing a long wait for HPD in the transfer() 466 * callback, though this is deprecated. 467 * 468 * This function will efficiently wait for the HPD signal to be 469 * asserted. The `wait_us` parameter that is passed in says that we 470 * know that the HPD signal is expected to be asserted within `wait_us` 471 * microseconds. This function could wait for longer than `wait_us` if 472 * the logic in the DP controller has a long debouncing time. The 473 * important thing is that if this function returns success that the 474 * DP controller is ready to send AUX transactions. 475 * 476 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 477 * expired and HPD wasn't asserted. This function should not print 478 * timeout errors to the log. 479 * 480 * The semantics of this function are designed to match the 481 * readx_poll_timeout() function. That means a `wait_us` of 0 means 482 * to wait forever. Like readx_poll_timeout(), this function may sleep. 483 * 484 * NOTE: this function specifically reports the state of the HPD pin 485 * that's associated with the DP AUX channel. This is different from 486 * the HPD concept in much of the rest of DRM which is more about 487 * physical presence of a display. For eDP, for instance, a display is 488 * assumed always present even if the HPD pin is deasserted. 489 */ 490 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 491 492 /** 493 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 494 */ 495 unsigned i2c_nack_count; 496 /** 497 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 498 */ 499 unsigned i2c_defer_count; 500 /** 501 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 502 */ 503 struct drm_dp_aux_cec cec; 504 /** 505 * @is_remote: Is this AUX CH actually using sideband messaging. 506 */ 507 bool is_remote; 508 509 /** 510 * @powered_down: If true then the remote endpoint is powered down. 511 */ 512 bool powered_down; 513 }; 514 515 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 516 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered); 517 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 518 void *buffer, size_t size); 519 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 520 void *buffer, size_t size); 521 522 /** 523 * drm_dp_dpcd_readb() - read a single byte from the DPCD 524 * @aux: DisplayPort AUX channel 525 * @offset: address of the register to read 526 * @valuep: location where the value of the register will be stored 527 * 528 * Returns the number of bytes transferred (1) on success, or a negative 529 * error code on failure. 530 */ 531 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 532 unsigned int offset, u8 *valuep) 533 { 534 return drm_dp_dpcd_read(aux, offset, valuep, 1); 535 } 536 537 /** 538 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 539 * @aux: DisplayPort AUX channel 540 * @offset: address of the register to write 541 * @value: value to write to the register 542 * 543 * Returns the number of bytes transferred (1) on success, or a negative 544 * error code on failure. 545 */ 546 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 547 unsigned int offset, u8 value) 548 { 549 return drm_dp_dpcd_write(aux, offset, &value, 1); 550 } 551 552 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 553 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 554 555 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 556 u8 status[DP_LINK_STATUS_SIZE]); 557 558 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 559 enum drm_dp_phy dp_phy, 560 u8 link_status[DP_LINK_STATUS_SIZE]); 561 562 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 563 u8 real_edid_checksum); 564 565 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 566 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 567 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 568 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 569 const u8 port_cap[4], u8 type); 570 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 571 const u8 port_cap[4], 572 const struct drm_edid *drm_edid); 573 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 574 const u8 port_cap[4]); 575 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 576 const u8 port_cap[4], 577 const struct drm_edid *drm_edid); 578 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 579 const u8 port_cap[4], 580 const struct drm_edid *drm_edid); 581 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 582 const u8 port_cap[4], 583 const struct drm_edid *drm_edid); 584 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 585 const u8 port_cap[4]); 586 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 587 const u8 port_cap[4]); 588 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 589 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 590 const u8 port_cap[4]); 591 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 592 void drm_dp_downstream_debug(struct seq_file *m, 593 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 594 const u8 port_cap[4], 595 const struct drm_edid *drm_edid, 596 struct drm_dp_aux *aux); 597 enum drm_mode_subconnector 598 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 599 const u8 port_cap[4]); 600 void drm_dp_set_subconnector_property(struct drm_connector *connector, 601 enum drm_connector_status status, 602 const u8 *dpcd, 603 const u8 port_cap[4]); 604 605 struct drm_dp_desc; 606 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 607 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 608 const struct drm_dp_desc *desc); 609 int drm_dp_read_sink_count(struct drm_dp_aux *aux); 610 611 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 612 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 613 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 614 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 615 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 616 enum drm_dp_phy dp_phy, 617 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 618 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 619 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 620 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 621 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 622 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 623 624 void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 625 void drm_dp_aux_init(struct drm_dp_aux *aux); 626 int drm_dp_aux_register(struct drm_dp_aux *aux); 627 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 628 629 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 630 int drm_dp_stop_crc(struct drm_dp_aux *aux); 631 632 struct drm_dp_dpcd_ident { 633 u8 oui[3]; 634 u8 device_id[6]; 635 u8 hw_rev; 636 u8 sw_major_rev; 637 u8 sw_minor_rev; 638 } __packed; 639 640 /** 641 * struct drm_dp_desc - DP branch/sink device descriptor 642 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 643 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 644 */ 645 struct drm_dp_desc { 646 struct drm_dp_dpcd_ident ident; 647 u32 quirks; 648 }; 649 650 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 651 bool is_branch); 652 653 /** 654 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 655 * 656 * Display Port sink and branch devices in the wild have a variety of bugs, try 657 * to collect them here. The quirks are shared, but it's up to the drivers to 658 * implement workarounds for them. 659 */ 660 enum drm_dp_quirk { 661 /** 662 * @DP_DPCD_QUIRK_CONSTANT_N: 663 * 664 * The device requires main link attributes Mvid and Nvid to be limited 665 * to 16 bits. So will give a constant value (0x8000) for compatability. 666 */ 667 DP_DPCD_QUIRK_CONSTANT_N, 668 /** 669 * @DP_DPCD_QUIRK_NO_PSR: 670 * 671 * The device does not support PSR even if reports that it supports or 672 * driver still need to implement proper handling for such device. 673 */ 674 DP_DPCD_QUIRK_NO_PSR, 675 /** 676 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 677 * 678 * The device does not set SINK_COUNT to a non-zero value. 679 * The driver should ignore SINK_COUNT during detection. Note that 680 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 681 */ 682 DP_DPCD_QUIRK_NO_SINK_COUNT, 683 /** 684 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 685 * 686 * The device supports MST DSC despite not supporting Virtual DPCD. 687 * The DSC caps can be read from the physical aux instead. 688 */ 689 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 690 /** 691 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 692 * 693 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 694 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 695 */ 696 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 697 /** 698 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: 699 * 700 * The device applies HBLANK expansion for some modes, but this 701 * requires enabling DSC. 702 */ 703 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, 704 }; 705 706 /** 707 * drm_dp_has_quirk() - does the DP device have a specific quirk 708 * @desc: Device descriptor filled by drm_dp_read_desc() 709 * @quirk: Quirk to query for 710 * 711 * Return true if DP device identified by @desc has @quirk. 712 */ 713 static inline bool 714 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 715 { 716 return desc->quirks & BIT(quirk); 717 } 718 719 /** 720 * struct drm_edp_backlight_info - Probed eDP backlight info struct 721 * @pwmgen_bit_count: The pwmgen bit count 722 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 723 * @max: The maximum backlight level that may be set 724 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 725 * @aux_enable: Does the panel support the AUX enable cap? 726 * @aux_set: Does the panel support setting the brightness through AUX? 727 * 728 * This structure contains various data about an eDP backlight, which can be populated by using 729 * drm_edp_backlight_init(). 730 */ 731 struct drm_edp_backlight_info { 732 u8 pwmgen_bit_count; 733 u8 pwm_freq_pre_divider; 734 u16 max; 735 736 bool lsb_reg_used : 1; 737 bool aux_enable : 1; 738 bool aux_set : 1; 739 }; 740 741 int 742 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 743 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 744 u16 *current_level, u8 *current_mode); 745 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 746 u16 level); 747 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 748 u16 level); 749 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 750 751 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 752 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 753 754 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 755 756 #else 757 758 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 759 struct drm_dp_aux *aux) 760 { 761 return 0; 762 } 763 764 #endif 765 766 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC 767 void drm_dp_cec_irq(struct drm_dp_aux *aux); 768 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 769 struct drm_connector *connector); 770 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 771 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); 772 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 773 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 774 #else 775 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 776 { 777 } 778 779 static inline void 780 drm_dp_cec_register_connector(struct drm_dp_aux *aux, 781 struct drm_connector *connector) 782 { 783 } 784 785 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 786 { 787 } 788 789 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, 790 u16 source_physical_address) 791 { 792 } 793 794 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 795 const struct edid *edid) 796 { 797 } 798 799 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 800 { 801 } 802 803 #endif 804 805 /** 806 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 807 * @link_rate: Requested Link rate from DPCD 0x219 808 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 809 * @phy_pattern: DP Phy test pattern from DPCD 0x248 810 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 811 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 812 * @enhanced_frame_cap: flag for enhanced frame capability. 813 */ 814 struct drm_dp_phy_test_params { 815 int link_rate; 816 u8 num_lanes; 817 u8 phy_pattern; 818 u8 hbr2_reset[2]; 819 u8 custom80[10]; 820 bool enhanced_frame_cap; 821 }; 822 823 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 824 struct drm_dp_phy_test_params *data); 825 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 826 struct drm_dp_phy_test_params *data, u8 dp_rev); 827 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 828 const u8 port_cap[4]); 829 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 830 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 831 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 832 u8 frl_mode); 833 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 834 u8 frl_type); 835 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 836 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 837 838 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 839 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 840 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 841 struct drm_connector *connector); 842 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 843 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 844 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 845 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 846 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 847 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 848 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 849 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 850 const u8 port_cap[4], u8 color_spc); 851 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 852 853 #define DRM_DP_BW_OVERHEAD_MST BIT(0) 854 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1) 855 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) 856 #define DRM_DP_BW_OVERHEAD_FEC BIT(3) 857 #define DRM_DP_BW_OVERHEAD_DSC BIT(4) 858 859 int drm_dp_bw_overhead(int lane_count, int hactive, 860 int dsc_slice_count, 861 int bpp_x16, unsigned long flags); 862 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); 863 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); 864 865 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp); 866 867 #endif /* _DRM_DP_HELPER_H_ */ 868