1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_H_ 24 #define _DRM_DP_H_ 25 26 #include <linux/types.h> 27 28 /* 29 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 30 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 31 * 1.0 devices basically don't exist in the wild. 32 * 33 * Abbreviations, in chronological order: 34 * 35 * eDP: Embedded DisplayPort version 1 36 * DPI: DisplayPort Interoperability Guideline v1.1a 37 * 1.2: DisplayPort 1.2 38 * MST: Multistream Transport - part of DP 1.2a 39 * 40 * 1.2 formally includes both eDP and DPI definitions. 41 */ 42 43 /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */ 44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0) 45 #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8) 46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9) 47 #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9) 48 #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9) 49 /* bits per component for non-RAW */ 50 #define DP_MSA_MISC_6_BPC (0 << 5) 51 #define DP_MSA_MISC_8_BPC (1 << 5) 52 #define DP_MSA_MISC_10_BPC (2 << 5) 53 #define DP_MSA_MISC_12_BPC (3 << 5) 54 #define DP_MSA_MISC_16_BPC (4 << 5) 55 /* bits per component for RAW */ 56 #define DP_MSA_MISC_RAW_6_BPC (1 << 5) 57 #define DP_MSA_MISC_RAW_7_BPC (2 << 5) 58 #define DP_MSA_MISC_RAW_8_BPC (3 << 5) 59 #define DP_MSA_MISC_RAW_10_BPC (4 << 5) 60 #define DP_MSA_MISC_RAW_12_BPC (5 << 5) 61 #define DP_MSA_MISC_RAW_14_BPC (6 << 5) 62 #define DP_MSA_MISC_RAW_16_BPC (7 << 5) 63 /* pixel encoding/colorimetry format */ 64 #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \ 65 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1)) 66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0) 67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0) 68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0) 69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1) 70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0) 71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0) 72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0) 73 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1) 74 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0) 75 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1) 76 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0) 77 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1) 78 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0) 79 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1) 80 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1) 81 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0) 82 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1) 83 #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14) 84 85 #define DP_AUX_MAX_PAYLOAD_BYTES 16 86 87 #define DP_AUX_I2C_WRITE 0x0 88 #define DP_AUX_I2C_READ 0x1 89 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 90 #define DP_AUX_I2C_MOT 0x4 91 #define DP_AUX_NATIVE_WRITE 0x8 92 #define DP_AUX_NATIVE_READ 0x9 93 94 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 95 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 96 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 97 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 98 99 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 100 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 101 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 102 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 103 104 /* DPCD Field Address Mapping */ 105 106 /* Receiver Capability */ 107 #define DP_DPCD_REV 0x000 108 # define DP_DPCD_REV_10 0x10 109 # define DP_DPCD_REV_11 0x11 110 # define DP_DPCD_REV_12 0x12 111 # define DP_DPCD_REV_13 0x13 112 # define DP_DPCD_REV_14 0x14 113 114 #define DP_MAX_LINK_RATE 0x001 115 116 #define DP_MAX_LANE_COUNT 0x002 117 # define DP_MAX_LANE_COUNT_MASK 0x1f 118 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 119 # define DP_ENHANCED_FRAME_CAP (1 << 7) 120 121 #define DP_MAX_DOWNSPREAD 0x003 122 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0) 123 # define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */ 124 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 125 # define DP_TPS4_SUPPORTED (1 << 7) 126 127 #define DP_NORP 0x004 128 129 #define DP_DOWNSTREAMPORT_PRESENT 0x005 130 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 131 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 132 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 133 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 134 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 135 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 136 # define DP_FORMAT_CONVERSION (1 << 3) 137 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 138 139 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 140 # define DP_CAP_ANSI_8B10B (1 << 0) 141 # define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */ 142 143 #define DP_DOWN_STREAM_PORT_COUNT 0x007 144 # define DP_PORT_COUNT_MASK 0x0f 145 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 146 # define DP_OUI_SUPPORT (1 << 7) 147 148 #define DP_RECEIVE_PORT_0_CAP_0 0x008 149 # define DP_LOCAL_EDID_PRESENT (1 << 1) 150 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) 151 # define DP_HBLANK_EXPANSION_CAPABLE (1 << 3) 152 153 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 154 155 #define DP_RECEIVE_PORT_1_CAP_0 0x00a 156 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b 157 158 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 159 # define DP_I2C_SPEED_1K 0x01 160 # define DP_I2C_SPEED_5K 0x02 161 # define DP_I2C_SPEED_10K 0x04 162 # define DP_I2C_SPEED_100K 0x08 163 # define DP_I2C_SPEED_400K 0x10 164 # define DP_I2C_SPEED_1M 0x20 165 166 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 167 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) 168 # define DP_FRAMING_CHANGE_CAP (1 << 1) 169 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ 170 171 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 172 # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ 173 # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ 174 175 #define DP_ADAPTER_CAP 0x00f /* 1.2 */ 176 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) 177 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) 178 179 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ 180 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ 181 182 /* Multiple stream transport */ 183 #define DP_FAUX_CAP 0x020 /* 1.2 */ 184 # define DP_FAUX_CAP_1 (1 << 0) 185 186 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */ 187 # define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0) 188 # define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1) 189 # define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2) 190 191 #define DP_MSTM_CAP 0x021 /* 1.2 */ 192 # define DP_MST_CAP (1 << 0) 193 # define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */ 194 195 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ 196 197 /* AV_SYNC_DATA_BLOCK 1.2 */ 198 #define DP_AV_GRANULARITY 0x023 199 # define DP_AG_FACTOR_MASK (0xf << 0) 200 # define DP_AG_FACTOR_3MS (0 << 0) 201 # define DP_AG_FACTOR_2MS (1 << 0) 202 # define DP_AG_FACTOR_1MS (2 << 0) 203 # define DP_AG_FACTOR_500US (3 << 0) 204 # define DP_AG_FACTOR_200US (4 << 0) 205 # define DP_AG_FACTOR_100US (5 << 0) 206 # define DP_AG_FACTOR_10US (6 << 0) 207 # define DP_AG_FACTOR_1US (7 << 0) 208 # define DP_VG_FACTOR_MASK (0xf << 4) 209 # define DP_VG_FACTOR_3MS (0 << 4) 210 # define DP_VG_FACTOR_2MS (1 << 4) 211 # define DP_VG_FACTOR_1MS (2 << 4) 212 # define DP_VG_FACTOR_500US (3 << 4) 213 # define DP_VG_FACTOR_200US (4 << 4) 214 # define DP_VG_FACTOR_100US (5 << 4) 215 216 #define DP_AUD_DEC_LAT0 0x024 217 #define DP_AUD_DEC_LAT1 0x025 218 219 #define DP_AUD_PP_LAT0 0x026 220 #define DP_AUD_PP_LAT1 0x027 221 222 #define DP_VID_INTER_LAT 0x028 223 224 #define DP_VID_PROG_LAT 0x029 225 226 #define DP_REP_LAT 0x02a 227 228 #define DP_AUD_DEL_INS0 0x02b 229 #define DP_AUD_DEL_INS1 0x02c 230 #define DP_AUD_DEL_INS2 0x02d 231 /* End of AV_SYNC_DATA_BLOCK */ 232 233 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ 234 # define DP_ALPM_CAP (1 << 0) 235 236 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ 237 # define DP_AUX_FRAME_SYNC_CAP (1 << 0) 238 239 #define DP_GUID 0x030 /* 1.2 */ 240 241 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ 242 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) 243 # define DP_DSC_PASSTHROUGH_IS_SUPPORTED (1 << 1) 244 # define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) 245 # define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) 246 247 #define DP_DSC_REV 0x061 248 # define DP_DSC_MAJOR_MASK (0xf << 0) 249 # define DP_DSC_MINOR_MASK (0xf << 4) 250 # define DP_DSC_MAJOR_SHIFT 0 251 # define DP_DSC_MINOR_SHIFT 4 252 253 #define DP_DSC_RC_BUF_BLK_SIZE 0x062 254 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 255 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 256 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 257 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 258 259 #define DP_DSC_RC_BUF_SIZE 0x063 260 261 #define DP_DSC_SLICE_CAP_1 0x064 262 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) 263 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) 264 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) 265 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) 266 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) 267 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) 268 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) 269 270 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 271 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) 272 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 273 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 274 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 275 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 276 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 277 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 278 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 279 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 280 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 281 282 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 283 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) 284 # define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) 285 286 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ 287 288 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ 289 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) 290 # define DP_DSC_MAX_BPP_DELTA_VERSION_MASK (0x3 << 5) /* eDP 1.5 & DP 2.0 */ 291 # define DP_DSC_MAX_BPP_DELTA_AVAILABILITY (1 << 7) /* eDP 1.5 & DP 2.0 */ 292 293 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 294 # define DP_DSC_RGB (1 << 0) 295 # define DP_DSC_YCbCr444 (1 << 1) 296 # define DP_DSC_YCbCr422_Simple (1 << 2) 297 # define DP_DSC_YCbCr422_Native (1 << 3) 298 # define DP_DSC_YCbCr420_Native (1 << 4) 299 300 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A 301 # define DP_DSC_8_BPC (1 << 1) 302 # define DP_DSC_10_BPC (1 << 2) 303 # define DP_DSC_12_BPC (1 << 3) 304 305 #define DP_DSC_PEAK_THROUGHPUT 0x06B 306 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) 307 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 308 # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 309 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) 310 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) 311 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) 312 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) 313 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) 314 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) 315 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) 316 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) 317 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) 318 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) 319 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) 320 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) 321 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) 322 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) 323 # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ 324 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) 325 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 326 # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0 327 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) 328 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) 329 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) 330 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) 331 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) 332 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) 333 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) 334 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) 335 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) 336 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) 337 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) 338 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) 339 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) 340 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) 341 # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4) 342 343 #define DP_DSC_MAX_SLICE_WIDTH 0x06C 344 #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560 345 #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 346 347 #define DP_DSC_SLICE_CAP_2 0x06D 348 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) 349 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) 350 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) 351 352 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F 353 # define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f 354 # define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 355 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 356 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 357 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 358 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 359 # define DP_DSC_BITS_PER_PIXEL_1_1 0x4 360 361 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 362 # define DP_PSR_IS_SUPPORTED 1 363 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ 364 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ 365 # define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */ 366 367 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 368 # define DP_PSR_NO_TRAIN_ON_EXIT 1 369 # define DP_PSR_SETUP_TIME_330 (0 << 1) 370 # define DP_PSR_SETUP_TIME_275 (1 << 1) 371 # define DP_PSR_SETUP_TIME_220 (2 << 1) 372 # define DP_PSR_SETUP_TIME_165 (3 << 1) 373 # define DP_PSR_SETUP_TIME_110 (4 << 1) 374 # define DP_PSR_SETUP_TIME_55 (5 << 1) 375 # define DP_PSR_SETUP_TIME_0 (6 << 1) 376 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 377 # define DP_PSR_SETUP_TIME_SHIFT 1 378 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ 379 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ 380 # define DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED (1 << 6)/* eDP 1.5, adopted eDP 1.4b SCR */ 381 382 #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ 383 #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ 384 385 /* 386 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 387 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 388 * each port's descriptor is one byte wide. If it was set, each port's is 389 * four bytes wide, starting with the one byte from the base info. As of 390 * DP interop v1.1a only VGA defines additional detail. 391 */ 392 393 /* offset 0 */ 394 #define DP_DOWNSTREAM_PORT_0 0x80 395 # define DP_DS_PORT_TYPE_MASK (7 << 0) 396 # define DP_DS_PORT_TYPE_DP 0 397 # define DP_DS_PORT_TYPE_VGA 1 398 # define DP_DS_PORT_TYPE_DVI 2 399 # define DP_DS_PORT_TYPE_HDMI 3 400 # define DP_DS_PORT_TYPE_NON_EDID 4 401 # define DP_DS_PORT_TYPE_DP_DUALMODE 5 402 # define DP_DS_PORT_TYPE_WIRELESS 6 403 # define DP_DS_PORT_HPD (1 << 3) 404 # define DP_DS_NON_EDID_MASK (0xf << 4) 405 # define DP_DS_NON_EDID_720x480i_60 (1 << 4) 406 # define DP_DS_NON_EDID_720x480i_50 (2 << 4) 407 # define DP_DS_NON_EDID_1920x1080i_60 (3 << 4) 408 # define DP_DS_NON_EDID_1920x1080i_50 (4 << 4) 409 # define DP_DS_NON_EDID_1280x720_60 (5 << 4) 410 # define DP_DS_NON_EDID_1280x720_50 (7 << 4) 411 /* offset 1 for VGA is maximum megapixels per second / 8 */ 412 /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */ 413 /* offset 2 for VGA/DVI/HDMI */ 414 # define DP_DS_MAX_BPC_MASK (3 << 0) 415 # define DP_DS_8BPC 0 416 # define DP_DS_10BPC 1 417 # define DP_DS_12BPC 2 418 # define DP_DS_16BPC 3 419 /* HDMI2.1 PCON FRL CONFIGURATION */ 420 # define DP_PCON_MAX_FRL_BW (7 << 2) 421 # define DP_PCON_MAX_0GBPS (0 << 2) 422 # define DP_PCON_MAX_9GBPS (1 << 2) 423 # define DP_PCON_MAX_18GBPS (2 << 2) 424 # define DP_PCON_MAX_24GBPS (3 << 2) 425 # define DP_PCON_MAX_32GBPS (4 << 2) 426 # define DP_PCON_MAX_40GBPS (5 << 2) 427 # define DP_PCON_MAX_48GBPS (6 << 2) 428 # define DP_PCON_SOURCE_CTL_MODE (1 << 5) 429 430 /* offset 3 for DVI */ 431 # define DP_DS_DVI_DUAL_LINK (1 << 1) 432 # define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2) 433 /* offset 3 for HDMI */ 434 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0) 435 # define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1) 436 # define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2) 437 # define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3) 438 # define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4) 439 440 /* 441 * VESA DP-to-HDMI PCON Specification adds caps for colorspace 442 * conversion in DFP cap DPCD 83h. Sec6.1 Table-3. 443 * Based on the available support the source can enable 444 * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2 445 * DPCD 3052h. 446 */ 447 # define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5) 448 # define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6) 449 # define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7) 450 451 #define DP_MAX_DOWNSTREAM_PORTS 0x10 452 453 /* DP Forward error Correction Registers */ 454 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */ 455 # define DP_FEC_CAPABLE (1 << 0) 456 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) 457 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) 458 # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) 459 #define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ 460 461 /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ 462 #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */ 463 #define DP_PCON_DSC_ENCODER 0x092 464 # define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0) 465 # define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1) 466 467 /* DP-HDMI2.1 PCON DSC Version */ 468 #define DP_PCON_DSC_VERSION 0x093 469 # define DP_PCON_DSC_MAJOR_MASK (0xF << 0) 470 # define DP_PCON_DSC_MINOR_MASK (0xF << 4) 471 # define DP_PCON_DSC_MAJOR_SHIFT 0 472 # define DP_PCON_DSC_MINOR_SHIFT 4 473 474 /* DP-HDMI2.1 PCON DSC RC Buffer block size */ 475 #define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094 476 # define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0) 477 # define DP_PCON_DSC_RC_BUF_BLK_1KB 0 478 # define DP_PCON_DSC_RC_BUF_BLK_4KB 1 479 # define DP_PCON_DSC_RC_BUF_BLK_16KB 2 480 # define DP_PCON_DSC_RC_BUF_BLK_64KB 3 481 482 /* DP-HDMI2.1 PCON DSC RC Buffer size */ 483 #define DP_PCON_DSC_RC_BUF_SIZE 0x095 484 485 /* DP-HDMI2.1 PCON DSC Slice capabilities-1 */ 486 #define DP_PCON_DSC_SLICE_CAP_1 0x096 487 # define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0) 488 # define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1) 489 # define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3) 490 # define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4) 491 # define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5) 492 # define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6) 493 # define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7) 494 495 #define DP_PCON_DSC_BUF_BIT_DEPTH 0x097 496 # define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0) 497 # define DP_PCON_DSC_DEPTH_9_BITS 0 498 # define DP_PCON_DSC_DEPTH_10_BITS 1 499 # define DP_PCON_DSC_DEPTH_11_BITS 2 500 # define DP_PCON_DSC_DEPTH_12_BITS 3 501 # define DP_PCON_DSC_DEPTH_13_BITS 4 502 # define DP_PCON_DSC_DEPTH_14_BITS 5 503 # define DP_PCON_DSC_DEPTH_15_BITS 6 504 # define DP_PCON_DSC_DEPTH_16_BITS 7 505 # define DP_PCON_DSC_DEPTH_8_BITS 8 506 507 #define DP_PCON_DSC_BLOCK_PREDICTION 0x098 508 # define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0) 509 510 #define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099 511 # define DP_PCON_DSC_ENC_RGB (0x1 << 0) 512 # define DP_PCON_DSC_ENC_YUV444 (0x1 << 1) 513 # define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2) 514 # define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3) 515 # define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4) 516 517 #define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A 518 # define DP_PCON_DSC_ENC_8BPC (0x1 << 1) 519 # define DP_PCON_DSC_ENC_10BPC (0x1 << 2) 520 # define DP_PCON_DSC_ENC_12BPC (0x1 << 3) 521 522 #define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B 523 524 /* DP-HDMI2.1 PCON DSC Slice capabilities-2 */ 525 #define DP_PCON_DSC_SLICE_CAP_2 0x09C 526 # define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0) 527 # define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1) 528 # define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2) 529 530 /* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */ 531 #define DP_PCON_DSC_BPP_INCR 0x09E 532 # define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0) 533 # define DP_PCON_DSC_ONE_16TH_BPP 0 534 # define DP_PCON_DSC_ONE_8TH_BPP 1 535 # define DP_PCON_DSC_ONE_4TH_BPP 2 536 # define DP_PCON_DSC_ONE_HALF_BPP 3 537 # define DP_PCON_DSC_ONE_BPP 4 538 539 /* DP Extended DSC Capabilities */ 540 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */ 541 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 542 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 543 544 /* DFP Capability Extension */ 545 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ 546 547 #define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */ 548 # define DP_PANEL_REPLAY_SUPPORT (1 << 0) 549 # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) 550 551 /* Link Configuration */ 552 #define DP_LINK_BW_SET 0x100 553 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ 554 # define DP_LINK_BW_1_62 0x06 555 # define DP_LINK_BW_2_7 0x0a 556 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 557 # define DP_LINK_BW_8_1 0x1e /* 1.4 */ 558 # define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */ 559 # define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */ 560 # define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ 561 562 #define DP_LANE_COUNT_SET 0x101 563 # define DP_LANE_COUNT_MASK 0x0f 564 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 565 566 #define DP_TRAINING_PATTERN_SET 0x102 567 # define DP_TRAINING_PATTERN_DISABLE 0 568 # define DP_TRAINING_PATTERN_1 1 569 # define DP_TRAINING_PATTERN_2 2 570 # define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */ 571 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 572 # define DP_TRAINING_PATTERN_4 7 /* 1.4 */ 573 # define DP_TRAINING_PATTERN_MASK 0x3 574 # define DP_TRAINING_PATTERN_MASK_1_4 0xf 575 576 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ 577 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) 578 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) 579 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) 580 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) 581 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) 582 583 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 584 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 585 586 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 587 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 588 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 589 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 590 591 #define DP_TRAINING_LANE0_SET 0x103 592 #define DP_TRAINING_LANE1_SET 0x104 593 #define DP_TRAINING_LANE2_SET 0x105 594 #define DP_TRAINING_LANE3_SET 0x106 595 596 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 597 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 598 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 599 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 600 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 601 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 602 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 603 604 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 605 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 606 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 607 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 608 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 609 610 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 611 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 612 613 # define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */ 614 615 #define DP_DOWNSPREAD_CTRL 0x107 616 # define DP_SPREAD_AMP_0_5 (1 << 4) 617 # define DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE (1 << 6) 618 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 619 620 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 621 # define DP_SET_ANSI_8B10B (1 << 0) 622 # define DP_SET_ANSI_128B132B (1 << 1) 623 624 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 625 /* bitmask as for DP_I2C_SPEED_CAP */ 626 627 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 628 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) 629 # define DP_FRAMING_CHANGE_ENABLE (1 << 1) 630 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) 631 632 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ 633 #define DP_LINK_QUAL_LANE1_SET 0x10c 634 #define DP_LINK_QUAL_LANE2_SET 0x10d 635 #define DP_LINK_QUAL_LANE3_SET 0x10e 636 # define DP_LINK_QUAL_PATTERN_DISABLE 0 637 # define DP_LINK_QUAL_PATTERN_D10_2 1 638 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 639 # define DP_LINK_QUAL_PATTERN_PRBS7 3 640 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 641 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5 642 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6 643 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7 644 /* DP 2.0 UHBR10, UHBR13.5, UHBR20 */ 645 # define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08 646 # define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10 647 # define DP_LINK_QUAL_PATTERN_PRSBS9 0x18 648 # define DP_LINK_QUAL_PATTERN_PRSBS11 0x20 649 # define DP_LINK_QUAL_PATTERN_PRSBS15 0x28 650 # define DP_LINK_QUAL_PATTERN_PRSBS23 0x30 651 # define DP_LINK_QUAL_PATTERN_PRSBS31 0x38 652 # define DP_LINK_QUAL_PATTERN_CUSTOM 0x40 653 # define DP_LINK_QUAL_PATTERN_SQUARE 0x48 654 # define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DISABLED 0x49 655 # define DP_LINK_QUAL_PATTERN_SQUARE_DEEMPHASIS_DISABLED 0x4a 656 # define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED 0x4b 657 658 #define DP_TRAINING_LANE0_1_SET2 0x10f 659 #define DP_TRAINING_LANE2_3_SET2 0x110 660 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) 661 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) 662 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) 663 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) 664 665 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 666 # define DP_MST_EN (1 << 0) 667 # define DP_UP_REQ_EN (1 << 1) 668 # define DP_UPSTREAM_IS_SRC (1 << 2) 669 670 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ 671 #define DP_AUDIO_DELAY1 0x113 672 #define DP_AUDIO_DELAY2 0x114 673 674 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ 675 # define DP_LINK_RATE_SET_SHIFT 0 676 # define DP_LINK_RATE_SET_MASK (7 << 0) 677 678 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ 679 # define DP_ALPM_ENABLE (1 << 0) 680 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) 681 682 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ 683 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) 684 # define DP_IRQ_HPD_ENABLE (1 << 1) 685 686 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ 687 # define DP_PWR_NOT_NEEDED (1 << 0) 688 689 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ 690 # define DP_FEC_READY (1 << 0) 691 # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) 692 # define DP_FEC_ERR_COUNT_DIS (0 << 1) 693 # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) 694 # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) 695 # define DP_FEC_BIT_ERROR_COUNT (3 << 1) 696 # define DP_FEC_LANE_SELECT_MASK (3 << 4) 697 # define DP_FEC_LANE_0_SELECT (0 << 4) 698 # define DP_FEC_LANE_1_SELECT (1 << 4) 699 # define DP_FEC_LANE_2_SELECT (2 << 4) 700 # define DP_FEC_LANE_3_SELECT (3 << 4) 701 702 #define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */ 703 #define DP_SDP_CRC16_128B132B_EN BIT(0) 704 705 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ 706 # define DP_AUX_FRAME_SYNC_VALID (1 << 0) 707 708 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ 709 # define DP_DECOMPRESSION_EN (1 << 0) 710 # define DP_DSC_PASSTHROUGH_EN (1 << 1) 711 #define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ 712 713 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 714 # define DP_PSR_ENABLE BIT(0) 715 # define DP_PSR_MAIN_LINK_ACTIVE BIT(1) 716 # define DP_PSR_CRC_VERIFICATION BIT(2) 717 # define DP_PSR_FRAME_CAPTURE BIT(3) 718 # define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */ 719 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */ 720 # define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */ 721 # define DP_PSR_ENABLE_SU_REGION_ET BIT(7) /* eDP 1.5 */ 722 723 #define DP_ADAPTER_CTRL 0x1a0 724 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 725 726 #define DP_BRANCH_DEVICE_CTRL 0x1a1 727 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 728 729 #define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */ 730 # define DP_PANEL_REPLAY_ENABLE (1 << 0) 731 # define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3) 732 # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) 733 # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) 734 # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) 735 736 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 737 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 738 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 739 740 /* Link/Sink Device Status */ 741 #define DP_SINK_COUNT 0x200 742 /* prior to 1.2 bit 7 was reserved mbz */ 743 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 744 # define DP_SINK_CP_READY (1 << 6) 745 746 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 747 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 748 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 749 # define DP_CP_IRQ (1 << 2) 750 # define DP_MCCS_IRQ (1 << 3) 751 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 752 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 753 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 754 755 #define DP_LANE0_1_STATUS 0x202 756 #define DP_LANE2_3_STATUS 0x203 757 # define DP_LANE_CR_DONE (1 << 0) 758 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 759 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 760 761 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 762 DP_LANE_CHANNEL_EQ_DONE | \ 763 DP_LANE_SYMBOL_LOCKED) 764 765 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 766 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 767 #define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */ 768 #define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */ 769 #define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */ 770 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 771 #define DP_LINK_STATUS_UPDATED (1 << 7) 772 773 #define DP_SINK_STATUS 0x205 774 # define DP_RECEIVE_PORT_0_STATUS (1 << 0) 775 # define DP_RECEIVE_PORT_1_STATUS (1 << 1) 776 # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ 777 # define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ 778 779 #define DP_ADJUST_REQUEST_LANE0_1 0x206 780 #define DP_ADJUST_REQUEST_LANE2_3 0x207 781 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 782 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 783 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 784 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 785 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 786 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 787 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 788 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 789 790 /* DP 2.0 128b/132b Link Layer */ 791 # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0) 792 # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0 793 # define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4) 794 # define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4 795 796 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c 797 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03 798 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0 799 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c 800 # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2 801 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30 802 # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4 803 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0 804 # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6 805 806 #define DP_TEST_REQUEST 0x218 807 # define DP_TEST_LINK_TRAINING (1 << 0) 808 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 809 # define DP_TEST_LINK_EDID_READ (1 << 2) 810 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 811 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 812 # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */ 813 # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */ 814 815 #define DP_TEST_LINK_RATE 0x219 816 # define DP_LINK_RATE_162 (0x6) 817 # define DP_LINK_RATE_27 (0xa) 818 819 #define DP_TEST_LANE_COUNT 0x220 820 821 #define DP_TEST_PATTERN 0x221 822 # define DP_NO_TEST_PATTERN 0x0 823 # define DP_COLOR_RAMP 0x1 824 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 825 # define DP_COLOR_SQUARE 0x3 826 827 #define DP_TEST_H_TOTAL_HI 0x222 828 #define DP_TEST_H_TOTAL_LO 0x223 829 830 #define DP_TEST_V_TOTAL_HI 0x224 831 #define DP_TEST_V_TOTAL_LO 0x225 832 833 #define DP_TEST_H_START_HI 0x226 834 #define DP_TEST_H_START_LO 0x227 835 836 #define DP_TEST_V_START_HI 0x228 837 #define DP_TEST_V_START_LO 0x229 838 839 #define DP_TEST_HSYNC_HI 0x22A 840 # define DP_TEST_HSYNC_POLARITY (1 << 7) 841 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) 842 #define DP_TEST_HSYNC_WIDTH_LO 0x22B 843 844 #define DP_TEST_VSYNC_HI 0x22C 845 # define DP_TEST_VSYNC_POLARITY (1 << 7) 846 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) 847 #define DP_TEST_VSYNC_WIDTH_LO 0x22D 848 849 #define DP_TEST_H_WIDTH_HI 0x22E 850 #define DP_TEST_H_WIDTH_LO 0x22F 851 852 #define DP_TEST_V_HEIGHT_HI 0x230 853 #define DP_TEST_V_HEIGHT_LO 0x231 854 855 #define DP_TEST_MISC0 0x232 856 # define DP_TEST_SYNC_CLOCK (1 << 0) 857 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1) 858 # define DP_TEST_COLOR_FORMAT_SHIFT 1 859 # define DP_COLOR_FORMAT_RGB (0 << 1) 860 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1) 861 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1) 862 # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3) 863 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) 864 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) 865 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) 866 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) 867 # define DP_TEST_BIT_DEPTH_MASK (7 << 5) 868 # define DP_TEST_BIT_DEPTH_SHIFT 5 869 # define DP_TEST_BIT_DEPTH_6 (0 << 5) 870 # define DP_TEST_BIT_DEPTH_8 (1 << 5) 871 # define DP_TEST_BIT_DEPTH_10 (2 << 5) 872 # define DP_TEST_BIT_DEPTH_12 (3 << 5) 873 # define DP_TEST_BIT_DEPTH_16 (4 << 5) 874 875 #define DP_TEST_MISC1 0x233 876 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0) 877 # define DP_TEST_INTERLACED (1 << 1) 878 879 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 880 881 #define DP_TEST_MISC0 0x232 882 883 #define DP_TEST_CRC_R_CR 0x240 884 #define DP_TEST_CRC_G_Y 0x242 885 #define DP_TEST_CRC_B_CB 0x244 886 887 #define DP_TEST_SINK_MISC 0x246 888 # define DP_TEST_CRC_SUPPORTED (1 << 5) 889 # define DP_TEST_COUNT_MASK 0xf 890 891 #define DP_PHY_TEST_PATTERN 0x248 892 # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7 893 # define DP_PHY_TEST_PATTERN_NONE 0x0 894 # define DP_PHY_TEST_PATTERN_D10_2 0x1 895 # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 896 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 897 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 898 # define DP_PHY_TEST_PATTERN_CP2520 0x5 899 900 #define DP_PHY_SQUARE_PATTERN 0x249 901 902 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A 903 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 904 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 905 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 906 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 907 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 908 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 909 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 910 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 911 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 912 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 913 914 #define DP_TEST_RESPONSE 0x260 915 # define DP_TEST_ACK (1 << 0) 916 # define DP_TEST_NAK (1 << 1) 917 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 918 919 #define DP_TEST_EDID_CHECKSUM 0x261 920 921 #define DP_TEST_SINK 0x270 922 # define DP_TEST_SINK_START (1 << 0) 923 #define DP_TEST_AUDIO_MODE 0x271 924 #define DP_TEST_AUDIO_PATTERN_TYPE 0x272 925 #define DP_TEST_AUDIO_PERIOD_CH1 0x273 926 #define DP_TEST_AUDIO_PERIOD_CH2 0x274 927 #define DP_TEST_AUDIO_PERIOD_CH3 0x275 928 #define DP_TEST_AUDIO_PERIOD_CH4 0x276 929 #define DP_TEST_AUDIO_PERIOD_CH5 0x277 930 #define DP_TEST_AUDIO_PERIOD_CH6 0x278 931 #define DP_TEST_AUDIO_PERIOD_CH7 0x279 932 #define DP_TEST_AUDIO_PERIOD_CH8 0x27A 933 934 #define DP_FEC_STATUS 0x280 /* 1.4 */ 935 # define DP_FEC_DECODE_EN_DETECTED (1 << 0) 936 # define DP_FEC_DECODE_DIS_DETECTED (1 << 1) 937 938 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ 939 940 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ 941 # define DP_FEC_ERROR_COUNT_MASK 0x7F 942 # define DP_FEC_ERR_COUNT_VALID (1 << 7) 943 944 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 945 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 946 # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 947 948 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 949 /* up to ID_SLOT_63 at 0x2ff */ 950 951 /* Source Device-specific */ 952 #define DP_SOURCE_OUI 0x300 953 954 /* Sink Device-specific */ 955 #define DP_SINK_OUI 0x400 956 957 /* Branch Device-specific */ 958 #define DP_BRANCH_OUI 0x500 959 #define DP_BRANCH_ID 0x503 960 #define DP_BRANCH_REVISION_START 0x509 961 #define DP_BRANCH_HW_REV 0x509 962 #define DP_BRANCH_SW_REV 0x50A 963 964 /* Link/Sink Device Power Control */ 965 #define DP_SET_POWER 0x600 966 # define DP_SET_POWER_D0 0x1 967 # define DP_SET_POWER_D3 0x2 968 # define DP_SET_POWER_MASK 0x3 969 # define DP_SET_POWER_D3_AUX_ON 0x5 970 971 /* eDP-specific */ 972 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 973 # define DP_EDP_11 0x00 974 # define DP_EDP_12 0x01 975 # define DP_EDP_13 0x02 976 # define DP_EDP_14 0x03 977 # define DP_EDP_14a 0x04 /* eDP 1.4a */ 978 # define DP_EDP_14b 0x05 /* eDP 1.4b */ 979 980 #define DP_EDP_GENERAL_CAP_1 0x701 981 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) 982 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) 983 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) 984 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) 985 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) 986 # define DP_EDP_FRC_ENABLE_CAP (1 << 5) 987 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) 988 # define DP_EDP_SET_POWER_CAP (1 << 7) 989 990 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 991 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) 992 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) 993 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) 994 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) 995 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) 996 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) 997 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) 998 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) 999 1000 #define DP_EDP_GENERAL_CAP_2 0x703 1001 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) 1002 # define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4) 1003 1004 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ 1005 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) 1006 # define DP_EDP_X_REGION_CAP_SHIFT 0 1007 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) 1008 # define DP_EDP_Y_REGION_CAP_SHIFT 4 1009 1010 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 1011 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) 1012 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) 1013 # define DP_EDP_FRC_ENABLE (1 << 2) 1014 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) 1015 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) 1016 1017 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 1018 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) 1019 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) 1020 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) 1021 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) 1022 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) 1023 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) 1024 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) 1025 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) 1026 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) 1027 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ 1028 # define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7) 1029 1030 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 1031 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 1032 1033 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 1034 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 1035 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 1036 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) 1037 1038 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 1039 1040 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 1041 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 1042 1043 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a 1044 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b 1045 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c 1046 1047 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d 1048 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e 1049 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f 1050 1051 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 1052 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 1053 #define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734 1054 1055 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ 1056 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ 1057 1058 #define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */ 1059 # define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0) 1060 # define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0 1061 # define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3) 1062 1063 /* Sideband MSG Buffers */ 1064 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 1065 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 1066 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 1067 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 1068 1069 /* DPRX Event Status Indicator */ 1070 #define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */ 1071 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */ 1072 1073 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 1074 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) 1075 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1) 1076 # define DP_CEC_IRQ (1 << 2) 1077 1078 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 1079 # define RX_CAP_CHANGED (1 << 0) 1080 # define LINK_STATUS_CHANGED (1 << 1) 1081 # define STREAM_STATUS_CHANGED (1 << 2) 1082 # define HDMI_LINK_STATUS_CHANGED (1 << 3) 1083 # define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4) 1084 # define DP_TUNNELING_IRQ (1 << 5) 1085 1086 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 1087 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 1088 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 1089 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 1090 1091 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 1092 # define DP_PSR_CAPS_CHANGE (1 << 0) 1093 1094 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 1095 # define DP_PSR_SINK_INACTIVE 0 1096 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 1097 # define DP_PSR_SINK_ACTIVE_RFB 2 1098 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 1099 # define DP_PSR_SINK_ACTIVE_RESYNC 4 1100 # define DP_PSR_SINK_INTERNAL_ERROR 7 1101 # define DP_PSR_SINK_STATE_MASK 0x07 1102 1103 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ 1104 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) 1105 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 1106 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) 1107 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 1108 1109 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ 1110 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ 1111 # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ 1112 # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ 1113 # define DP_SU_VALID (1 << 3) /* eDP 1.4 */ 1114 # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ 1115 # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ 1116 # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ 1117 1118 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ 1119 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) 1120 1121 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ 1122 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ 1123 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ 1124 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ 1125 1126 #define DP_PANEL_REPLAY_ERROR_STATUS 0x2020 /* DP 2.1*/ 1127 # define DP_PANEL_REPLAY_LINK_CRC_ERROR (1 << 0) 1128 # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1) 1129 # define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) 1130 1131 #define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS 0x2022 /* DP 2.1 */ 1132 # define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0) 1133 # define DP_SINK_FRAME_LOCKED_SHIFT 3 1134 # define DP_SINK_FRAME_LOCKED_MASK (3 << 3) 1135 # define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 5 1136 # define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK (1 << 5) 1137 1138 /* Extended Receiver Capability: See DP_DPCD_REV for definitions */ 1139 #define DP_DP13_DPCD_REV 0x2200 1140 1141 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ 1142 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */ 1143 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ 1144 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ 1145 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ 1146 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ 1147 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ 1148 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ 1149 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ 1150 1151 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ 1152 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0) 1153 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1) 1154 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4) 1155 1156 #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ 1157 # define DP_UHBR10 (1 << 0) 1158 # define DP_UHBR20 (1 << 1) 1159 # define DP_UHBR13_5 (1 << 2) 1160 1161 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ 1162 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7) 1163 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f 1164 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00 1165 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01 1166 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02 1167 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03 1168 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04 1169 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05 1170 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06 1171 1172 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 1173 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 1174 1175 /* DSC Extended Capability Branch Total DSC Resources */ 1176 #define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ 1177 # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) 1178 # define DP_DSC_DECODER_COUNT_SHIFT 5 1179 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ 1180 # define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) 1181 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) 1182 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 1183 1184 /* Protocol Converter Extension */ 1185 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ 1186 #define DP_CEC_TUNNELING_CAPABILITY 0x3000 1187 # define DP_CEC_TUNNELING_CAPABLE (1 << 0) 1188 # define DP_CEC_SNOOPING_CAPABLE (1 << 1) 1189 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) 1190 1191 #define DP_CEC_TUNNELING_CONTROL 0x3001 1192 # define DP_CEC_TUNNELING_ENABLE (1 << 0) 1193 # define DP_CEC_SNOOPING_ENABLE (1 << 1) 1194 1195 #define DP_CEC_RX_MESSAGE_INFO 0x3002 1196 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) 1197 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 1198 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) 1199 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) 1200 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6) 1201 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7) 1202 1203 #define DP_CEC_TX_MESSAGE_INFO 0x3003 1204 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) 1205 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 1206 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) 1207 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4 1208 # define DP_CEC_TX_MESSAGE_SEND (1 << 7) 1209 1210 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 1211 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) 1212 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) 1213 # define DP_CEC_TX_MESSAGE_SENT (1 << 4) 1214 # define DP_CEC_TX_LINE_ERROR (1 << 5) 1215 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) 1216 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) 1217 1218 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ 1219 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) 1220 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) 1221 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) 1222 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) 1223 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) 1224 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) 1225 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) 1226 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) 1227 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ 1228 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) 1229 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) 1230 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) 1231 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) 1232 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) 1233 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) 1234 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) 1235 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) 1236 1237 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010 1238 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 1239 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 1240 1241 /* PCON CONFIGURE-1 FRL FOR HDMI SINK */ 1242 #define DP_PCON_HDMI_LINK_CONFIG_1 0x305A 1243 # define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0) 1244 # define DP_PCON_ENABLE_MAX_BW_0GBPS 0 1245 # define DP_PCON_ENABLE_MAX_BW_9GBPS 1 1246 # define DP_PCON_ENABLE_MAX_BW_18GBPS 2 1247 # define DP_PCON_ENABLE_MAX_BW_24GBPS 3 1248 # define DP_PCON_ENABLE_MAX_BW_32GBPS 4 1249 # define DP_PCON_ENABLE_MAX_BW_40GBPS 5 1250 # define DP_PCON_ENABLE_MAX_BW_48GBPS 6 1251 # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) 1252 # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) 1253 # define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) 1254 # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) 1255 # define DP_PCON_ENABLE_HPD_READY (1 << 6) 1256 # define DP_PCON_ENABLE_HDMI_LINK (1 << 7) 1257 1258 /* PCON CONFIGURE-2 FRL FOR HDMI SINK */ 1259 #define DP_PCON_HDMI_LINK_CONFIG_2 0x305B 1260 # define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0) 1261 # define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0) 1262 # define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1) 1263 # define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2) 1264 # define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3) 1265 # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) 1266 # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) 1267 # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) 1268 # define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) 1269 1270 /* PCON HDMI LINK STATUS */ 1271 #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B 1272 # define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0) 1273 # define DP_PCON_FRL_READY (1 << 1) 1274 1275 /* PCON HDMI POST FRL STATUS */ 1276 #define DP_PCON_HDMI_POST_FRL_STATUS 0x3036 1277 # define DP_PCON_HDMI_LINK_MODE (1 << 0) 1278 # define DP_PCON_HDMI_MODE_TMDS 0 1279 # define DP_PCON_HDMI_MODE_FRL 1 1280 # define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1) 1281 # define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1) 1282 # define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2) 1283 # define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3) 1284 # define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4) 1285 # define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) 1286 # define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) 1287 1288 #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */ 1289 # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */ 1290 #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */ 1291 # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */ 1292 # define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */ 1293 # define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */ 1294 # define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */ 1295 #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */ 1296 # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */ 1297 # define DP_PCON_ENABLE_DSC_ENCODER (1 << 1) 1298 # define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2) 1299 # define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0 1300 # define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1 1301 # define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2 1302 # define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4) 1303 # define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4) 1304 # define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5) 1305 # define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6) 1306 1307 /* PCON Downstream HDMI ERROR Status per Lane */ 1308 #define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037 1309 #define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038 1310 #define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039 1311 #define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A 1312 # define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0) 1313 # define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0) 1314 # define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1) 1315 # define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2) 1316 1317 /* PCON HDMI CONFIG PPS Override Buffer 1318 * Valid Offsets to be added to Base : 0-127 1319 */ 1320 #define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100 1321 1322 /* PCON HDMI CONFIG PPS Override Parameter: Slice height 1323 * Offset-0 8LSBs of the Slice height. 1324 * Offset-1 8MSBs of the Slice height. 1325 */ 1326 #define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180 1327 1328 /* PCON HDMI CONFIG PPS Override Parameter: Slice width 1329 * Offset-0 8LSBs of the Slice width. 1330 * Offset-1 8MSBs of the Slice width. 1331 */ 1332 #define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182 1333 1334 /* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel 1335 * Offset-0 8LSBs of the bits_per_pixel. 1336 * Offset-1 2MSBs of the bits_per_pixel. 1337 */ 1338 #define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184 1339 1340 /* HDCP 1.3 and HDCP 2.2 */ 1341 #define DP_AUX_HDCP_BKSV 0x68000 1342 #define DP_AUX_HDCP_RI_PRIME 0x68005 1343 #define DP_AUX_HDCP_AKSV 0x68007 1344 #define DP_AUX_HDCP_AN 0x6800C 1345 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) 1346 #define DP_AUX_HDCP_BCAPS 0x68028 1347 # define DP_BCAPS_REPEATER_PRESENT BIT(1) 1348 # define DP_BCAPS_HDCP_CAPABLE BIT(0) 1349 #define DP_AUX_HDCP_BSTATUS 0x68029 1350 # define DP_BSTATUS_REAUTH_REQ BIT(3) 1351 # define DP_BSTATUS_LINK_FAILURE BIT(2) 1352 # define DP_BSTATUS_R0_PRIME_READY BIT(1) 1353 # define DP_BSTATUS_READY BIT(0) 1354 #define DP_AUX_HDCP_BINFO 0x6802A 1355 #define DP_AUX_HDCP_KSV_FIFO 0x6802C 1356 #define DP_AUX_HDCP_AINFO 0x6803B 1357 1358 /* DP HDCP2.2 parameter offsets in DPCD address space */ 1359 #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 1360 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 1361 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B 1362 #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 1363 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D 1364 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 1365 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 1366 #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 1367 #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 1368 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 1369 #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 1370 #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 1371 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 1372 #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 1373 #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 1374 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 1375 #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 1376 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 1377 #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 1378 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 1379 #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 1380 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 1381 #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 1382 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 1383 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 1384 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 1385 1386 /* DP-tunneling */ 1387 #define DP_TUNNELING_OUI 0xe0000 1388 #define DP_TUNNELING_OUI_BYTES 3 1389 1390 #define DP_TUNNELING_DEV_ID 0xe0003 1391 #define DP_TUNNELING_DEV_ID_BYTES 6 1392 1393 #define DP_TUNNELING_HW_REV 0xe0009 1394 #define DP_TUNNELING_HW_REV_MAJOR_SHIFT 4 1395 #define DP_TUNNELING_HW_REV_MAJOR_MASK (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT) 1396 #define DP_TUNNELING_HW_REV_MINOR_SHIFT 0 1397 #define DP_TUNNELING_HW_REV_MINOR_MASK (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT) 1398 1399 #define DP_TUNNELING_SW_REV_MAJOR 0xe000a 1400 #define DP_TUNNELING_SW_REV_MINOR 0xe000b 1401 1402 #define DP_TUNNELING_CAPABILITIES 0xe000d 1403 #define DP_IN_BW_ALLOCATION_MODE_SUPPORT (1 << 7) 1404 #define DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT (1 << 6) 1405 #define DP_TUNNELING_SUPPORT (1 << 0) 1406 1407 #define DP_IN_ADAPTER_INFO 0xe000e 1408 #define DP_IN_ADAPTER_NUMBER_BITS 7 1409 #define DP_IN_ADAPTER_NUMBER_MASK ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1) 1410 1411 #define DP_USB4_DRIVER_ID 0xe000f 1412 #define DP_USB4_DRIVER_ID_BITS 4 1413 #define DP_USB4_DRIVER_ID_MASK ((1 << DP_USB4_DRIVER_ID_BITS) - 1) 1414 1415 #define DP_USB4_DRIVER_BW_CAPABILITY 0xe0020 1416 #define DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT (1 << 7) 1417 1418 #define DP_IN_ADAPTER_TUNNEL_INFORMATION 0xe0021 1419 #define DP_GROUP_ID_BITS 3 1420 #define DP_GROUP_ID_MASK ((1 << DP_GROUP_ID_BITS) - 1) 1421 1422 #define DP_BW_GRANULARITY 0xe0022 1423 #define DP_BW_GRANULARITY_MASK 0x3 1424 1425 #define DP_ESTIMATED_BW 0xe0023 1426 #define DP_ALLOCATED_BW 0xe0024 1427 1428 #define DP_TUNNELING_STATUS 0xe0025 1429 #define DP_BW_ALLOCATION_CAPABILITY_CHANGED (1 << 3) 1430 #define DP_ESTIMATED_BW_CHANGED (1 << 2) 1431 #define DP_BW_REQUEST_SUCCEEDED (1 << 1) 1432 #define DP_BW_REQUEST_FAILED (1 << 0) 1433 1434 #define DP_TUNNELING_MAX_LINK_RATE 0xe0028 1435 1436 #define DP_TUNNELING_MAX_LANE_COUNT 0xe0029 1437 #define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f 1438 1439 #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe0030 1440 #define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE (1 << 7) 1441 #define DP_UNMASK_BW_ALLOCATION_IRQ (1 << 6) 1442 1443 #define DP_REQUEST_BW 0xe0031 1444 #define MAX_DP_REQUEST_BW 255 1445 1446 /* LTTPR: Link Training (LT)-tunable PHY Repeaters */ 1447 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ 1448 #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ 1449 #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ 1450 #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ 1451 #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ 1452 #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ 1453 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ 1454 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ 1455 # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) 1456 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */ 1457 #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ 1458 #define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */ 1459 1460 enum drm_dp_phy { 1461 DP_PHY_DPRX, 1462 1463 DP_PHY_LTTPR1, 1464 DP_PHY_LTTPR2, 1465 DP_PHY_LTTPR3, 1466 DP_PHY_LTTPR4, 1467 DP_PHY_LTTPR5, 1468 DP_PHY_LTTPR6, 1469 DP_PHY_LTTPR7, 1470 DP_PHY_LTTPR8, 1471 1472 DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8, 1473 }; 1474 1475 #define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i)) 1476 1477 #define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */ 1478 #define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */ 1479 #define DP_LTTPR_BASE(dp_phy) \ 1480 (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \ 1481 ((dp_phy) - DP_PHY_LTTPR1)) 1482 1483 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ 1484 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg)) 1485 1486 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ 1487 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ 1488 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1) 1489 1490 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ 1491 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ 1492 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1) 1493 1494 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ 1495 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ 1496 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ 1497 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ 1498 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ 1499 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) 1500 1501 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ 1502 # define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0) 1503 # define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1) 1504 1505 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */ 1506 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ 1507 DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) 1508 /* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */ 1509 1510 #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ 1511 #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ 1512 DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1) 1513 1514 #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ 1515 1516 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ 1517 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ 1518 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ 1519 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ 1520 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ 1521 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ 1522 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ 1523 1524 #define __DP_FEC1_BASE 0xf0290 /* 1.4 */ 1525 #define __DP_FEC2_BASE 0xf0298 /* 1.4 */ 1526 #define DP_FEC_BASE(dp_phy) \ 1527 (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \ 1528 ((dp_phy) - DP_PHY_LTTPR1))) 1529 1530 #define DP_FEC_REG(dp_phy, fec1_reg) \ 1531 (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg) 1532 1533 #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ 1534 #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ 1535 DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1) 1536 1537 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */ 1538 #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */ 1539 1540 #define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */ 1541 1542 #define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */ 1543 1544 /* Repeater modes */ 1545 #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ 1546 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ 1547 1548 /* DP HDCP message start offsets in DPCD address space */ 1549 #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET 1550 #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET 1551 #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 1552 #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 1553 #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET 1554 #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ 1555 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 1556 #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET 1557 #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET 1558 #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 1559 #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET 1560 #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET 1561 #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 1562 #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET 1563 1564 #define HDCP_2_2_DP_RXSTATUS_LEN 1 1565 #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) 1566 #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) 1567 #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) 1568 #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) 1569 #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) 1570 1571 /* DP 1.2 Sideband message defines */ 1572 /* peer device type - DP 1.2a Table 2-92 */ 1573 #define DP_PEER_DEVICE_NONE 0x0 1574 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 1575 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 1576 #define DP_PEER_DEVICE_SST_SINK 0x3 1577 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 1578 1579 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 1580 #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */ 1581 #define DP_LINK_ADDRESS 0x01 1582 #define DP_CONNECTION_STATUS_NOTIFY 0x02 1583 #define DP_ENUM_PATH_RESOURCES 0x10 1584 #define DP_ALLOCATE_PAYLOAD 0x11 1585 #define DP_QUERY_PAYLOAD 0x12 1586 #define DP_RESOURCE_STATUS_NOTIFY 0x13 1587 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 1588 #define DP_REMOTE_DPCD_READ 0x20 1589 #define DP_REMOTE_DPCD_WRITE 0x21 1590 #define DP_REMOTE_I2C_READ 0x22 1591 #define DP_REMOTE_I2C_WRITE 0x23 1592 #define DP_POWER_UP_PHY 0x24 1593 #define DP_POWER_DOWN_PHY 0x25 1594 #define DP_SINK_EVENT_NOTIFY 0x30 1595 #define DP_QUERY_STREAM_ENC_STATUS 0x38 1596 #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 1597 #define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 1598 #define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2 1599 1600 /* DP 1.2 MST sideband reply types */ 1601 #define DP_SIDEBAND_REPLY_ACK 0x00 1602 #define DP_SIDEBAND_REPLY_NAK 0x01 1603 1604 /* DP 1.2 MST sideband nak reasons - table 2.84 */ 1605 #define DP_NAK_WRITE_FAILURE 0x01 1606 #define DP_NAK_INVALID_READ 0x02 1607 #define DP_NAK_CRC_FAILURE 0x03 1608 #define DP_NAK_BAD_PARAM 0x04 1609 #define DP_NAK_DEFER 0x05 1610 #define DP_NAK_LINK_FAILURE 0x06 1611 #define DP_NAK_NO_RESOURCES 0x07 1612 #define DP_NAK_DPCD_FAIL 0x08 1613 #define DP_NAK_I2C_NAK 0x09 1614 #define DP_NAK_ALLOCATE_FAIL 0x0a 1615 1616 #define MODE_I2C_START 1 1617 #define MODE_I2C_WRITE 2 1618 #define MODE_I2C_READ 4 1619 #define MODE_I2C_STOP 8 1620 1621 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ 1622 #define DP_MST_PHYSICAL_PORT_0 0 1623 #define DP_MST_LOGICAL_PORT_0 8 1624 1625 #define DP_LINK_CONSTANT_N_VALUE 0x8000 1626 #define DP_LINK_STATUS_SIZE 6 1627 1628 #define DP_BRANCH_OUI_HEADER_SIZE 0xc 1629 #define DP_RECEIVER_CAP_SIZE 0xf 1630 #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */ 1631 #define EDP_PSR_RECEIVER_CAP_SIZE 2 1632 #define EDP_DISPLAY_CTL_CAP_SIZE 3 1633 #define DP_LTTPR_COMMON_CAP_SIZE 8 1634 #define DP_LTTPR_PHY_CAP_SIZE 3 1635 1636 #define DP_SDP_AUDIO_TIMESTAMP 0x01 1637 #define DP_SDP_AUDIO_STREAM 0x02 1638 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ 1639 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ 1640 #define DP_SDP_ISRC 0x06 /* DP 1.2 */ 1641 #define DP_SDP_VSC 0x07 /* DP 1.2 */ 1642 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ 1643 #define DP_SDP_PPS 0x10 /* DP 1.4 */ 1644 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ 1645 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ 1646 /* 0x80+ CEA-861 infoframe types */ 1647 1648 #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b 1649 1650 /** 1651 * struct dp_sdp_header - DP secondary data packet header 1652 * @HB0: Secondary Data Packet ID 1653 * @HB1: Secondary Data Packet Type 1654 * @HB2: Secondary Data Packet Specific header, Byte 0 1655 * @HB3: Secondary Data packet Specific header, Byte 1 1656 */ 1657 struct dp_sdp_header { 1658 u8 HB0; 1659 u8 HB1; 1660 u8 HB2; 1661 u8 HB3; 1662 } __packed; 1663 1664 #define EDP_SDP_HEADER_REVISION_MASK 0x1F 1665 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F 1666 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F 1667 1668 /** 1669 * struct dp_sdp - DP secondary data packet 1670 * @sdp_header: DP secondary data packet header 1671 * @db: DP secondaray data packet data blocks 1672 * VSC SDP Payload for PSR 1673 * db[0]: Stereo Interface 1674 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid 1675 * db[2]: CRC value bits 7:0 of the R or Cr component 1676 * db[3]: CRC value bits 15:8 of the R or Cr component 1677 * db[4]: CRC value bits 7:0 of the G or Y component 1678 * db[5]: CRC value bits 15:8 of the G or Y component 1679 * db[6]: CRC value bits 7:0 of the B or Cb component 1680 * db[7]: CRC value bits 15:8 of the B or Cb component 1681 * db[8] - db[31]: Reserved 1682 * VSC SDP Payload for Pixel Encoding/Colorimetry Format 1683 * db[0] - db[15]: Reserved 1684 * db[16]: Pixel Encoding and Colorimetry Formats 1685 * db[17]: Dynamic Range and Component Bit Depth 1686 * db[18]: Content Type 1687 * db[19] - db[31]: Reserved 1688 */ 1689 struct dp_sdp { 1690 struct dp_sdp_header sdp_header; 1691 u8 db[32]; 1692 } __packed; 1693 1694 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) 1695 #define EDP_VSC_PSR_UPDATE_RFB (1<<1) 1696 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) 1697 1698 /** 1699 * enum dp_pixelformat - drm DP Pixel encoding formats 1700 * 1701 * This enum is used to indicate DP VSC SDP Pixel encoding formats. 1702 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through 1703 * DB18] 1704 * 1705 * @DP_PIXELFORMAT_RGB: RGB pixel encoding format 1706 * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format 1707 * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format 1708 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format 1709 * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format 1710 * @DP_PIXELFORMAT_RAW: RAW pixel encoding format 1711 * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format 1712 */ 1713 enum dp_pixelformat { 1714 DP_PIXELFORMAT_RGB = 0, 1715 DP_PIXELFORMAT_YUV444 = 0x1, 1716 DP_PIXELFORMAT_YUV422 = 0x2, 1717 DP_PIXELFORMAT_YUV420 = 0x3, 1718 DP_PIXELFORMAT_Y_ONLY = 0x4, 1719 DP_PIXELFORMAT_RAW = 0x5, 1720 DP_PIXELFORMAT_RESERVED = 0x6, 1721 }; 1722 1723 /** 1724 * enum dp_colorimetry - drm DP Colorimetry formats 1725 * 1726 * This enum is used to indicate DP VSC SDP Colorimetry formats. 1727 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through 1728 * DB18] and a name of enum member follows enum drm_colorimetry definition. 1729 * 1730 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or 1731 * ITU-R BT.601 colorimetry format 1732 * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format 1733 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format 1734 * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point 1735 * (scRGB (IEC 61966-2-2)) colorimetry format 1736 * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format 1737 * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format 1738 * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format 1739 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format 1740 * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format 1741 * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format 1742 * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format 1743 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format 1744 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format 1745 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format 1746 */ 1747 enum dp_colorimetry { 1748 DP_COLORIMETRY_DEFAULT = 0, 1749 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1, 1750 DP_COLORIMETRY_BT709_YCC = 0x1, 1751 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2, 1752 DP_COLORIMETRY_XVYCC_601 = 0x2, 1753 DP_COLORIMETRY_OPRGB = 0x3, 1754 DP_COLORIMETRY_XVYCC_709 = 0x3, 1755 DP_COLORIMETRY_DCI_P3_RGB = 0x4, 1756 DP_COLORIMETRY_SYCC_601 = 0x4, 1757 DP_COLORIMETRY_RGB_CUSTOM = 0x5, 1758 DP_COLORIMETRY_OPYCC_601 = 0x5, 1759 DP_COLORIMETRY_BT2020_RGB = 0x6, 1760 DP_COLORIMETRY_BT2020_CYCC = 0x6, 1761 DP_COLORIMETRY_BT2020_YCC = 0x7, 1762 }; 1763 1764 /** 1765 * enum dp_dynamic_range - drm DP Dynamic Range 1766 * 1767 * This enum is used to indicate DP VSC SDP Dynamic Range. 1768 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through 1769 * DB18] 1770 * 1771 * @DP_DYNAMIC_RANGE_VESA: VESA range 1772 * @DP_DYNAMIC_RANGE_CTA: CTA range 1773 */ 1774 enum dp_dynamic_range { 1775 DP_DYNAMIC_RANGE_VESA = 0, 1776 DP_DYNAMIC_RANGE_CTA = 1, 1777 }; 1778 1779 /** 1780 * enum dp_content_type - drm DP Content Type 1781 * 1782 * This enum is used to indicate DP VSC SDP Content Types. 1783 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through 1784 * DB18] 1785 * CTA-861-G defines content types and expected processing by a sink device 1786 * 1787 * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type 1788 * @DP_CONTENT_TYPE_GRAPHICS: Graphics type 1789 * @DP_CONTENT_TYPE_PHOTO: Photo type 1790 * @DP_CONTENT_TYPE_VIDEO: Video type 1791 * @DP_CONTENT_TYPE_GAME: Game type 1792 */ 1793 enum dp_content_type { 1794 DP_CONTENT_TYPE_NOT_DEFINED = 0x00, 1795 DP_CONTENT_TYPE_GRAPHICS = 0x01, 1796 DP_CONTENT_TYPE_PHOTO = 0x02, 1797 DP_CONTENT_TYPE_VIDEO = 0x03, 1798 DP_CONTENT_TYPE_GAME = 0x04, 1799 }; 1800 1801 #endif /* _DRM_DP_H_ */ 1802