1*2c599da8SAlejandro Lucero /* SPDX-License-Identifier: GPL-2.0-only */ 2*2c599da8SAlejandro Lucero /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 3*2c599da8SAlejandro Lucero 4*2c599da8SAlejandro Lucero #ifndef __CXL_CXL_PCI_H__ 5*2c599da8SAlejandro Lucero #define __CXL_CXL_PCI_H__ 6*2c599da8SAlejandro Lucero 7*2c599da8SAlejandro Lucero /* Register Block Identifier (RBI) */ 8*2c599da8SAlejandro Lucero enum cxl_regloc_type { 9*2c599da8SAlejandro Lucero CXL_REGLOC_RBI_EMPTY = 0, 10*2c599da8SAlejandro Lucero CXL_REGLOC_RBI_COMPONENT, 11*2c599da8SAlejandro Lucero CXL_REGLOC_RBI_VIRT, 12*2c599da8SAlejandro Lucero CXL_REGLOC_RBI_MEMDEV, 13*2c599da8SAlejandro Lucero CXL_REGLOC_RBI_PMU, 14*2c599da8SAlejandro Lucero CXL_REGLOC_RBI_TYPES 15*2c599da8SAlejandro Lucero }; 16*2c599da8SAlejandro Lucero 17*2c599da8SAlejandro Lucero struct cxl_register_map; 18*2c599da8SAlejandro Lucero struct pci_dev; 19*2c599da8SAlejandro Lucero 20*2c599da8SAlejandro Lucero int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, 21*2c599da8SAlejandro Lucero struct cxl_register_map *map); 22*2c599da8SAlejandro Lucero #endif 23