1 /* Generic I/O port emulation. 2 * 3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public Licence 8 * as published by the Free Software Foundation; either version 9 * 2 of the Licence, or (at your option) any later version. 10 */ 11 #ifndef __ASM_GENERIC_IO_H 12 #define __ASM_GENERIC_IO_H 13 14 #include <asm/page.h> /* I/O is all done through memory accesses */ 15 #include <linux/string.h> /* for memset() and memcpy() */ 16 #include <linux/types.h> 17 18 #ifdef CONFIG_GENERIC_IOMAP 19 #include <asm-generic/iomap.h> 20 #endif 21 22 #include <asm-generic/pci_iomap.h> 23 24 #ifndef mmiowb 25 #define mmiowb() do {} while (0) 26 #endif 27 28 /* 29 * __raw_{read,write}{b,w,l,q}() access memory in native endianness. 30 * 31 * On some architectures memory mapped IO needs to be accessed differently. 32 * On the simple architectures, we just read/write the memory location 33 * directly. 34 */ 35 36 #ifndef __raw_readb 37 #define __raw_readb __raw_readb 38 static inline u8 __raw_readb(const volatile void __iomem *addr) 39 { 40 return *(const volatile u8 __force *)addr; 41 } 42 #endif 43 44 #ifndef __raw_readw 45 #define __raw_readw __raw_readw 46 static inline u16 __raw_readw(const volatile void __iomem *addr) 47 { 48 return *(const volatile u16 __force *)addr; 49 } 50 #endif 51 52 #ifndef __raw_readl 53 #define __raw_readl __raw_readl 54 static inline u32 __raw_readl(const volatile void __iomem *addr) 55 { 56 return *(const volatile u32 __force *)addr; 57 } 58 #endif 59 60 #ifdef CONFIG_64BIT 61 #ifndef __raw_readq 62 #define __raw_readq __raw_readq 63 static inline u64 __raw_readq(const volatile void __iomem *addr) 64 { 65 return *(const volatile u64 __force *)addr; 66 } 67 #endif 68 #endif /* CONFIG_64BIT */ 69 70 #ifndef __raw_writeb 71 #define __raw_writeb __raw_writeb 72 static inline void __raw_writeb(u8 value, volatile void __iomem *addr) 73 { 74 *(volatile u8 __force *)addr = value; 75 } 76 #endif 77 78 #ifndef __raw_writew 79 #define __raw_writew __raw_writew 80 static inline void __raw_writew(u16 value, volatile void __iomem *addr) 81 { 82 *(volatile u16 __force *)addr = value; 83 } 84 #endif 85 86 #ifndef __raw_writel 87 #define __raw_writel __raw_writel 88 static inline void __raw_writel(u32 value, volatile void __iomem *addr) 89 { 90 *(volatile u32 __force *)addr = value; 91 } 92 #endif 93 94 #ifdef CONFIG_64BIT 95 #ifndef __raw_writeq 96 #define __raw_writeq __raw_writeq 97 static inline void __raw_writeq(u64 value, volatile void __iomem *addr) 98 { 99 *(volatile u64 __force *)addr = value; 100 } 101 #endif 102 #endif /* CONFIG_64BIT */ 103 104 /* 105 * {read,write}{b,w,l,q}() access little endian memory and return result in 106 * native endianness. 107 */ 108 109 #ifndef readb 110 #define readb readb 111 static inline u8 readb(const volatile void __iomem *addr) 112 { 113 return __raw_readb(addr); 114 } 115 #endif 116 117 #ifndef readw 118 #define readw readw 119 static inline u16 readw(const volatile void __iomem *addr) 120 { 121 return __le16_to_cpu(__raw_readw(addr)); 122 } 123 #endif 124 125 #ifndef readl 126 #define readl readl 127 static inline u32 readl(const volatile void __iomem *addr) 128 { 129 return __le32_to_cpu(__raw_readl(addr)); 130 } 131 #endif 132 133 #ifdef CONFIG_64BIT 134 #ifndef readq 135 #define readq readq 136 static inline u64 readq(const volatile void __iomem *addr) 137 { 138 return __le64_to_cpu(__raw_readq(addr)); 139 } 140 #endif 141 #endif /* CONFIG_64BIT */ 142 143 #ifndef writeb 144 #define writeb writeb 145 static inline void writeb(u8 value, volatile void __iomem *addr) 146 { 147 __raw_writeb(value, addr); 148 } 149 #endif 150 151 #ifndef writew 152 #define writew writew 153 static inline void writew(u16 value, volatile void __iomem *addr) 154 { 155 __raw_writew(cpu_to_le16(value), addr); 156 } 157 #endif 158 159 #ifndef writel 160 #define writel writel 161 static inline void writel(u32 value, volatile void __iomem *addr) 162 { 163 __raw_writel(__cpu_to_le32(value), addr); 164 } 165 #endif 166 167 #ifdef CONFIG_64BIT 168 #ifndef writeq 169 #define writeq writeq 170 static inline void writeq(u64 value, volatile void __iomem *addr) 171 { 172 __raw_writeq(__cpu_to_le64(value), addr); 173 } 174 #endif 175 #endif /* CONFIG_64BIT */ 176 177 /* 178 * {read,write}{b,w,l,q}_relaxed() are like the regular version, but 179 * are not guaranteed to provide ordering against spinlocks or memory 180 * accesses. 181 */ 182 #ifndef readb_relaxed 183 #define readb_relaxed readb 184 #endif 185 186 #ifndef readw_relaxed 187 #define readw_relaxed readw 188 #endif 189 190 #ifndef readl_relaxed 191 #define readl_relaxed readl 192 #endif 193 194 #if defined(readq) && !defined(readq_relaxed) 195 #define readq_relaxed readq 196 #endif 197 198 #ifndef writeb_relaxed 199 #define writeb_relaxed writeb 200 #endif 201 202 #ifndef writew_relaxed 203 #define writew_relaxed writew 204 #endif 205 206 #ifndef writel_relaxed 207 #define writel_relaxed writel 208 #endif 209 210 #if defined(writeq) && !defined(writeq_relaxed) 211 #define writeq_relaxed writeq 212 #endif 213 214 /* 215 * {read,write}s{b,w,l,q}() repeatedly access the same memory address in 216 * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). 217 */ 218 #ifndef readsb 219 #define readsb readsb 220 static inline void readsb(const volatile void __iomem *addr, void *buffer, 221 unsigned int count) 222 { 223 if (count) { 224 u8 *buf = buffer; 225 226 do { 227 u8 x = __raw_readb(addr); 228 *buf++ = x; 229 } while (--count); 230 } 231 } 232 #endif 233 234 #ifndef readsw 235 #define readsw readsw 236 static inline void readsw(const volatile void __iomem *addr, void *buffer, 237 unsigned int count) 238 { 239 if (count) { 240 u16 *buf = buffer; 241 242 do { 243 u16 x = __raw_readw(addr); 244 *buf++ = x; 245 } while (--count); 246 } 247 } 248 #endif 249 250 #ifndef readsl 251 #define readsl readsl 252 static inline void readsl(const volatile void __iomem *addr, void *buffer, 253 unsigned int count) 254 { 255 if (count) { 256 u32 *buf = buffer; 257 258 do { 259 u32 x = __raw_readl(addr); 260 *buf++ = x; 261 } while (--count); 262 } 263 } 264 #endif 265 266 #ifdef CONFIG_64BIT 267 #ifndef readsq 268 #define readsq readsq 269 static inline void readsq(const volatile void __iomem *addr, void *buffer, 270 unsigned int count) 271 { 272 if (count) { 273 u64 *buf = buffer; 274 275 do { 276 u64 x = __raw_readq(addr); 277 *buf++ = x; 278 } while (--count); 279 } 280 } 281 #endif 282 #endif /* CONFIG_64BIT */ 283 284 #ifndef writesb 285 #define writesb writesb 286 static inline void writesb(volatile void __iomem *addr, const void *buffer, 287 unsigned int count) 288 { 289 if (count) { 290 const u8 *buf = buffer; 291 292 do { 293 __raw_writeb(*buf++, addr); 294 } while (--count); 295 } 296 } 297 #endif 298 299 #ifndef writesw 300 #define writesw writesw 301 static inline void writesw(volatile void __iomem *addr, const void *buffer, 302 unsigned int count) 303 { 304 if (count) { 305 const u16 *buf = buffer; 306 307 do { 308 __raw_writew(*buf++, addr); 309 } while (--count); 310 } 311 } 312 #endif 313 314 #ifndef writesl 315 #define writesl writesl 316 static inline void writesl(volatile void __iomem *addr, const void *buffer, 317 unsigned int count) 318 { 319 if (count) { 320 const u32 *buf = buffer; 321 322 do { 323 __raw_writel(*buf++, addr); 324 } while (--count); 325 } 326 } 327 #endif 328 329 #ifdef CONFIG_64BIT 330 #ifndef writesq 331 #define writesq writesq 332 static inline void writesq(volatile void __iomem *addr, const void *buffer, 333 unsigned int count) 334 { 335 if (count) { 336 const u64 *buf = buffer; 337 338 do { 339 __raw_writeq(*buf++, addr); 340 } while (--count); 341 } 342 } 343 #endif 344 #endif /* CONFIG_64BIT */ 345 346 #ifndef PCI_IOBASE 347 #define PCI_IOBASE ((void __iomem *)0) 348 #endif 349 350 #ifndef IO_SPACE_LIMIT 351 #define IO_SPACE_LIMIT 0xffff 352 #endif 353 354 #include <linux/logic_pio.h> 355 356 /* 357 * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be 358 * implemented on hardware that needs an additional delay for I/O accesses to 359 * take effect. 360 */ 361 362 #ifndef inb 363 #define inb inb 364 static inline u8 inb(unsigned long addr) 365 { 366 return readb(PCI_IOBASE + addr); 367 } 368 #endif 369 370 #ifndef inw 371 #define inw inw 372 static inline u16 inw(unsigned long addr) 373 { 374 return readw(PCI_IOBASE + addr); 375 } 376 #endif 377 378 #ifndef inl 379 #define inl inl 380 static inline u32 inl(unsigned long addr) 381 { 382 return readl(PCI_IOBASE + addr); 383 } 384 #endif 385 386 #ifndef outb 387 #define outb outb 388 static inline void outb(u8 value, unsigned long addr) 389 { 390 writeb(value, PCI_IOBASE + addr); 391 } 392 #endif 393 394 #ifndef outw 395 #define outw outw 396 static inline void outw(u16 value, unsigned long addr) 397 { 398 writew(value, PCI_IOBASE + addr); 399 } 400 #endif 401 402 #ifndef outl 403 #define outl outl 404 static inline void outl(u32 value, unsigned long addr) 405 { 406 writel(value, PCI_IOBASE + addr); 407 } 408 #endif 409 410 #ifndef inb_p 411 #define inb_p inb_p 412 static inline u8 inb_p(unsigned long addr) 413 { 414 return inb(addr); 415 } 416 #endif 417 418 #ifndef inw_p 419 #define inw_p inw_p 420 static inline u16 inw_p(unsigned long addr) 421 { 422 return inw(addr); 423 } 424 #endif 425 426 #ifndef inl_p 427 #define inl_p inl_p 428 static inline u32 inl_p(unsigned long addr) 429 { 430 return inl(addr); 431 } 432 #endif 433 434 #ifndef outb_p 435 #define outb_p outb_p 436 static inline void outb_p(u8 value, unsigned long addr) 437 { 438 outb(value, addr); 439 } 440 #endif 441 442 #ifndef outw_p 443 #define outw_p outw_p 444 static inline void outw_p(u16 value, unsigned long addr) 445 { 446 outw(value, addr); 447 } 448 #endif 449 450 #ifndef outl_p 451 #define outl_p outl_p 452 static inline void outl_p(u32 value, unsigned long addr) 453 { 454 outl(value, addr); 455 } 456 #endif 457 458 /* 459 * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a 460 * single I/O port multiple times. 461 */ 462 463 #ifndef insb 464 #define insb insb 465 static inline void insb(unsigned long addr, void *buffer, unsigned int count) 466 { 467 readsb(PCI_IOBASE + addr, buffer, count); 468 } 469 #endif 470 471 #ifndef insw 472 #define insw insw 473 static inline void insw(unsigned long addr, void *buffer, unsigned int count) 474 { 475 readsw(PCI_IOBASE + addr, buffer, count); 476 } 477 #endif 478 479 #ifndef insl 480 #define insl insl 481 static inline void insl(unsigned long addr, void *buffer, unsigned int count) 482 { 483 readsl(PCI_IOBASE + addr, buffer, count); 484 } 485 #endif 486 487 #ifndef outsb 488 #define outsb outsb 489 static inline void outsb(unsigned long addr, const void *buffer, 490 unsigned int count) 491 { 492 writesb(PCI_IOBASE + addr, buffer, count); 493 } 494 #endif 495 496 #ifndef outsw 497 #define outsw outsw 498 static inline void outsw(unsigned long addr, const void *buffer, 499 unsigned int count) 500 { 501 writesw(PCI_IOBASE + addr, buffer, count); 502 } 503 #endif 504 505 #ifndef outsl 506 #define outsl outsl 507 static inline void outsl(unsigned long addr, const void *buffer, 508 unsigned int count) 509 { 510 writesl(PCI_IOBASE + addr, buffer, count); 511 } 512 #endif 513 514 #ifndef insb_p 515 #define insb_p insb_p 516 static inline void insb_p(unsigned long addr, void *buffer, unsigned int count) 517 { 518 insb(addr, buffer, count); 519 } 520 #endif 521 522 #ifndef insw_p 523 #define insw_p insw_p 524 static inline void insw_p(unsigned long addr, void *buffer, unsigned int count) 525 { 526 insw(addr, buffer, count); 527 } 528 #endif 529 530 #ifndef insl_p 531 #define insl_p insl_p 532 static inline void insl_p(unsigned long addr, void *buffer, unsigned int count) 533 { 534 insl(addr, buffer, count); 535 } 536 #endif 537 538 #ifndef outsb_p 539 #define outsb_p outsb_p 540 static inline void outsb_p(unsigned long addr, const void *buffer, 541 unsigned int count) 542 { 543 outsb(addr, buffer, count); 544 } 545 #endif 546 547 #ifndef outsw_p 548 #define outsw_p outsw_p 549 static inline void outsw_p(unsigned long addr, const void *buffer, 550 unsigned int count) 551 { 552 outsw(addr, buffer, count); 553 } 554 #endif 555 556 #ifndef outsl_p 557 #define outsl_p outsl_p 558 static inline void outsl_p(unsigned long addr, const void *buffer, 559 unsigned int count) 560 { 561 outsl(addr, buffer, count); 562 } 563 #endif 564 565 #ifndef CONFIG_GENERIC_IOMAP 566 #ifndef ioread8 567 #define ioread8 ioread8 568 static inline u8 ioread8(const volatile void __iomem *addr) 569 { 570 return readb(addr); 571 } 572 #endif 573 574 #ifndef ioread16 575 #define ioread16 ioread16 576 static inline u16 ioread16(const volatile void __iomem *addr) 577 { 578 return readw(addr); 579 } 580 #endif 581 582 #ifndef ioread32 583 #define ioread32 ioread32 584 static inline u32 ioread32(const volatile void __iomem *addr) 585 { 586 return readl(addr); 587 } 588 #endif 589 590 #ifdef CONFIG_64BIT 591 #ifndef ioread64 592 #define ioread64 ioread64 593 static inline u64 ioread64(const volatile void __iomem *addr) 594 { 595 return readq(addr); 596 } 597 #endif 598 #endif /* CONFIG_64BIT */ 599 600 #ifndef iowrite8 601 #define iowrite8 iowrite8 602 static inline void iowrite8(u8 value, volatile void __iomem *addr) 603 { 604 writeb(value, addr); 605 } 606 #endif 607 608 #ifndef iowrite16 609 #define iowrite16 iowrite16 610 static inline void iowrite16(u16 value, volatile void __iomem *addr) 611 { 612 writew(value, addr); 613 } 614 #endif 615 616 #ifndef iowrite32 617 #define iowrite32 iowrite32 618 static inline void iowrite32(u32 value, volatile void __iomem *addr) 619 { 620 writel(value, addr); 621 } 622 #endif 623 624 #ifdef CONFIG_64BIT 625 #ifndef iowrite64 626 #define iowrite64 iowrite64 627 static inline void iowrite64(u64 value, volatile void __iomem *addr) 628 { 629 writeq(value, addr); 630 } 631 #endif 632 #endif /* CONFIG_64BIT */ 633 634 #ifndef ioread16be 635 #define ioread16be ioread16be 636 static inline u16 ioread16be(const volatile void __iomem *addr) 637 { 638 return swab16(readw(addr)); 639 } 640 #endif 641 642 #ifndef ioread32be 643 #define ioread32be ioread32be 644 static inline u32 ioread32be(const volatile void __iomem *addr) 645 { 646 return swab32(readl(addr)); 647 } 648 #endif 649 650 #ifdef CONFIG_64BIT 651 #ifndef ioread64be 652 #define ioread64be ioread64be 653 static inline u64 ioread64be(const volatile void __iomem *addr) 654 { 655 return swab64(readq(addr)); 656 } 657 #endif 658 #endif /* CONFIG_64BIT */ 659 660 #ifndef iowrite16be 661 #define iowrite16be iowrite16be 662 static inline void iowrite16be(u16 value, void volatile __iomem *addr) 663 { 664 writew(swab16(value), addr); 665 } 666 #endif 667 668 #ifndef iowrite32be 669 #define iowrite32be iowrite32be 670 static inline void iowrite32be(u32 value, volatile void __iomem *addr) 671 { 672 writel(swab32(value), addr); 673 } 674 #endif 675 676 #ifdef CONFIG_64BIT 677 #ifndef iowrite64be 678 #define iowrite64be iowrite64be 679 static inline void iowrite64be(u64 value, volatile void __iomem *addr) 680 { 681 writeq(swab64(value), addr); 682 } 683 #endif 684 #endif /* CONFIG_64BIT */ 685 686 #ifndef ioread8_rep 687 #define ioread8_rep ioread8_rep 688 static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer, 689 unsigned int count) 690 { 691 readsb(addr, buffer, count); 692 } 693 #endif 694 695 #ifndef ioread16_rep 696 #define ioread16_rep ioread16_rep 697 static inline void ioread16_rep(const volatile void __iomem *addr, 698 void *buffer, unsigned int count) 699 { 700 readsw(addr, buffer, count); 701 } 702 #endif 703 704 #ifndef ioread32_rep 705 #define ioread32_rep ioread32_rep 706 static inline void ioread32_rep(const volatile void __iomem *addr, 707 void *buffer, unsigned int count) 708 { 709 readsl(addr, buffer, count); 710 } 711 #endif 712 713 #ifdef CONFIG_64BIT 714 #ifndef ioread64_rep 715 #define ioread64_rep ioread64_rep 716 static inline void ioread64_rep(const volatile void __iomem *addr, 717 void *buffer, unsigned int count) 718 { 719 readsq(addr, buffer, count); 720 } 721 #endif 722 #endif /* CONFIG_64BIT */ 723 724 #ifndef iowrite8_rep 725 #define iowrite8_rep iowrite8_rep 726 static inline void iowrite8_rep(volatile void __iomem *addr, 727 const void *buffer, 728 unsigned int count) 729 { 730 writesb(addr, buffer, count); 731 } 732 #endif 733 734 #ifndef iowrite16_rep 735 #define iowrite16_rep iowrite16_rep 736 static inline void iowrite16_rep(volatile void __iomem *addr, 737 const void *buffer, 738 unsigned int count) 739 { 740 writesw(addr, buffer, count); 741 } 742 #endif 743 744 #ifndef iowrite32_rep 745 #define iowrite32_rep iowrite32_rep 746 static inline void iowrite32_rep(volatile void __iomem *addr, 747 const void *buffer, 748 unsigned int count) 749 { 750 writesl(addr, buffer, count); 751 } 752 #endif 753 754 #ifdef CONFIG_64BIT 755 #ifndef iowrite64_rep 756 #define iowrite64_rep iowrite64_rep 757 static inline void iowrite64_rep(volatile void __iomem *addr, 758 const void *buffer, 759 unsigned int count) 760 { 761 writesq(addr, buffer, count); 762 } 763 #endif 764 #endif /* CONFIG_64BIT */ 765 #endif /* CONFIG_GENERIC_IOMAP */ 766 767 #ifdef __KERNEL__ 768 769 #include <linux/vmalloc.h> 770 #define __io_virt(x) ((void __force *)(x)) 771 772 #ifndef CONFIG_GENERIC_IOMAP 773 struct pci_dev; 774 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); 775 776 #ifndef pci_iounmap 777 #define pci_iounmap pci_iounmap 778 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) 779 { 780 } 781 #endif 782 #endif /* CONFIG_GENERIC_IOMAP */ 783 784 /* 785 * Change virtual addresses to physical addresses and vv. 786 * These are pretty trivial 787 */ 788 #ifndef virt_to_phys 789 #define virt_to_phys virt_to_phys 790 static inline unsigned long virt_to_phys(volatile void *address) 791 { 792 return __pa((unsigned long)address); 793 } 794 #endif 795 796 #ifndef phys_to_virt 797 #define phys_to_virt phys_to_virt 798 static inline void *phys_to_virt(unsigned long address) 799 { 800 return __va(address); 801 } 802 #endif 803 804 /** 805 * DOC: ioremap() and ioremap_*() variants 806 * 807 * If you have an IOMMU your architecture is expected to have both ioremap() 808 * and iounmap() implemented otherwise the asm-generic helpers will provide a 809 * direct mapping. 810 * 811 * There are ioremap_*() call variants, if you have no IOMMU we naturally will 812 * default to direct mapping for all of them, you can override these defaults. 813 * If you have an IOMMU you are highly encouraged to provide your own 814 * ioremap variant implementation as there currently is no safe architecture 815 * agnostic default. To avoid possible improper behaviour default asm-generic 816 * ioremap_*() variants all return NULL when an IOMMU is available. If you've 817 * defined your own ioremap_*() variant you must then declare your own 818 * ioremap_*() variant as defined to itself to avoid the default NULL return. 819 */ 820 821 #ifdef CONFIG_MMU 822 823 #ifndef ioremap_uc 824 #define ioremap_uc ioremap_uc 825 static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size) 826 { 827 return NULL; 828 } 829 #endif 830 831 #else /* !CONFIG_MMU */ 832 833 /* 834 * Change "struct page" to physical address. 835 * 836 * This implementation is for the no-MMU case only... if you have an MMU 837 * you'll need to provide your own definitions. 838 */ 839 840 #ifndef ioremap 841 #define ioremap ioremap 842 static inline void __iomem *ioremap(phys_addr_t offset, size_t size) 843 { 844 return (void __iomem *)(unsigned long)offset; 845 } 846 #endif 847 848 #ifndef __ioremap 849 #define __ioremap __ioremap 850 static inline void __iomem *__ioremap(phys_addr_t offset, size_t size, 851 unsigned long flags) 852 { 853 return ioremap(offset, size); 854 } 855 #endif 856 857 #ifndef iounmap 858 #define iounmap iounmap 859 860 static inline void iounmap(void __iomem *addr) 861 { 862 } 863 #endif 864 #endif /* CONFIG_MMU */ 865 #ifndef ioremap_nocache 866 void __iomem *ioremap(phys_addr_t phys_addr, size_t size); 867 #define ioremap_nocache ioremap_nocache 868 static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size) 869 { 870 return ioremap(offset, size); 871 } 872 #endif 873 874 #ifndef ioremap_uc 875 #define ioremap_uc ioremap_uc 876 static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size) 877 { 878 return ioremap_nocache(offset, size); 879 } 880 #endif 881 882 #ifndef ioremap_wc 883 #define ioremap_wc ioremap_wc 884 static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size) 885 { 886 return ioremap_nocache(offset, size); 887 } 888 #endif 889 890 #ifndef ioremap_wt 891 #define ioremap_wt ioremap_wt 892 static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size) 893 { 894 return ioremap_nocache(offset, size); 895 } 896 #endif 897 898 #ifdef CONFIG_HAS_IOPORT_MAP 899 #ifndef CONFIG_GENERIC_IOMAP 900 #ifndef ioport_map 901 #define ioport_map ioport_map 902 static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) 903 { 904 return PCI_IOBASE + (port & MMIO_UPPER_LIMIT); 905 } 906 #endif 907 908 #ifndef ioport_unmap 909 #define ioport_unmap ioport_unmap 910 static inline void ioport_unmap(void __iomem *p) 911 { 912 } 913 #endif 914 #else /* CONFIG_GENERIC_IOMAP */ 915 extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 916 extern void ioport_unmap(void __iomem *p); 917 #endif /* CONFIG_GENERIC_IOMAP */ 918 #endif /* CONFIG_HAS_IOPORT_MAP */ 919 920 /* 921 * Convert a virtual cached pointer to an uncached pointer 922 */ 923 #ifndef xlate_dev_kmem_ptr 924 #define xlate_dev_kmem_ptr xlate_dev_kmem_ptr 925 static inline void *xlate_dev_kmem_ptr(void *addr) 926 { 927 return addr; 928 } 929 #endif 930 931 #ifndef xlate_dev_mem_ptr 932 #define xlate_dev_mem_ptr xlate_dev_mem_ptr 933 static inline void *xlate_dev_mem_ptr(phys_addr_t addr) 934 { 935 return __va(addr); 936 } 937 #endif 938 939 #ifndef unxlate_dev_mem_ptr 940 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr 941 static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr) 942 { 943 } 944 #endif 945 946 #ifdef CONFIG_VIRT_TO_BUS 947 #ifndef virt_to_bus 948 static inline unsigned long virt_to_bus(void *address) 949 { 950 return (unsigned long)address; 951 } 952 953 static inline void *bus_to_virt(unsigned long address) 954 { 955 return (void *)address; 956 } 957 #endif 958 #endif 959 960 #ifndef memset_io 961 #define memset_io memset_io 962 /** 963 * memset_io Set a range of I/O memory to a constant value 964 * @addr: The beginning of the I/O-memory range to set 965 * @val: The value to set the memory to 966 * @count: The number of bytes to set 967 * 968 * Set a range of I/O memory to a given value. 969 */ 970 static inline void memset_io(volatile void __iomem *addr, int value, 971 size_t size) 972 { 973 memset(__io_virt(addr), value, size); 974 } 975 #endif 976 977 #ifndef memcpy_fromio 978 #define memcpy_fromio memcpy_fromio 979 /** 980 * memcpy_fromio Copy a block of data from I/O memory 981 * @dst: The (RAM) destination for the copy 982 * @src: The (I/O memory) source for the data 983 * @count: The number of bytes to copy 984 * 985 * Copy a block of data from I/O memory. 986 */ 987 static inline void memcpy_fromio(void *buffer, 988 const volatile void __iomem *addr, 989 size_t size) 990 { 991 memcpy(buffer, __io_virt(addr), size); 992 } 993 #endif 994 995 #ifndef memcpy_toio 996 #define memcpy_toio memcpy_toio 997 /** 998 * memcpy_toio Copy a block of data into I/O memory 999 * @dst: The (I/O memory) destination for the copy 1000 * @src: The (RAM) source for the data 1001 * @count: The number of bytes to copy 1002 * 1003 * Copy a block of data to I/O memory. 1004 */ 1005 static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer, 1006 size_t size) 1007 { 1008 memcpy(__io_virt(addr), buffer, size); 1009 } 1010 #endif 1011 1012 #endif /* __KERNEL__ */ 1013 1014 #endif /* __ASM_GENERIC_IO_H */ 1015