1 /* 2 * sp5100_tco : TCO timer driver for sp5100 chipsets 3 * 4 * (c) Copyright 2009 Google Inc., All Rights Reserved. 5 * 6 * Based on i8xx_tco.c: 7 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights 8 * Reserved. 9 * http://www.kernelconcepts.de 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 * 16 * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide", 17 * AMD Publication 45482 "AMD SB800-Series Southbridges Register 18 * Reference Guide" 19 */ 20 21 /* 22 * Includes, defines, variables, module parameters, ... 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/module.h> 28 #include <linux/moduleparam.h> 29 #include <linux/types.h> 30 #include <linux/miscdevice.h> 31 #include <linux/watchdog.h> 32 #include <linux/init.h> 33 #include <linux/fs.h> 34 #include <linux/pci.h> 35 #include <linux/ioport.h> 36 #include <linux/platform_device.h> 37 #include <linux/uaccess.h> 38 #include <linux/io.h> 39 40 #include "sp5100_tco.h" 41 42 /* Module and version information */ 43 #define TCO_VERSION "0.05" 44 #define TCO_MODULE_NAME "SP5100 TCO timer" 45 #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION 46 47 /* internal variables */ 48 static u32 tcobase_phys; 49 static u32 tco_wdt_fired; 50 static void __iomem *tcobase; 51 static unsigned int pm_iobase; 52 static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */ 53 static unsigned long timer_alive; 54 static char tco_expect_close; 55 static struct pci_dev *sp5100_tco_pci; 56 57 /* the watchdog platform device */ 58 static struct platform_device *sp5100_tco_platform_device; 59 60 /* module parameters */ 61 62 #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */ 63 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ 64 module_param(heartbeat, int, 0); 65 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default=" 66 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); 67 68 static bool nowayout = WATCHDOG_NOWAYOUT; 69 module_param(nowayout, bool, 0); 70 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started." 71 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 72 73 /* 74 * Some TCO specific functions 75 */ 76 77 static bool tco_has_sp5100_reg_layout(struct pci_dev *dev) 78 { 79 return dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && 80 dev->revision < 0x40; 81 } 82 83 static void tco_timer_start(void) 84 { 85 u32 val; 86 unsigned long flags; 87 88 spin_lock_irqsave(&tco_lock, flags); 89 val = readl(SP5100_WDT_CONTROL(tcobase)); 90 val |= SP5100_WDT_START_STOP_BIT; 91 writel(val, SP5100_WDT_CONTROL(tcobase)); 92 spin_unlock_irqrestore(&tco_lock, flags); 93 } 94 95 static void tco_timer_stop(void) 96 { 97 u32 val; 98 unsigned long flags; 99 100 spin_lock_irqsave(&tco_lock, flags); 101 val = readl(SP5100_WDT_CONTROL(tcobase)); 102 val &= ~SP5100_WDT_START_STOP_BIT; 103 writel(val, SP5100_WDT_CONTROL(tcobase)); 104 spin_unlock_irqrestore(&tco_lock, flags); 105 } 106 107 static void tco_timer_keepalive(void) 108 { 109 u32 val; 110 unsigned long flags; 111 112 spin_lock_irqsave(&tco_lock, flags); 113 val = readl(SP5100_WDT_CONTROL(tcobase)); 114 val |= SP5100_WDT_TRIGGER_BIT; 115 writel(val, SP5100_WDT_CONTROL(tcobase)); 116 spin_unlock_irqrestore(&tco_lock, flags); 117 } 118 119 static int tco_timer_set_heartbeat(int t) 120 { 121 unsigned long flags; 122 123 if (t < 0 || t > 0xffff) 124 return -EINVAL; 125 126 /* Write new heartbeat to watchdog */ 127 spin_lock_irqsave(&tco_lock, flags); 128 writel(t, SP5100_WDT_COUNT(tcobase)); 129 spin_unlock_irqrestore(&tco_lock, flags); 130 131 heartbeat = t; 132 return 0; 133 } 134 135 static void tco_timer_enable(void) 136 { 137 int val; 138 139 if (!tco_has_sp5100_reg_layout(sp5100_tco_pci)) { 140 /* For SB800 or later */ 141 /* Set the Watchdog timer resolution to 1 sec */ 142 outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG); 143 val = inb(SB800_IO_PM_DATA_REG); 144 val |= SB800_PM_WATCHDOG_SECOND_RES; 145 outb(val, SB800_IO_PM_DATA_REG); 146 147 /* Enable watchdog decode bit and watchdog timer */ 148 outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG); 149 val = inb(SB800_IO_PM_DATA_REG); 150 val |= SB800_PCI_WATCHDOG_DECODE_EN; 151 val &= ~SB800_PM_WATCHDOG_DISABLE; 152 outb(val, SB800_IO_PM_DATA_REG); 153 } else { 154 /* For SP5100 or SB7x0 */ 155 /* Enable watchdog decode bit */ 156 pci_read_config_dword(sp5100_tco_pci, 157 SP5100_PCI_WATCHDOG_MISC_REG, 158 &val); 159 160 val |= SP5100_PCI_WATCHDOG_DECODE_EN; 161 162 pci_write_config_dword(sp5100_tco_pci, 163 SP5100_PCI_WATCHDOG_MISC_REG, 164 val); 165 166 /* Enable Watchdog timer and set the resolution to 1 sec */ 167 outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG); 168 val = inb(SP5100_IO_PM_DATA_REG); 169 val |= SP5100_PM_WATCHDOG_SECOND_RES; 170 val &= ~SP5100_PM_WATCHDOG_DISABLE; 171 outb(val, SP5100_IO_PM_DATA_REG); 172 } 173 } 174 175 /* 176 * /dev/watchdog handling 177 */ 178 179 static int sp5100_tco_open(struct inode *inode, struct file *file) 180 { 181 /* /dev/watchdog can only be opened once */ 182 if (test_and_set_bit(0, &timer_alive)) 183 return -EBUSY; 184 185 /* Reload and activate timer */ 186 tco_timer_start(); 187 tco_timer_keepalive(); 188 return nonseekable_open(inode, file); 189 } 190 191 static int sp5100_tco_release(struct inode *inode, struct file *file) 192 { 193 /* Shut off the timer. */ 194 if (tco_expect_close == 42) { 195 tco_timer_stop(); 196 } else { 197 pr_crit("Unexpected close, not stopping watchdog!\n"); 198 tco_timer_keepalive(); 199 } 200 clear_bit(0, &timer_alive); 201 tco_expect_close = 0; 202 return 0; 203 } 204 205 static ssize_t sp5100_tco_write(struct file *file, const char __user *data, 206 size_t len, loff_t *ppos) 207 { 208 /* See if we got the magic character 'V' and reload the timer */ 209 if (len) { 210 if (!nowayout) { 211 size_t i; 212 213 /* note: just in case someone wrote the magic character 214 * five months ago... */ 215 tco_expect_close = 0; 216 217 /* scan to see whether or not we got the magic character 218 */ 219 for (i = 0; i != len; i++) { 220 char c; 221 if (get_user(c, data + i)) 222 return -EFAULT; 223 if (c == 'V') 224 tco_expect_close = 42; 225 } 226 } 227 228 /* someone wrote to us, we should reload the timer */ 229 tco_timer_keepalive(); 230 } 231 return len; 232 } 233 234 static long sp5100_tco_ioctl(struct file *file, unsigned int cmd, 235 unsigned long arg) 236 { 237 int new_options, retval = -EINVAL; 238 int new_heartbeat; 239 void __user *argp = (void __user *)arg; 240 int __user *p = argp; 241 static const struct watchdog_info ident = { 242 .options = WDIOF_SETTIMEOUT | 243 WDIOF_KEEPALIVEPING | 244 WDIOF_MAGICCLOSE, 245 .firmware_version = 0, 246 .identity = TCO_MODULE_NAME, 247 }; 248 249 switch (cmd) { 250 case WDIOC_GETSUPPORT: 251 return copy_to_user(argp, &ident, 252 sizeof(ident)) ? -EFAULT : 0; 253 case WDIOC_GETSTATUS: 254 case WDIOC_GETBOOTSTATUS: 255 return put_user(0, p); 256 case WDIOC_SETOPTIONS: 257 if (get_user(new_options, p)) 258 return -EFAULT; 259 if (new_options & WDIOS_DISABLECARD) { 260 tco_timer_stop(); 261 retval = 0; 262 } 263 if (new_options & WDIOS_ENABLECARD) { 264 tco_timer_start(); 265 tco_timer_keepalive(); 266 retval = 0; 267 } 268 return retval; 269 case WDIOC_KEEPALIVE: 270 tco_timer_keepalive(); 271 return 0; 272 case WDIOC_SETTIMEOUT: 273 if (get_user(new_heartbeat, p)) 274 return -EFAULT; 275 if (tco_timer_set_heartbeat(new_heartbeat)) 276 return -EINVAL; 277 tco_timer_keepalive(); 278 /* Fall through */ 279 case WDIOC_GETTIMEOUT: 280 return put_user(heartbeat, p); 281 default: 282 return -ENOTTY; 283 } 284 } 285 286 /* 287 * Kernel Interfaces 288 */ 289 290 static const struct file_operations sp5100_tco_fops = { 291 .owner = THIS_MODULE, 292 .llseek = no_llseek, 293 .write = sp5100_tco_write, 294 .unlocked_ioctl = sp5100_tco_ioctl, 295 .open = sp5100_tco_open, 296 .release = sp5100_tco_release, 297 }; 298 299 static struct miscdevice sp5100_tco_miscdev = { 300 .minor = WATCHDOG_MINOR, 301 .name = "watchdog", 302 .fops = &sp5100_tco_fops, 303 }; 304 305 /* 306 * Data for PCI driver interface 307 * 308 * This data only exists for exporting the supported 309 * PCI ids via MODULE_DEVICE_TABLE. We do not actually 310 * register a pci_driver, because someone else might 311 * want to register another driver on the same PCI id. 312 */ 313 static const struct pci_device_id sp5100_tco_pci_tbl[] = { 314 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID, 315 PCI_ANY_ID, }, 316 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID, 317 PCI_ANY_ID, }, 318 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID, 319 PCI_ANY_ID, }, 320 { 0, }, /* End of list */ 321 }; 322 MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl); 323 324 /* 325 * Init & exit routines 326 */ 327 static unsigned char sp5100_tco_setupdevice(void) 328 { 329 struct pci_dev *dev = NULL; 330 const char *dev_name = NULL; 331 u32 val; 332 u32 index_reg, data_reg, base_addr; 333 334 /* Match the PCI device */ 335 for_each_pci_dev(dev) { 336 if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) { 337 sp5100_tco_pci = dev; 338 break; 339 } 340 } 341 342 if (!sp5100_tco_pci) 343 return 0; 344 345 pr_info("PCI Vendor ID: 0x%x, Device ID: 0x%x, Revision ID: 0x%x\n", 346 sp5100_tco_pci->vendor, sp5100_tco_pci->device, 347 sp5100_tco_pci->revision); 348 349 /* 350 * Determine type of southbridge chipset. 351 */ 352 if (tco_has_sp5100_reg_layout(sp5100_tco_pci)) { 353 dev_name = SP5100_DEVNAME; 354 index_reg = SP5100_IO_PM_INDEX_REG; 355 data_reg = SP5100_IO_PM_DATA_REG; 356 base_addr = SP5100_PM_WATCHDOG_BASE; 357 } else { 358 dev_name = SB800_DEVNAME; 359 index_reg = SB800_IO_PM_INDEX_REG; 360 data_reg = SB800_IO_PM_DATA_REG; 361 base_addr = SB800_PM_WATCHDOG_BASE; 362 } 363 364 /* Request the IO ports used by this driver */ 365 pm_iobase = SP5100_IO_PM_INDEX_REG; 366 if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) { 367 pr_err("I/O address 0x%04x already in use\n", pm_iobase); 368 goto exit; 369 } 370 371 /* 372 * First, Find the watchdog timer MMIO address from indirect I/O. 373 */ 374 outb(base_addr+3, index_reg); 375 val = inb(data_reg); 376 outb(base_addr+2, index_reg); 377 val = val << 8 | inb(data_reg); 378 outb(base_addr+1, index_reg); 379 val = val << 8 | inb(data_reg); 380 outb(base_addr+0, index_reg); 381 /* Low three bits of BASE are reserved */ 382 val = val << 8 | (inb(data_reg) & 0xf8); 383 384 pr_debug("Got 0x%04x from indirect I/O\n", val); 385 386 /* Check MMIO address conflict */ 387 if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE, 388 dev_name)) 389 goto setup_wdt; 390 else 391 pr_debug("MMIO address 0x%04x already in use\n", val); 392 393 /* 394 * Secondly, Find the watchdog timer MMIO address 395 * from SBResource_MMIO register. 396 */ 397 if (tco_has_sp5100_reg_layout(sp5100_tco_pci)) { 398 /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */ 399 pci_read_config_dword(sp5100_tco_pci, 400 SP5100_SB_RESOURCE_MMIO_BASE, &val); 401 } else { 402 /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */ 403 outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG); 404 val = inb(SB800_IO_PM_DATA_REG); 405 outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG); 406 val = val << 8 | inb(SB800_IO_PM_DATA_REG); 407 outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG); 408 val = val << 8 | inb(SB800_IO_PM_DATA_REG); 409 outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG); 410 val = val << 8 | inb(SB800_IO_PM_DATA_REG); 411 } 412 413 /* The SBResource_MMIO is enabled and mapped memory space? */ 414 if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) == 415 SB800_ACPI_MMIO_DECODE_EN) { 416 /* Clear unnecessary the low twelve bits */ 417 val &= ~0xFFF; 418 /* Add the Watchdog Timer offset to base address. */ 419 val += SB800_PM_WDT_MMIO_OFFSET; 420 /* Check MMIO address conflict */ 421 if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE, 422 dev_name)) { 423 pr_debug("Got 0x%04x from SBResource_MMIO register\n", 424 val); 425 goto setup_wdt; 426 } else 427 pr_debug("MMIO address 0x%04x already in use\n", val); 428 } else 429 pr_debug("SBResource_MMIO is disabled(0x%04x)\n", val); 430 431 pr_notice("failed to find MMIO address, giving up.\n"); 432 goto unreg_region; 433 434 setup_wdt: 435 tcobase_phys = val; 436 437 tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE); 438 if (!tcobase) { 439 pr_err("failed to get tcobase address\n"); 440 goto unreg_mem_region; 441 } 442 443 pr_info("Using 0x%04x for watchdog MMIO address\n", val); 444 445 /* Setup the watchdog timer */ 446 tco_timer_enable(); 447 448 /* Check that the watchdog action is set to reset the system */ 449 val = readl(SP5100_WDT_CONTROL(tcobase)); 450 /* 451 * Save WatchDogFired status, because WatchDogFired flag is 452 * cleared here. 453 */ 454 tco_wdt_fired = val & SP5100_PM_WATCHDOG_FIRED; 455 val &= ~SP5100_PM_WATCHDOG_ACTION_RESET; 456 writel(val, SP5100_WDT_CONTROL(tcobase)); 457 458 /* Set a reasonable heartbeat before we stop the timer */ 459 tco_timer_set_heartbeat(heartbeat); 460 461 /* 462 * Stop the TCO before we change anything so we don't race with 463 * a zeroed timer. 464 */ 465 tco_timer_stop(); 466 467 /* Done */ 468 return 1; 469 470 unreg_mem_region: 471 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); 472 unreg_region: 473 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); 474 exit: 475 return 0; 476 } 477 478 static int sp5100_tco_init(struct platform_device *dev) 479 { 480 int ret; 481 482 /* 483 * Check whether or not the hardware watchdog is there. If found, then 484 * set it up. 485 */ 486 if (!sp5100_tco_setupdevice()) 487 return -ENODEV; 488 489 /* Check to see if last reboot was due to watchdog timeout */ 490 pr_info("Last reboot was %striggered by watchdog.\n", 491 tco_wdt_fired ? "" : "not "); 492 493 /* 494 * Check that the heartbeat value is within it's range. 495 * If not, reset to the default. 496 */ 497 if (tco_timer_set_heartbeat(heartbeat)) { 498 heartbeat = WATCHDOG_HEARTBEAT; 499 tco_timer_set_heartbeat(heartbeat); 500 } 501 502 ret = misc_register(&sp5100_tco_miscdev); 503 if (ret != 0) { 504 pr_err("cannot register miscdev on minor=%d (err=%d)\n", 505 WATCHDOG_MINOR, ret); 506 goto exit; 507 } 508 509 clear_bit(0, &timer_alive); 510 511 /* Show module parameters */ 512 pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", 513 tcobase, heartbeat, nowayout); 514 515 return 0; 516 517 exit: 518 iounmap(tcobase); 519 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); 520 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); 521 return ret; 522 } 523 524 static void sp5100_tco_cleanup(void) 525 { 526 /* Stop the timer before we leave */ 527 if (!nowayout) 528 tco_timer_stop(); 529 530 /* Deregister */ 531 misc_deregister(&sp5100_tco_miscdev); 532 iounmap(tcobase); 533 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); 534 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); 535 } 536 537 static int sp5100_tco_remove(struct platform_device *dev) 538 { 539 if (tcobase) 540 sp5100_tco_cleanup(); 541 return 0; 542 } 543 544 static void sp5100_tco_shutdown(struct platform_device *dev) 545 { 546 tco_timer_stop(); 547 } 548 549 static struct platform_driver sp5100_tco_driver = { 550 .probe = sp5100_tco_init, 551 .remove = sp5100_tco_remove, 552 .shutdown = sp5100_tco_shutdown, 553 .driver = { 554 .name = TCO_MODULE_NAME, 555 }, 556 }; 557 558 static int __init sp5100_tco_init_module(void) 559 { 560 int err; 561 562 pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION); 563 564 err = platform_driver_register(&sp5100_tco_driver); 565 if (err) 566 return err; 567 568 sp5100_tco_platform_device = platform_device_register_simple( 569 TCO_MODULE_NAME, -1, NULL, 0); 570 if (IS_ERR(sp5100_tco_platform_device)) { 571 err = PTR_ERR(sp5100_tco_platform_device); 572 goto unreg_platform_driver; 573 } 574 575 return 0; 576 577 unreg_platform_driver: 578 platform_driver_unregister(&sp5100_tco_driver); 579 return err; 580 } 581 582 static void __exit sp5100_tco_cleanup_module(void) 583 { 584 platform_device_unregister(sp5100_tco_platform_device); 585 platform_driver_unregister(&sp5100_tco_driver); 586 pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n"); 587 } 588 589 module_init(sp5100_tco_init_module); 590 module_exit(sp5100_tco_cleanup_module); 591 592 MODULE_AUTHOR("Priyanka Gupta"); 593 MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset"); 594 MODULE_LICENSE("GPL"); 595