1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * sp5100_tco : TCO timer driver for sp5100 chipsets 4 * 5 * (c) Copyright 2009 Google Inc., All Rights Reserved. 6 * 7 * Based on i8xx_tco.c: 8 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights 9 * Reserved. 10 * https://www.kernelconcepts.de 11 * 12 * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide", 13 * AMD Publication 44413 "AMD SP5100 Register Reference Guide" 14 * AMD Publication 45482 "AMD SB800-Series Southbridges Register 15 * Reference Guide" 16 * AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG) 17 * for AMD Family 16h Models 00h-0Fh Processors" 18 * AMD Publication 51192 "AMD Bolton FCH Register Reference Guide" 19 * AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG) 20 * for AMD Family 16h Models 30h-3Fh Processors" 21 * AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR) 22 * for AMD Family 17h Model 18h, Revision B1 23 * Processors (PUB) 24 * AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR) 25 * for AMD Family 17h Model 20h, Revision A1 26 * Processors (PUB) 27 */ 28 29 /* 30 * Includes, defines, variables, module parameters, ... 31 */ 32 33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35 #include <linux/init.h> 36 #include <linux/io.h> 37 #include <linux/ioport.h> 38 #include <linux/module.h> 39 #include <linux/moduleparam.h> 40 #include <linux/pci.h> 41 #include <linux/platform_device.h> 42 #include <linux/types.h> 43 #include <linux/watchdog.h> 44 45 #include "sp5100_tco.h" 46 47 #define TCO_DRIVER_NAME "sp5100-tco" 48 49 /* internal variables */ 50 51 enum tco_reg_layout { 52 sp5100, sb800, efch 53 }; 54 55 struct sp5100_tco { 56 struct watchdog_device wdd; 57 void __iomem *tcobase; 58 enum tco_reg_layout tco_reg_layout; 59 }; 60 61 /* the watchdog platform device */ 62 static struct platform_device *sp5100_tco_platform_device; 63 /* the associated PCI device */ 64 static struct pci_dev *sp5100_tco_pci; 65 66 /* module parameters */ 67 68 #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */ 69 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ 70 module_param(heartbeat, int, 0); 71 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default=" 72 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); 73 74 static bool nowayout = WATCHDOG_NOWAYOUT; 75 module_param(nowayout, bool, 0); 76 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started." 77 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 78 79 /* 80 * Some TCO specific functions 81 */ 82 83 static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev) 84 { 85 if (dev->vendor == PCI_VENDOR_ID_ATI && 86 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && 87 dev->revision < 0x40) { 88 return sp5100; 89 } else if (dev->vendor == PCI_VENDOR_ID_AMD && 90 ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 91 dev->revision >= 0x41) || 92 (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 93 dev->revision >= 0x49))) { 94 return efch; 95 } 96 return sb800; 97 } 98 99 static int tco_timer_start(struct watchdog_device *wdd) 100 { 101 struct sp5100_tco *tco = watchdog_get_drvdata(wdd); 102 u32 val; 103 104 val = readl(SP5100_WDT_CONTROL(tco->tcobase)); 105 val |= SP5100_WDT_START_STOP_BIT; 106 writel(val, SP5100_WDT_CONTROL(tco->tcobase)); 107 108 return 0; 109 } 110 111 static int tco_timer_stop(struct watchdog_device *wdd) 112 { 113 struct sp5100_tco *tco = watchdog_get_drvdata(wdd); 114 u32 val; 115 116 val = readl(SP5100_WDT_CONTROL(tco->tcobase)); 117 val &= ~SP5100_WDT_START_STOP_BIT; 118 writel(val, SP5100_WDT_CONTROL(tco->tcobase)); 119 120 return 0; 121 } 122 123 static int tco_timer_ping(struct watchdog_device *wdd) 124 { 125 struct sp5100_tco *tco = watchdog_get_drvdata(wdd); 126 u32 val; 127 128 val = readl(SP5100_WDT_CONTROL(tco->tcobase)); 129 val |= SP5100_WDT_TRIGGER_BIT; 130 writel(val, SP5100_WDT_CONTROL(tco->tcobase)); 131 132 return 0; 133 } 134 135 static int tco_timer_set_timeout(struct watchdog_device *wdd, 136 unsigned int t) 137 { 138 struct sp5100_tco *tco = watchdog_get_drvdata(wdd); 139 140 /* Write new heartbeat to watchdog */ 141 writel(t, SP5100_WDT_COUNT(tco->tcobase)); 142 143 wdd->timeout = t; 144 145 return 0; 146 } 147 148 static unsigned int tco_timer_get_timeleft(struct watchdog_device *wdd) 149 { 150 struct sp5100_tco *tco = watchdog_get_drvdata(wdd); 151 152 return readl(SP5100_WDT_COUNT(tco->tcobase)); 153 } 154 155 static u8 sp5100_tco_read_pm_reg8(u8 index) 156 { 157 outb(index, SP5100_IO_PM_INDEX_REG); 158 return inb(SP5100_IO_PM_DATA_REG); 159 } 160 161 static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set) 162 { 163 u8 val; 164 165 outb(index, SP5100_IO_PM_INDEX_REG); 166 val = inb(SP5100_IO_PM_DATA_REG); 167 val &= reset; 168 val |= set; 169 outb(val, SP5100_IO_PM_DATA_REG); 170 } 171 172 static void tco_timer_enable(struct sp5100_tco *tco) 173 { 174 u32 val; 175 176 switch (tco->tco_reg_layout) { 177 case sb800: 178 /* For SB800 or later */ 179 /* Set the Watchdog timer resolution to 1 sec */ 180 sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG, 181 0xff, SB800_PM_WATCHDOG_SECOND_RES); 182 183 /* Enable watchdog decode bit and watchdog timer */ 184 sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL, 185 ~SB800_PM_WATCHDOG_DISABLE, 186 SB800_PCI_WATCHDOG_DECODE_EN); 187 break; 188 case sp5100: 189 /* For SP5100 or SB7x0 */ 190 /* Enable watchdog decode bit */ 191 pci_read_config_dword(sp5100_tco_pci, 192 SP5100_PCI_WATCHDOG_MISC_REG, 193 &val); 194 195 val |= SP5100_PCI_WATCHDOG_DECODE_EN; 196 197 pci_write_config_dword(sp5100_tco_pci, 198 SP5100_PCI_WATCHDOG_MISC_REG, 199 val); 200 201 /* Enable Watchdog timer and set the resolution to 1 sec */ 202 sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL, 203 ~SP5100_PM_WATCHDOG_DISABLE, 204 SP5100_PM_WATCHDOG_SECOND_RES); 205 break; 206 case efch: 207 /* Set the Watchdog timer resolution to 1 sec and enable */ 208 sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3, 209 ~EFCH_PM_WATCHDOG_DISABLE, 210 EFCH_PM_DECODEEN_SECOND_RES); 211 break; 212 } 213 } 214 215 static u32 sp5100_tco_read_pm_reg32(u8 index) 216 { 217 u32 val = 0; 218 int i; 219 220 for (i = 3; i >= 0; i--) 221 val = (val << 8) + sp5100_tco_read_pm_reg8(index + i); 222 223 return val; 224 } 225 226 static int sp5100_tco_setupdevice(struct device *dev, 227 struct watchdog_device *wdd) 228 { 229 struct sp5100_tco *tco = watchdog_get_drvdata(wdd); 230 const char *dev_name; 231 u32 mmio_addr = 0, val; 232 int ret; 233 234 /* Request the IO ports used by this driver */ 235 if (!request_muxed_region(SP5100_IO_PM_INDEX_REG, 236 SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) { 237 dev_err(dev, "I/O address 0x%04x already in use\n", 238 SP5100_IO_PM_INDEX_REG); 239 return -EBUSY; 240 } 241 242 /* 243 * Determine type of southbridge chipset. 244 */ 245 switch (tco->tco_reg_layout) { 246 case sp5100: 247 dev_name = SP5100_DEVNAME; 248 mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) & 249 0xfffffff8; 250 break; 251 case sb800: 252 dev_name = SB800_DEVNAME; 253 mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) & 254 0xfffffff8; 255 break; 256 case efch: 257 dev_name = SB800_DEVNAME; 258 /* 259 * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of 260 * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory 261 * region, it also enables the watchdog itself. 262 */ 263 if (boot_cpu_data.x86 == 0x17) { 264 val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN); 265 if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) { 266 sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff, 267 EFCH_PM_DECODEEN_WDT_TMREN); 268 } 269 } 270 val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN); 271 if (val & EFCH_PM_DECODEEN_WDT_TMREN) 272 mmio_addr = EFCH_PM_WDT_ADDR; 273 break; 274 default: 275 return -ENODEV; 276 } 277 278 /* Check MMIO address conflict */ 279 if (!mmio_addr || 280 !devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE, 281 dev_name)) { 282 if (mmio_addr) 283 dev_dbg(dev, "MMIO address 0x%08x already in use\n", 284 mmio_addr); 285 switch (tco->tco_reg_layout) { 286 case sp5100: 287 /* 288 * Secondly, Find the watchdog timer MMIO address 289 * from SBResource_MMIO register. 290 */ 291 /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */ 292 pci_read_config_dword(sp5100_tco_pci, 293 SP5100_SB_RESOURCE_MMIO_BASE, 294 &mmio_addr); 295 if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN | 296 SB800_ACPI_MMIO_SEL)) != 297 SB800_ACPI_MMIO_DECODE_EN) { 298 ret = -ENODEV; 299 goto unreg_region; 300 } 301 mmio_addr &= ~0xFFF; 302 mmio_addr += SB800_PM_WDT_MMIO_OFFSET; 303 break; 304 case sb800: 305 /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */ 306 mmio_addr = 307 sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN); 308 if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN | 309 SB800_ACPI_MMIO_SEL)) != 310 SB800_ACPI_MMIO_DECODE_EN) { 311 ret = -ENODEV; 312 goto unreg_region; 313 } 314 mmio_addr &= ~0xFFF; 315 mmio_addr += SB800_PM_WDT_MMIO_OFFSET; 316 break; 317 case efch: 318 val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL); 319 if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) { 320 ret = -ENODEV; 321 goto unreg_region; 322 } 323 mmio_addr = EFCH_PM_ACPI_MMIO_ADDR + 324 EFCH_PM_ACPI_MMIO_WDT_OFFSET; 325 break; 326 } 327 dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n", 328 mmio_addr); 329 if (!devm_request_mem_region(dev, mmio_addr, 330 SP5100_WDT_MEM_MAP_SIZE, 331 dev_name)) { 332 dev_dbg(dev, "MMIO address 0x%08x already in use\n", 333 mmio_addr); 334 ret = -EBUSY; 335 goto unreg_region; 336 } 337 } 338 339 tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE); 340 if (!tco->tcobase) { 341 dev_err(dev, "failed to get tcobase address\n"); 342 ret = -ENOMEM; 343 goto unreg_region; 344 } 345 346 dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr); 347 348 /* Setup the watchdog timer */ 349 tco_timer_enable(tco); 350 351 val = readl(SP5100_WDT_CONTROL(tco->tcobase)); 352 if (val & SP5100_WDT_DISABLED) { 353 dev_err(dev, "Watchdog hardware is disabled\n"); 354 ret = -ENODEV; 355 goto unreg_region; 356 } 357 358 /* 359 * Save WatchDogFired status, because WatchDogFired flag is 360 * cleared here. 361 */ 362 if (val & SP5100_WDT_FIRED) 363 wdd->bootstatus = WDIOF_CARDRESET; 364 /* Set watchdog action to reset the system */ 365 val &= ~SP5100_WDT_ACTION_RESET; 366 writel(val, SP5100_WDT_CONTROL(tco->tcobase)); 367 368 /* Set a reasonable heartbeat before we stop the timer */ 369 tco_timer_set_timeout(wdd, wdd->timeout); 370 371 /* 372 * Stop the TCO before we change anything so we don't race with 373 * a zeroed timer. 374 */ 375 tco_timer_stop(wdd); 376 377 release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE); 378 379 return 0; 380 381 unreg_region: 382 release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE); 383 return ret; 384 } 385 386 static struct watchdog_info sp5100_tco_wdt_info = { 387 .identity = "SP5100 TCO timer", 388 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, 389 }; 390 391 static const struct watchdog_ops sp5100_tco_wdt_ops = { 392 .owner = THIS_MODULE, 393 .start = tco_timer_start, 394 .stop = tco_timer_stop, 395 .ping = tco_timer_ping, 396 .set_timeout = tco_timer_set_timeout, 397 .get_timeleft = tco_timer_get_timeleft, 398 }; 399 400 static int sp5100_tco_probe(struct platform_device *pdev) 401 { 402 struct device *dev = &pdev->dev; 403 struct watchdog_device *wdd; 404 struct sp5100_tco *tco; 405 int ret; 406 407 tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL); 408 if (!tco) 409 return -ENOMEM; 410 411 tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci); 412 413 wdd = &tco->wdd; 414 wdd->parent = dev; 415 wdd->info = &sp5100_tco_wdt_info; 416 wdd->ops = &sp5100_tco_wdt_ops; 417 wdd->timeout = WATCHDOG_HEARTBEAT; 418 wdd->min_timeout = 1; 419 wdd->max_timeout = 0xffff; 420 421 watchdog_init_timeout(wdd, heartbeat, NULL); 422 watchdog_set_nowayout(wdd, nowayout); 423 watchdog_stop_on_reboot(wdd); 424 watchdog_stop_on_unregister(wdd); 425 watchdog_set_drvdata(wdd, tco); 426 427 ret = sp5100_tco_setupdevice(dev, wdd); 428 if (ret) 429 return ret; 430 431 ret = devm_watchdog_register_device(dev, wdd); 432 if (ret) 433 return ret; 434 435 /* Show module parameters */ 436 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n", 437 wdd->timeout, nowayout); 438 439 return 0; 440 } 441 442 static struct platform_driver sp5100_tco_driver = { 443 .probe = sp5100_tco_probe, 444 .driver = { 445 .name = TCO_DRIVER_NAME, 446 }, 447 }; 448 449 /* 450 * Data for PCI driver interface 451 * 452 * This data only exists for exporting the supported 453 * PCI ids via MODULE_DEVICE_TABLE. We do not actually 454 * register a pci_driver, because someone else might 455 * want to register another driver on the same PCI id. 456 */ 457 static const struct pci_device_id sp5100_tco_pci_tbl[] = { 458 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID, 459 PCI_ANY_ID, }, 460 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID, 461 PCI_ANY_ID, }, 462 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID, 463 PCI_ANY_ID, }, 464 { 0, }, /* End of list */ 465 }; 466 MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl); 467 468 static int __init sp5100_tco_init(void) 469 { 470 struct pci_dev *dev = NULL; 471 int err; 472 473 /* Match the PCI device */ 474 for_each_pci_dev(dev) { 475 if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) { 476 sp5100_tco_pci = dev; 477 break; 478 } 479 } 480 481 if (!sp5100_tco_pci) 482 return -ENODEV; 483 484 pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n"); 485 486 err = platform_driver_register(&sp5100_tco_driver); 487 if (err) 488 return err; 489 490 sp5100_tco_platform_device = 491 platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0); 492 if (IS_ERR(sp5100_tco_platform_device)) { 493 err = PTR_ERR(sp5100_tco_platform_device); 494 goto unreg_platform_driver; 495 } 496 497 return 0; 498 499 unreg_platform_driver: 500 platform_driver_unregister(&sp5100_tco_driver); 501 return err; 502 } 503 504 static void __exit sp5100_tco_exit(void) 505 { 506 platform_device_unregister(sp5100_tco_platform_device); 507 platform_driver_unregister(&sp5100_tco_driver); 508 } 509 510 module_init(sp5100_tco_init); 511 module_exit(sp5100_tco_exit); 512 513 MODULE_AUTHOR("Priyanka Gupta"); 514 MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset"); 515 MODULE_LICENSE("GPL"); 516