1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PIC32 deadman timer driver 4 * 5 * Purna Chandra Mandal <purna.mandal@microchip.com> 6 * Copyright (c) 2016, Microchip Technology Inc. 7 */ 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_data/pic32.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/watchdog.h> 19 20 /* Deadman Timer Regs */ 21 #define DMTCON_REG 0x00 22 #define DMTPRECLR_REG 0x10 23 #define DMTCLR_REG 0x20 24 #define DMTSTAT_REG 0x30 25 #define DMTCNT_REG 0x40 26 #define DMTPSCNT_REG 0x60 27 #define DMTPSINTV_REG 0x70 28 29 /* Deadman Timer Regs fields */ 30 #define DMT_ON BIT(15) 31 #define DMT_STEP1_KEY BIT(6) 32 #define DMT_STEP2_KEY BIT(3) 33 #define DMTSTAT_WINOPN BIT(0) 34 #define DMTSTAT_EVENT BIT(5) 35 #define DMTSTAT_BAD2 BIT(6) 36 #define DMTSTAT_BAD1 BIT(7) 37 38 /* Reset Control Register fields for watchdog */ 39 #define RESETCON_DMT_TIMEOUT BIT(5) 40 41 struct pic32_dmt { 42 void __iomem *regs; 43 struct clk *clk; 44 }; 45 46 static inline void dmt_enable(struct pic32_dmt *dmt) 47 { 48 writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG)); 49 } 50 51 static inline void dmt_disable(struct pic32_dmt *dmt) 52 { 53 writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG)); 54 /* 55 * Cannot touch registers in the CPU cycle following clearing the 56 * ON bit. 57 */ 58 nop(); 59 } 60 61 static inline int dmt_bad_status(struct pic32_dmt *dmt) 62 { 63 u32 val; 64 65 val = readl(dmt->regs + DMTSTAT_REG); 66 val &= (DMTSTAT_BAD1 | DMTSTAT_BAD2 | DMTSTAT_EVENT); 67 if (val) 68 return -EAGAIN; 69 70 return 0; 71 } 72 73 static inline int dmt_keepalive(struct pic32_dmt *dmt) 74 { 75 u32 v; 76 u32 timeout = 500; 77 78 /* set pre-clear key */ 79 writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG); 80 81 /* wait for DMT window to open */ 82 while (--timeout) { 83 v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN; 84 if (v == DMTSTAT_WINOPN) 85 break; 86 } 87 88 /* apply key2 */ 89 writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG); 90 91 /* check whether keys are latched correctly */ 92 return dmt_bad_status(dmt); 93 } 94 95 static inline u32 pic32_dmt_get_timeout_secs(struct pic32_dmt *dmt) 96 { 97 unsigned long rate; 98 99 rate = clk_get_rate(dmt->clk); 100 if (rate) 101 return readl(dmt->regs + DMTPSCNT_REG) / rate; 102 103 return 0; 104 } 105 106 static inline u32 pic32_dmt_bootstatus(struct pic32_dmt *dmt) 107 { 108 u32 v; 109 void __iomem *rst_base; 110 111 rst_base = ioremap(PIC32_BASE_RESET, 0x10); 112 if (!rst_base) 113 return 0; 114 115 v = readl(rst_base); 116 117 writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base)); 118 119 iounmap(rst_base); 120 return v & RESETCON_DMT_TIMEOUT; 121 } 122 123 static int pic32_dmt_start(struct watchdog_device *wdd) 124 { 125 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd); 126 127 dmt_enable(dmt); 128 return dmt_keepalive(dmt); 129 } 130 131 static int pic32_dmt_stop(struct watchdog_device *wdd) 132 { 133 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd); 134 135 dmt_disable(dmt); 136 137 return 0; 138 } 139 140 static int pic32_dmt_ping(struct watchdog_device *wdd) 141 { 142 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd); 143 144 return dmt_keepalive(dmt); 145 } 146 147 static const struct watchdog_ops pic32_dmt_fops = { 148 .owner = THIS_MODULE, 149 .start = pic32_dmt_start, 150 .stop = pic32_dmt_stop, 151 .ping = pic32_dmt_ping, 152 }; 153 154 static const struct watchdog_info pic32_dmt_ident = { 155 .options = WDIOF_KEEPALIVEPING | 156 WDIOF_MAGICCLOSE, 157 .identity = "PIC32 Deadman Timer", 158 }; 159 160 static struct watchdog_device pic32_dmt_wdd = { 161 .info = &pic32_dmt_ident, 162 .ops = &pic32_dmt_fops, 163 }; 164 165 static int pic32_dmt_probe(struct platform_device *pdev) 166 { 167 struct device *dev = &pdev->dev; 168 int ret; 169 struct pic32_dmt *dmt; 170 struct watchdog_device *wdd = &pic32_dmt_wdd; 171 172 dmt = devm_kzalloc(dev, sizeof(*dmt), GFP_KERNEL); 173 if (!dmt) 174 return -ENOMEM; 175 176 dmt->regs = devm_platform_ioremap_resource(pdev, 0); 177 if (IS_ERR(dmt->regs)) 178 return PTR_ERR(dmt->regs); 179 180 dmt->clk = devm_clk_get_enabled(dev, NULL); 181 if (IS_ERR(dmt->clk)) { 182 dev_err(dev, "clk not found\n"); 183 return PTR_ERR(dmt->clk); 184 } 185 186 wdd->timeout = pic32_dmt_get_timeout_secs(dmt); 187 if (!wdd->timeout) { 188 dev_err(dev, "failed to read watchdog register timeout\n"); 189 return -EINVAL; 190 } 191 192 dev_info(dev, "timeout %d\n", wdd->timeout); 193 194 wdd->bootstatus = pic32_dmt_bootstatus(dmt) ? WDIOF_CARDRESET : 0; 195 196 watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT); 197 watchdog_set_drvdata(wdd, dmt); 198 199 ret = devm_watchdog_register_device(dev, wdd); 200 if (ret) 201 return ret; 202 203 platform_set_drvdata(pdev, wdd); 204 return 0; 205 } 206 207 static const struct of_device_id pic32_dmt_of_ids[] = { 208 { .compatible = "microchip,pic32mzda-dmt",}, 209 { /* sentinel */ } 210 }; 211 MODULE_DEVICE_TABLE(of, pic32_dmt_of_ids); 212 213 static struct platform_driver pic32_dmt_driver = { 214 .probe = pic32_dmt_probe, 215 .driver = { 216 .name = "pic32-dmt", 217 .of_match_table = of_match_ptr(pic32_dmt_of_ids), 218 } 219 }; 220 221 module_platform_driver(pic32_dmt_driver); 222 223 MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>"); 224 MODULE_DESCRIPTION("Microchip PIC32 DMT Driver"); 225 MODULE_LICENSE("GPL"); 226