1 /* 2 * Octeon Watchdog driver 3 * 4 * Copyright (C) 2007-2017 Cavium, Inc. 5 * 6 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>. 7 * 8 * Some parts derived from wdt.c 9 * 10 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>, 11 * All Rights Reserved. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 * 18 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide 19 * warranty for any of this software. This material is provided 20 * "AS-IS" and at no charge. 21 * 22 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> 23 * 24 * This file is subject to the terms and conditions of the GNU General Public 25 * License. See the file "COPYING" in the main directory of this archive 26 * for more details. 27 * 28 * 29 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. 30 * For most systems this is less than 10 seconds, so to allow for 31 * software to request longer watchdog heartbeats, we maintain software 32 * counters to count multiples of the base rate. If the system locks 33 * up in such a manner that we can not run the software counters, the 34 * only result is a watchdog reset sooner than was requested. But 35 * that is OK, because in this case userspace would likely not be able 36 * to do anything anyhow. 37 * 38 * The hardware watchdog interval we call the period. The OCTEON 39 * watchdog goes through several stages, after the first period an 40 * irq is asserted, then if it is not reset, after the next period NMI 41 * is asserted, then after an additional period a chip wide soft reset. 42 * So for the software counters, we reset watchdog after each period 43 * and decrement the counter. But for the last two periods we need to 44 * let the watchdog progress to the NMI stage so we disable the irq 45 * and let it proceed. Once in the NMI, we print the register state 46 * to the serial port and then wait for the reset. 47 * 48 * A watchdog is maintained for each CPU in the system, that way if 49 * one CPU suffers a lockup, we also get a register dump and reset. 50 * The userspace ping resets the watchdog on all CPUs. 51 * 52 * Before userspace opens the watchdog device, we still run the 53 * watchdogs to catch any lockups that may be kernel related. 54 * 55 */ 56 57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 58 59 #include <linux/interrupt.h> 60 #include <linux/watchdog.h> 61 #include <linux/cpumask.h> 62 #include <linux/module.h> 63 #include <linux/delay.h> 64 #include <linux/cpu.h> 65 #include <linux/irq.h> 66 67 #include <asm/mipsregs.h> 68 #include <asm/uasm.h> 69 70 #include <asm/octeon/octeon.h> 71 #include <asm/octeon/cvmx-boot-vector.h> 72 #include <asm/octeon/cvmx-ciu2-defs.h> 73 #include <asm/octeon/cvmx-rst-defs.h> 74 75 /* Watchdog interrupt major block number (8 MSBs of intsn) */ 76 #define WD_BLOCK_NUMBER 0x01 77 78 static int divisor; 79 80 /* The count needed to achieve timeout_sec. */ 81 static unsigned int timeout_cnt; 82 83 /* The maximum period supported. */ 84 static unsigned int max_timeout_sec; 85 86 /* The current period. */ 87 static unsigned int timeout_sec; 88 89 /* Set to non-zero when userspace countdown mode active */ 90 static bool do_countdown; 91 static unsigned int countdown_reset; 92 static unsigned int per_cpu_countdown[NR_CPUS]; 93 94 static cpumask_t irq_enabled_cpus; 95 96 #define WD_TIMO 60 /* Default heartbeat = 60 seconds */ 97 98 #define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull) 99 100 static int heartbeat = WD_TIMO; 101 module_param(heartbeat, int, 0444); 102 MODULE_PARM_DESC(heartbeat, 103 "Watchdog heartbeat in seconds. (0 < heartbeat, default=" 104 __MODULE_STRING(WD_TIMO) ")"); 105 106 static bool nowayout = WATCHDOG_NOWAYOUT; 107 module_param(nowayout, bool, 0444); 108 MODULE_PARM_DESC(nowayout, 109 "Watchdog cannot be stopped once started (default=" 110 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 111 112 static int disable; 113 module_param(disable, int, 0444); 114 MODULE_PARM_DESC(disable, 115 "Disable the watchdog entirely (default=0)"); 116 117 static struct cvmx_boot_vector_element *octeon_wdt_bootvector; 118 119 void octeon_wdt_nmi_stage2(void); 120 121 static int cpu2core(int cpu) 122 { 123 #ifdef CONFIG_SMP 124 return cpu_logical_map(cpu) & 0x3f; 125 #else 126 return cvmx_get_core_num(); 127 #endif 128 } 129 130 /** 131 * Poke the watchdog when an interrupt is received 132 * 133 * @cpl: 134 * @dev_id: 135 * 136 * Returns 137 */ 138 static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) 139 { 140 int cpu = raw_smp_processor_id(); 141 unsigned int core = cpu2core(cpu); 142 int node = cpu_to_node(cpu); 143 144 if (do_countdown) { 145 if (per_cpu_countdown[cpu] > 0) { 146 /* We're alive, poke the watchdog */ 147 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 148 per_cpu_countdown[cpu]--; 149 } else { 150 /* Bad news, you are about to reboot. */ 151 disable_irq_nosync(cpl); 152 cpumask_clear_cpu(cpu, &irq_enabled_cpus); 153 } 154 } else { 155 /* Not open, just ping away... */ 156 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 157 } 158 return IRQ_HANDLED; 159 } 160 161 /* From setup.c */ 162 extern int prom_putchar(char c); 163 164 /** 165 * Write a string to the uart 166 * 167 * @str: String to write 168 */ 169 static void octeon_wdt_write_string(const char *str) 170 { 171 /* Just loop writing one byte at a time */ 172 while (*str) 173 prom_putchar(*str++); 174 } 175 176 /** 177 * Write a hex number out of the uart 178 * 179 * @value: Number to display 180 * @digits: Number of digits to print (1 to 16) 181 */ 182 static void octeon_wdt_write_hex(u64 value, int digits) 183 { 184 int d; 185 int v; 186 187 for (d = 0; d < digits; d++) { 188 v = (value >> ((digits - d - 1) * 4)) & 0xf; 189 if (v >= 10) 190 prom_putchar('a' + v - 10); 191 else 192 prom_putchar('0' + v); 193 } 194 } 195 196 static const char reg_name[][3] = { 197 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 198 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 199 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 200 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 201 }; 202 203 /** 204 * NMI stage 3 handler. NMIs are handled in the following manner: 205 * 1) The first NMI handler enables CVMSEG and transfers from 206 * the bootbus region into normal memory. It is careful to not 207 * destroy any registers. 208 * 2) The second stage handler uses CVMSEG to save the registers 209 * and create a stack for C code. It then calls the third level 210 * handler with one argument, a pointer to the register values. 211 * 3) The third, and final, level handler is the following C 212 * function that prints out some useful infomration. 213 * 214 * @reg: Pointer to register state before the NMI 215 */ 216 void octeon_wdt_nmi_stage3(u64 reg[32]) 217 { 218 u64 i; 219 220 unsigned int coreid = cvmx_get_core_num(); 221 /* 222 * Save status and cause early to get them before any changes 223 * might happen. 224 */ 225 u64 cp0_cause = read_c0_cause(); 226 u64 cp0_status = read_c0_status(); 227 u64 cp0_error_epc = read_c0_errorepc(); 228 u64 cp0_epc = read_c0_epc(); 229 230 /* Delay so output from all cores output is not jumbled together. */ 231 udelay(85000 * coreid); 232 233 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); 234 octeon_wdt_write_hex(coreid, 2); 235 octeon_wdt_write_string(" ***\r\n"); 236 for (i = 0; i < 32; i++) { 237 octeon_wdt_write_string("\t"); 238 octeon_wdt_write_string(reg_name[i]); 239 octeon_wdt_write_string("\t0x"); 240 octeon_wdt_write_hex(reg[i], 16); 241 if (i & 1) 242 octeon_wdt_write_string("\r\n"); 243 } 244 octeon_wdt_write_string("\terr_epc\t0x"); 245 octeon_wdt_write_hex(cp0_error_epc, 16); 246 247 octeon_wdt_write_string("\tepc\t0x"); 248 octeon_wdt_write_hex(cp0_epc, 16); 249 octeon_wdt_write_string("\r\n"); 250 251 octeon_wdt_write_string("\tstatus\t0x"); 252 octeon_wdt_write_hex(cp0_status, 16); 253 octeon_wdt_write_string("\tcause\t0x"); 254 octeon_wdt_write_hex(cp0_cause, 16); 255 octeon_wdt_write_string("\r\n"); 256 257 /* The CIU register is different for each Octeon model. */ 258 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 259 octeon_wdt_write_string("\tsrc_wd\t0x"); 260 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16); 261 octeon_wdt_write_string("\ten_wd\t0x"); 262 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16); 263 octeon_wdt_write_string("\r\n"); 264 octeon_wdt_write_string("\tsrc_rml\t0x"); 265 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16); 266 octeon_wdt_write_string("\ten_rml\t0x"); 267 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16); 268 octeon_wdt_write_string("\r\n"); 269 octeon_wdt_write_string("\tsum\t0x"); 270 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16); 271 octeon_wdt_write_string("\r\n"); 272 } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) { 273 octeon_wdt_write_string("\tsum0\t0x"); 274 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); 275 octeon_wdt_write_string("\ten0\t0x"); 276 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); 277 octeon_wdt_write_string("\r\n"); 278 } 279 280 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); 281 282 /* 283 * G-30204: We must trigger a soft reset before watchdog 284 * does an incomplete job of doing it. 285 */ 286 if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) { 287 u64 scr; 288 unsigned int node = cvmx_get_node_num(); 289 unsigned int lcore = cvmx_get_local_core_num(); 290 union cvmx_ciu_wdogx ciu_wdog; 291 292 /* 293 * Wait for other cores to print out information, but 294 * not too long. Do the soft reset before watchdog 295 * can trigger it. 296 */ 297 do { 298 ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore)); 299 } while (ciu_wdog.s.cnt > 0x10000); 300 301 scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0)); 302 scr |= 1 << 11; /* Indicate watchdog in bit 11 */ 303 cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr); 304 cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1); 305 } 306 } 307 308 static int octeon_wdt_cpu_to_irq(int cpu) 309 { 310 unsigned int coreid; 311 int node; 312 int irq; 313 314 coreid = cpu2core(cpu); 315 node = cpu_to_node(cpu); 316 317 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 318 struct irq_domain *domain; 319 int hwirq; 320 321 domain = octeon_irq_get_block_domain(node, 322 WD_BLOCK_NUMBER); 323 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid; 324 irq = irq_find_mapping(domain, hwirq); 325 } else { 326 irq = OCTEON_IRQ_WDOG0 + coreid; 327 } 328 return irq; 329 } 330 331 static int octeon_wdt_cpu_pre_down(unsigned int cpu) 332 { 333 unsigned int core; 334 int node; 335 union cvmx_ciu_wdogx ciu_wdog; 336 337 core = cpu2core(cpu); 338 339 node = cpu_to_node(cpu); 340 341 /* Poke the watchdog to clear out its state */ 342 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 343 344 /* Disable the hardware. */ 345 ciu_wdog.u64 = 0; 346 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 347 348 free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq); 349 return 0; 350 } 351 352 static int octeon_wdt_cpu_online(unsigned int cpu) 353 { 354 unsigned int core; 355 unsigned int irq; 356 union cvmx_ciu_wdogx ciu_wdog; 357 int node; 358 struct irq_domain *domain; 359 int hwirq; 360 361 core = cpu2core(cpu); 362 node = cpu_to_node(cpu); 363 364 octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2; 365 366 /* Disable it before doing anything with the interrupts. */ 367 ciu_wdog.u64 = 0; 368 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 369 370 per_cpu_countdown[cpu] = countdown_reset; 371 372 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 373 /* Must get the domain for the watchdog block */ 374 domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER); 375 376 /* Get a irq for the wd intsn (hardware interrupt) */ 377 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core; 378 irq = irq_create_mapping(domain, hwirq); 379 irqd_set_trigger_type(irq_get_irq_data(irq), 380 IRQ_TYPE_EDGE_RISING); 381 } else 382 irq = OCTEON_IRQ_WDOG0 + core; 383 384 if (request_irq(irq, octeon_wdt_poke_irq, 385 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) 386 panic("octeon_wdt: Couldn't obtain irq %d", irq); 387 388 /* Must set the irq affinity here */ 389 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 390 cpumask_t mask; 391 392 cpumask_clear(&mask); 393 cpumask_set_cpu(cpu, &mask); 394 irq_set_affinity(irq, &mask); 395 } 396 397 cpumask_set_cpu(cpu, &irq_enabled_cpus); 398 399 /* Poke the watchdog to clear out its state */ 400 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 401 402 /* Finally enable the watchdog now that all handlers are installed */ 403 ciu_wdog.u64 = 0; 404 ciu_wdog.s.len = timeout_cnt; 405 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 406 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 407 408 return 0; 409 } 410 411 static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog) 412 { 413 int cpu; 414 int coreid; 415 int node; 416 417 if (disable) 418 return 0; 419 420 for_each_online_cpu(cpu) { 421 coreid = cpu2core(cpu); 422 node = cpu_to_node(cpu); 423 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 424 per_cpu_countdown[cpu] = countdown_reset; 425 if ((countdown_reset || !do_countdown) && 426 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { 427 /* We have to enable the irq */ 428 enable_irq(octeon_wdt_cpu_to_irq(cpu)); 429 cpumask_set_cpu(cpu, &irq_enabled_cpus); 430 } 431 } 432 return 0; 433 } 434 435 static void octeon_wdt_calc_parameters(int t) 436 { 437 unsigned int periods; 438 439 timeout_sec = max_timeout_sec; 440 441 442 /* 443 * Find the largest interrupt period, that can evenly divide 444 * the requested heartbeat time. 445 */ 446 while ((t % timeout_sec) != 0) 447 timeout_sec--; 448 449 periods = t / timeout_sec; 450 451 /* 452 * The last two periods are after the irq is disabled, and 453 * then to the nmi, so we subtract them off. 454 */ 455 456 countdown_reset = periods > 2 ? periods - 2 : 0; 457 heartbeat = t; 458 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8; 459 } 460 461 static int octeon_wdt_set_timeout(struct watchdog_device *wdog, 462 unsigned int t) 463 { 464 int cpu; 465 int coreid; 466 union cvmx_ciu_wdogx ciu_wdog; 467 int node; 468 469 if (t <= 0) 470 return -1; 471 472 octeon_wdt_calc_parameters(t); 473 474 if (disable) 475 return 0; 476 477 for_each_online_cpu(cpu) { 478 coreid = cpu2core(cpu); 479 node = cpu_to_node(cpu); 480 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 481 ciu_wdog.u64 = 0; 482 ciu_wdog.s.len = timeout_cnt; 483 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 484 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); 485 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 486 } 487 octeon_wdt_ping(wdog); /* Get the irqs back on. */ 488 return 0; 489 } 490 491 static int octeon_wdt_start(struct watchdog_device *wdog) 492 { 493 octeon_wdt_ping(wdog); 494 do_countdown = 1; 495 return 0; 496 } 497 498 static int octeon_wdt_stop(struct watchdog_device *wdog) 499 { 500 do_countdown = 0; 501 octeon_wdt_ping(wdog); 502 return 0; 503 } 504 505 static const struct watchdog_info octeon_wdt_info = { 506 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, 507 .identity = "OCTEON", 508 }; 509 510 static const struct watchdog_ops octeon_wdt_ops = { 511 .owner = THIS_MODULE, 512 .start = octeon_wdt_start, 513 .stop = octeon_wdt_stop, 514 .ping = octeon_wdt_ping, 515 .set_timeout = octeon_wdt_set_timeout, 516 }; 517 518 static struct watchdog_device octeon_wdt = { 519 .info = &octeon_wdt_info, 520 .ops = &octeon_wdt_ops, 521 }; 522 523 static enum cpuhp_state octeon_wdt_online; 524 /** 525 * Module/ driver initialization. 526 * 527 * Returns Zero on success 528 */ 529 static int __init octeon_wdt_init(void) 530 { 531 int ret; 532 533 octeon_wdt_bootvector = cvmx_boot_vector_get(); 534 if (!octeon_wdt_bootvector) { 535 pr_err("Error: Cannot allocate boot vector.\n"); 536 return -ENOMEM; 537 } 538 539 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 540 divisor = 0x200; 541 else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 542 divisor = 0x400; 543 else 544 divisor = 0x100; 545 546 /* 547 * Watchdog time expiration length = The 16 bits of LEN 548 * represent the most significant bits of a 24 bit decrementer 549 * that decrements every divisor cycle. 550 * 551 * Try for a timeout of 5 sec, if that fails a smaller number 552 * of even seconds, 553 */ 554 max_timeout_sec = 6; 555 do { 556 max_timeout_sec--; 557 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8; 558 } while (timeout_cnt > 65535); 559 560 BUG_ON(timeout_cnt == 0); 561 562 octeon_wdt_calc_parameters(heartbeat); 563 564 pr_info("Initial granularity %d Sec\n", timeout_sec); 565 566 octeon_wdt.timeout = timeout_sec; 567 octeon_wdt.max_timeout = UINT_MAX; 568 569 watchdog_set_nowayout(&octeon_wdt, nowayout); 570 571 ret = watchdog_register_device(&octeon_wdt); 572 if (ret) { 573 pr_err("watchdog_register_device() failed: %d\n", ret); 574 return ret; 575 } 576 577 if (disable) { 578 pr_notice("disabled\n"); 579 return 0; 580 } 581 582 cpumask_clear(&irq_enabled_cpus); 583 584 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online", 585 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down); 586 if (ret < 0) 587 goto err; 588 octeon_wdt_online = ret; 589 return 0; 590 err: 591 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 592 watchdog_unregister_device(&octeon_wdt); 593 return ret; 594 } 595 596 /** 597 * Module / driver shutdown 598 */ 599 static void __exit octeon_wdt_cleanup(void) 600 { 601 watchdog_unregister_device(&octeon_wdt); 602 603 if (disable) 604 return; 605 606 cpuhp_remove_state(octeon_wdt_online); 607 608 /* 609 * Disable the boot-bus memory, the code it points to is soon 610 * to go missing. 611 */ 612 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 613 } 614 615 MODULE_LICENSE("GPL"); 616 MODULE_AUTHOR("Cavium Inc. <support@cavium.com>"); 617 MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver."); 618 module_init(octeon_wdt_init); 619 module_exit(octeon_wdt_cleanup); 620