1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Mediatek Watchdog Driver 4 * 5 * Copyright (C) 2014 Matthias Brugger 6 * 7 * Matthias Brugger <matthias.bgg@gmail.com> 8 * 9 * Based on sunxi_wdt.c 10 */ 11 12 #include <dt-bindings/reset/mt2712-resets.h> 13 #include <dt-bindings/reset/mediatek,mt6795-resets.h> 14 #include <dt-bindings/reset/mt7986-resets.h> 15 #include <dt-bindings/reset/mt8183-resets.h> 16 #include <dt-bindings/reset/mt8186-resets.h> 17 #include <dt-bindings/reset/mt8188-resets.h> 18 #include <dt-bindings/reset/mt8192-resets.h> 19 #include <dt-bindings/reset/mt8195-resets.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/moduleparam.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/platform_device.h> 30 #include <linux/reset-controller.h> 31 #include <linux/types.h> 32 #include <linux/watchdog.h> 33 #include <linux/interrupt.h> 34 35 #define WDT_MAX_TIMEOUT 31 36 #define WDT_MIN_TIMEOUT 2 37 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5) 38 39 #define WDT_LENGTH 0x04 40 #define WDT_LENGTH_KEY 0x8 41 42 #define WDT_RST 0x08 43 #define WDT_RST_RELOAD 0x1971 44 45 #define WDT_MODE 0x00 46 #define WDT_MODE_EN (1 << 0) 47 #define WDT_MODE_EXT_POL_LOW (0 << 1) 48 #define WDT_MODE_EXT_POL_HIGH (1 << 1) 49 #define WDT_MODE_EXRST_EN (1 << 2) 50 #define WDT_MODE_IRQ_EN (1 << 3) 51 #define WDT_MODE_AUTO_START (1 << 4) 52 #define WDT_MODE_DUAL_EN (1 << 6) 53 #define WDT_MODE_CNT_SEL (1 << 8) 54 #define WDT_MODE_KEY 0x22000000 55 56 #define WDT_SWRST 0x14 57 #define WDT_SWRST_KEY 0x1209 58 59 #define WDT_SWSYSRST 0x18U 60 #define WDT_SWSYS_RST_KEY 0x88000000 61 62 #define DRV_NAME "mtk-wdt" 63 #define DRV_VERSION "1.0" 64 65 static bool nowayout = WATCHDOG_NOWAYOUT; 66 static unsigned int timeout; 67 68 struct mtk_wdt_dev { 69 struct watchdog_device wdt_dev; 70 void __iomem *wdt_base; 71 spinlock_t lock; /* protects WDT_SWSYSRST reg */ 72 struct reset_controller_dev rcdev; 73 bool disable_wdt_extrst; 74 bool reset_by_toprgu; 75 }; 76 77 struct mtk_wdt_data { 78 int toprgu_sw_rst_num; 79 }; 80 81 static const struct mtk_wdt_data mt2712_data = { 82 .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, 83 }; 84 85 static const struct mtk_wdt_data mt6795_data = { 86 .toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM, 87 }; 88 89 static const struct mtk_wdt_data mt7986_data = { 90 .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, 91 }; 92 93 static const struct mtk_wdt_data mt8183_data = { 94 .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, 95 }; 96 97 static const struct mtk_wdt_data mt8186_data = { 98 .toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM, 99 }; 100 101 static const struct mtk_wdt_data mt8188_data = { 102 .toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM, 103 }; 104 105 static const struct mtk_wdt_data mt8192_data = { 106 .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, 107 }; 108 109 static const struct mtk_wdt_data mt8195_data = { 110 .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, 111 }; 112 113 static int toprgu_reset_update(struct reset_controller_dev *rcdev, 114 unsigned long id, bool assert) 115 { 116 unsigned int tmp; 117 unsigned long flags; 118 struct mtk_wdt_dev *data = 119 container_of(rcdev, struct mtk_wdt_dev, rcdev); 120 121 spin_lock_irqsave(&data->lock, flags); 122 123 tmp = readl(data->wdt_base + WDT_SWSYSRST); 124 if (assert) 125 tmp |= BIT(id); 126 else 127 tmp &= ~BIT(id); 128 tmp |= WDT_SWSYS_RST_KEY; 129 writel(tmp, data->wdt_base + WDT_SWSYSRST); 130 131 spin_unlock_irqrestore(&data->lock, flags); 132 133 return 0; 134 } 135 136 static int toprgu_reset_assert(struct reset_controller_dev *rcdev, 137 unsigned long id) 138 { 139 return toprgu_reset_update(rcdev, id, true); 140 } 141 142 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, 143 unsigned long id) 144 { 145 return toprgu_reset_update(rcdev, id, false); 146 } 147 148 static int toprgu_reset(struct reset_controller_dev *rcdev, 149 unsigned long id) 150 { 151 int ret; 152 153 ret = toprgu_reset_assert(rcdev, id); 154 if (ret) 155 return ret; 156 157 return toprgu_reset_deassert(rcdev, id); 158 } 159 160 static const struct reset_control_ops toprgu_reset_ops = { 161 .assert = toprgu_reset_assert, 162 .deassert = toprgu_reset_deassert, 163 .reset = toprgu_reset, 164 }; 165 166 static int toprgu_register_reset_controller(struct platform_device *pdev, 167 int rst_num) 168 { 169 int ret; 170 struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); 171 172 spin_lock_init(&mtk_wdt->lock); 173 174 mtk_wdt->rcdev.owner = THIS_MODULE; 175 mtk_wdt->rcdev.nr_resets = rst_num; 176 mtk_wdt->rcdev.ops = &toprgu_reset_ops; 177 mtk_wdt->rcdev.of_node = pdev->dev.of_node; 178 ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); 179 if (ret != 0) 180 dev_err(&pdev->dev, 181 "couldn't register wdt reset controller: %d\n", ret); 182 return ret; 183 } 184 185 static int mtk_wdt_restart(struct watchdog_device *wdt_dev, 186 unsigned long action, void *data) 187 { 188 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 189 void __iomem *wdt_base; 190 191 wdt_base = mtk_wdt->wdt_base; 192 193 while (1) { 194 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST); 195 mdelay(5); 196 } 197 198 return 0; 199 } 200 201 static int mtk_wdt_ping(struct watchdog_device *wdt_dev) 202 { 203 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 204 void __iomem *wdt_base = mtk_wdt->wdt_base; 205 206 iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST); 207 208 return 0; 209 } 210 211 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev, 212 unsigned int timeout) 213 { 214 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 215 void __iomem *wdt_base = mtk_wdt->wdt_base; 216 u32 reg; 217 218 wdt_dev->timeout = timeout; 219 /* 220 * In dual mode, irq will be triggered at timeout / 2 221 * the real timeout occurs at timeout 222 */ 223 if (wdt_dev->pretimeout) 224 wdt_dev->pretimeout = timeout / 2; 225 226 /* 227 * One bit is the value of 512 ticks 228 * The clock has 32 KHz 229 */ 230 reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6) 231 | WDT_LENGTH_KEY; 232 iowrite32(reg, wdt_base + WDT_LENGTH); 233 234 mtk_wdt_ping(wdt_dev); 235 236 return 0; 237 } 238 239 static void mtk_wdt_init(struct watchdog_device *wdt_dev) 240 { 241 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 242 void __iomem *wdt_base; 243 244 wdt_base = mtk_wdt->wdt_base; 245 246 if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) { 247 set_bit(WDOG_HW_RUNNING, &wdt_dev->status); 248 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 249 } 250 } 251 252 static int mtk_wdt_stop(struct watchdog_device *wdt_dev) 253 { 254 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 255 void __iomem *wdt_base = mtk_wdt->wdt_base; 256 u32 reg; 257 258 reg = readl(wdt_base + WDT_MODE); 259 reg &= ~WDT_MODE_EN; 260 reg |= WDT_MODE_KEY; 261 iowrite32(reg, wdt_base + WDT_MODE); 262 263 return 0; 264 } 265 266 static int mtk_wdt_start(struct watchdog_device *wdt_dev) 267 { 268 u32 reg; 269 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 270 void __iomem *wdt_base = mtk_wdt->wdt_base; 271 int ret; 272 273 ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 274 if (ret < 0) 275 return ret; 276 277 reg = ioread32(wdt_base + WDT_MODE); 278 if (wdt_dev->pretimeout) 279 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 280 else 281 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 282 if (mtk_wdt->disable_wdt_extrst) 283 reg &= ~WDT_MODE_EXRST_EN; 284 if (mtk_wdt->reset_by_toprgu) 285 reg |= WDT_MODE_CNT_SEL; 286 reg |= (WDT_MODE_EN | WDT_MODE_KEY); 287 iowrite32(reg, wdt_base + WDT_MODE); 288 289 return 0; 290 } 291 292 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd, 293 unsigned int timeout) 294 { 295 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd); 296 void __iomem *wdt_base = mtk_wdt->wdt_base; 297 u32 reg = ioread32(wdt_base + WDT_MODE); 298 299 if (timeout && !wdd->pretimeout) { 300 wdd->pretimeout = wdd->timeout / 2; 301 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 302 } else if (!timeout && wdd->pretimeout) { 303 wdd->pretimeout = 0; 304 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 305 } else { 306 return 0; 307 } 308 309 reg |= WDT_MODE_KEY; 310 iowrite32(reg, wdt_base + WDT_MODE); 311 312 return mtk_wdt_set_timeout(wdd, wdd->timeout); 313 } 314 315 static irqreturn_t mtk_wdt_isr(int irq, void *arg) 316 { 317 struct watchdog_device *wdd = arg; 318 319 watchdog_notify_pretimeout(wdd); 320 321 return IRQ_HANDLED; 322 } 323 324 static const struct watchdog_info mtk_wdt_info = { 325 .identity = DRV_NAME, 326 .options = WDIOF_SETTIMEOUT | 327 WDIOF_KEEPALIVEPING | 328 WDIOF_MAGICCLOSE, 329 }; 330 331 static const struct watchdog_info mtk_wdt_pt_info = { 332 .identity = DRV_NAME, 333 .options = WDIOF_SETTIMEOUT | 334 WDIOF_PRETIMEOUT | 335 WDIOF_KEEPALIVEPING | 336 WDIOF_MAGICCLOSE, 337 }; 338 339 static const struct watchdog_ops mtk_wdt_ops = { 340 .owner = THIS_MODULE, 341 .start = mtk_wdt_start, 342 .stop = mtk_wdt_stop, 343 .ping = mtk_wdt_ping, 344 .set_timeout = mtk_wdt_set_timeout, 345 .set_pretimeout = mtk_wdt_set_pretimeout, 346 .restart = mtk_wdt_restart, 347 }; 348 349 static int mtk_wdt_probe(struct platform_device *pdev) 350 { 351 struct device *dev = &pdev->dev; 352 struct mtk_wdt_dev *mtk_wdt; 353 const struct mtk_wdt_data *wdt_data; 354 int err, irq; 355 356 mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); 357 if (!mtk_wdt) 358 return -ENOMEM; 359 360 platform_set_drvdata(pdev, mtk_wdt); 361 362 mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0); 363 if (IS_ERR(mtk_wdt->wdt_base)) 364 return PTR_ERR(mtk_wdt->wdt_base); 365 366 irq = platform_get_irq_optional(pdev, 0); 367 if (irq > 0) { 368 err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark", 369 &mtk_wdt->wdt_dev); 370 if (err) 371 return err; 372 373 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info; 374 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2; 375 } else { 376 if (irq == -EPROBE_DEFER) 377 return -EPROBE_DEFER; 378 379 mtk_wdt->wdt_dev.info = &mtk_wdt_info; 380 } 381 382 mtk_wdt->wdt_dev.ops = &mtk_wdt_ops; 383 mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT; 384 mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000; 385 mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT; 386 mtk_wdt->wdt_dev.parent = dev; 387 388 watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev); 389 watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout); 390 watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128); 391 392 watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt); 393 394 mtk_wdt_init(&mtk_wdt->wdt_dev); 395 396 watchdog_stop_on_reboot(&mtk_wdt->wdt_dev); 397 err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev); 398 if (unlikely(err)) 399 return err; 400 401 dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", 402 mtk_wdt->wdt_dev.timeout, nowayout); 403 404 wdt_data = of_device_get_match_data(dev); 405 if (wdt_data) { 406 err = toprgu_register_reset_controller(pdev, 407 wdt_data->toprgu_sw_rst_num); 408 if (err) 409 return err; 410 } 411 412 mtk_wdt->disable_wdt_extrst = 413 of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); 414 415 mtk_wdt->reset_by_toprgu = 416 of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu"); 417 418 return 0; 419 } 420 421 static int mtk_wdt_suspend(struct device *dev) 422 { 423 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 424 425 if (watchdog_active(&mtk_wdt->wdt_dev)) 426 mtk_wdt_stop(&mtk_wdt->wdt_dev); 427 428 return 0; 429 } 430 431 static int mtk_wdt_resume(struct device *dev) 432 { 433 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 434 435 if (watchdog_active(&mtk_wdt->wdt_dev)) { 436 mtk_wdt_start(&mtk_wdt->wdt_dev); 437 mtk_wdt_ping(&mtk_wdt->wdt_dev); 438 } 439 440 return 0; 441 } 442 443 static const struct of_device_id mtk_wdt_dt_ids[] = { 444 { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, 445 { .compatible = "mediatek,mt6589-wdt" }, 446 { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, 447 { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, 448 { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, 449 { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, 450 { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data }, 451 { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, 452 { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, 453 { /* sentinel */ } 454 }; 455 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); 456 457 static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops, 458 mtk_wdt_suspend, mtk_wdt_resume); 459 460 static struct platform_driver mtk_wdt_driver = { 461 .probe = mtk_wdt_probe, 462 .driver = { 463 .name = DRV_NAME, 464 .pm = pm_sleep_ptr(&mtk_wdt_pm_ops), 465 .of_match_table = mtk_wdt_dt_ids, 466 }, 467 }; 468 469 module_platform_driver(mtk_wdt_driver); 470 471 module_param(timeout, uint, 0); 472 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds"); 473 474 module_param(nowayout, bool, 0); 475 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 476 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 477 478 MODULE_LICENSE("GPL"); 479 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>"); 480 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver"); 481 MODULE_VERSION(DRV_VERSION); 482