xref: /linux/drivers/watchdog/meson_gxbb_wdt.c (revision 320fefa9e2edc67011e235ea1d50f0d00ddfe004)
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (c) 2016 BayLibre, SAS.
4  * Author: Neil Armstrong <narmstrong@baylibre.com>
5  *
6  */
7 #include <linux/clk.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
14 #include <linux/types.h>
15 #include <linux/watchdog.h>
16 
17 #define DEFAULT_TIMEOUT	30	/* seconds */
18 
19 #define GXBB_WDT_CTRL_REG			0x0
20 #define GXBB_WDT_TCNT_REG			0x8
21 #define GXBB_WDT_RSET_REG			0xc
22 
23 #define GXBB_WDT_CTRL_CLKDIV_EN			BIT(25)
24 #define GXBB_WDT_CTRL_CLK_EN			BIT(24)
25 #define GXBB_WDT_CTRL_EE_RESET			BIT(21)
26 #define GXBB_WDT_CTRL_EN			BIT(18)
27 #define GXBB_WDT_CTRL_DIV_MASK			(BIT(18) - 1)
28 
29 #define GXBB_WDT_TCNT_SETUP_MASK		(BIT(16) - 1)
30 #define GXBB_WDT_TCNT_CNT_SHIFT			16
31 
32 static bool nowayout = WATCHDOG_NOWAYOUT;
33 module_param(nowayout, bool, 0);
34 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started default="
35 		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
36 
37 static unsigned int timeout;
38 module_param(timeout, uint, 0);
39 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds="
40 		 __MODULE_STRING(DEFAULT_TIMEOUT) ")");
41 
42 struct meson_gxbb_wdt {
43 	void __iomem *reg_base;
44 	struct watchdog_device wdt_dev;
45 	struct clk *clk;
46 };
47 
48 static int meson_gxbb_wdt_start(struct watchdog_device *wdt_dev)
49 {
50 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
51 
52 	writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
53 	       data->reg_base + GXBB_WDT_CTRL_REG);
54 
55 	return 0;
56 }
57 
58 static int meson_gxbb_wdt_stop(struct watchdog_device *wdt_dev)
59 {
60 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
61 
62 	writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
63 	       data->reg_base + GXBB_WDT_CTRL_REG);
64 
65 	return 0;
66 }
67 
68 static int meson_gxbb_wdt_ping(struct watchdog_device *wdt_dev)
69 {
70 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
71 
72 	writel(0, data->reg_base + GXBB_WDT_RSET_REG);
73 
74 	return 0;
75 }
76 
77 static int meson_gxbb_wdt_set_timeout(struct watchdog_device *wdt_dev,
78 				      unsigned int timeout)
79 {
80 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
81 	unsigned long tcnt = timeout * 1000;
82 
83 	if (tcnt > GXBB_WDT_TCNT_SETUP_MASK)
84 		tcnt = GXBB_WDT_TCNT_SETUP_MASK;
85 
86 	wdt_dev->timeout = timeout;
87 
88 	meson_gxbb_wdt_ping(wdt_dev);
89 
90 	writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG);
91 
92 	return 0;
93 }
94 
95 static unsigned int meson_gxbb_wdt_get_timeleft(struct watchdog_device *wdt_dev)
96 {
97 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
98 	unsigned long reg;
99 
100 	reg = readl(data->reg_base + GXBB_WDT_TCNT_REG);
101 
102 	return ((reg & GXBB_WDT_TCNT_SETUP_MASK) -
103 		(reg >> GXBB_WDT_TCNT_CNT_SHIFT)) / 1000;
104 }
105 
106 static const struct watchdog_ops meson_gxbb_wdt_ops = {
107 	.start = meson_gxbb_wdt_start,
108 	.stop = meson_gxbb_wdt_stop,
109 	.ping = meson_gxbb_wdt_ping,
110 	.set_timeout = meson_gxbb_wdt_set_timeout,
111 	.get_timeleft = meson_gxbb_wdt_get_timeleft,
112 };
113 
114 static const struct watchdog_info meson_gxbb_wdt_info = {
115 	.identity = "Meson GXBB Watchdog",
116 	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
117 };
118 
119 static int __maybe_unused meson_gxbb_wdt_resume(struct device *dev)
120 {
121 	struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
122 
123 	if (watchdog_active(&data->wdt_dev))
124 		meson_gxbb_wdt_start(&data->wdt_dev);
125 
126 	return 0;
127 }
128 
129 static int __maybe_unused meson_gxbb_wdt_suspend(struct device *dev)
130 {
131 	struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
132 
133 	if (watchdog_active(&data->wdt_dev))
134 		meson_gxbb_wdt_stop(&data->wdt_dev);
135 
136 	return 0;
137 }
138 
139 static const struct dev_pm_ops meson_gxbb_wdt_pm_ops = {
140 	SET_SYSTEM_SLEEP_PM_OPS(meson_gxbb_wdt_suspend, meson_gxbb_wdt_resume)
141 };
142 
143 static const struct of_device_id meson_gxbb_wdt_dt_ids[] = {
144 	 { .compatible = "amlogic,meson-gxbb-wdt", },
145 	 { /* sentinel */ },
146 };
147 MODULE_DEVICE_TABLE(of, meson_gxbb_wdt_dt_ids);
148 
149 static void meson_clk_disable_unprepare(void *data)
150 {
151 	clk_disable_unprepare(data);
152 }
153 
154 static int meson_gxbb_wdt_probe(struct platform_device *pdev)
155 {
156 	struct device *dev = &pdev->dev;
157 	struct meson_gxbb_wdt *data;
158 	int ret;
159 	u32 ctrl_reg;
160 
161 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
162 	if (!data)
163 		return -ENOMEM;
164 
165 	data->reg_base = devm_platform_ioremap_resource(pdev, 0);
166 	if (IS_ERR(data->reg_base))
167 		return PTR_ERR(data->reg_base);
168 
169 	data->clk = devm_clk_get(dev, NULL);
170 	if (IS_ERR(data->clk))
171 		return PTR_ERR(data->clk);
172 
173 	ret = clk_prepare_enable(data->clk);
174 	if (ret)
175 		return ret;
176 	ret = devm_add_action_or_reset(dev, meson_clk_disable_unprepare,
177 				       data->clk);
178 	if (ret)
179 		return ret;
180 
181 	platform_set_drvdata(pdev, data);
182 
183 	data->wdt_dev.parent = dev;
184 	data->wdt_dev.info = &meson_gxbb_wdt_info;
185 	data->wdt_dev.ops = &meson_gxbb_wdt_ops;
186 	data->wdt_dev.max_hw_heartbeat_ms = GXBB_WDT_TCNT_SETUP_MASK;
187 	data->wdt_dev.min_timeout = 1;
188 	data->wdt_dev.timeout = DEFAULT_TIMEOUT;
189 	watchdog_init_timeout(&data->wdt_dev, timeout, dev);
190 	watchdog_set_nowayout(&data->wdt_dev, nowayout);
191 	watchdog_set_drvdata(&data->wdt_dev, data);
192 
193 	ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) &
194 				GXBB_WDT_CTRL_EN;
195 
196 	if (ctrl_reg) {
197 		/* Watchdog is running - keep it running but extend timeout
198 		 * to the maximum while setting the timebase
199 		 */
200 		set_bit(WDOG_HW_RUNNING, &data->wdt_dev.status);
201 		meson_gxbb_wdt_set_timeout(&data->wdt_dev,
202 				GXBB_WDT_TCNT_SETUP_MASK / 1000);
203 	}
204 
205 	/* Setup with 1ms timebase */
206 	ctrl_reg |= ((clk_get_rate(data->clk) / 1000) &
207 			GXBB_WDT_CTRL_DIV_MASK) |
208 			GXBB_WDT_CTRL_EE_RESET |
209 			GXBB_WDT_CTRL_CLK_EN |
210 			GXBB_WDT_CTRL_CLKDIV_EN;
211 
212 	writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG);
213 	meson_gxbb_wdt_set_timeout(&data->wdt_dev, data->wdt_dev.timeout);
214 
215 	return devm_watchdog_register_device(dev, &data->wdt_dev);
216 }
217 
218 static struct platform_driver meson_gxbb_wdt_driver = {
219 	.probe	= meson_gxbb_wdt_probe,
220 	.driver = {
221 		.name = "meson-gxbb-wdt",
222 		.pm = &meson_gxbb_wdt_pm_ops,
223 		.of_match_table	= meson_gxbb_wdt_dt_ids,
224 	},
225 };
226 
227 module_platform_driver(meson_gxbb_wdt_driver);
228 
229 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
230 MODULE_DESCRIPTION("Amlogic Meson GXBB Watchdog timer driver");
231 MODULE_LICENSE("Dual BSD/GPL");
232