1 /* 2 * Imagination Technologies PowerDown Controller Watchdog Timer. 3 * 4 * Copyright (c) 2014 Imagination Technologies Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione 11 * 2012 Henrik Nordstrom 12 * 13 * Notes 14 * ----- 15 * The timeout value is rounded to the next power of two clock cycles. 16 * This is configured using the PDC_WDT_CONFIG register, according to this 17 * formula: 18 * 19 * timeout = 2^(delay + 1) clock cycles 20 * 21 * Where 'delay' is the value written in PDC_WDT_CONFIG register. 22 * 23 * Therefore, the hardware only allows to program watchdog timeouts, expressed 24 * as a power of two number of watchdog clock cycles. The current implementation 25 * guarantees that the actual watchdog timeout will be _at least_ the value 26 * programmed in the imgpdg_wdt driver. 27 * 28 * The following table shows how the user-configured timeout relates 29 * to the actual hardware timeout (watchdog clock @ 40000 Hz): 30 * 31 * input timeout | WD_DELAY | actual timeout 32 * ----------------------------------- 33 * 10 | 18 | 13 seconds 34 * 20 | 19 | 26 seconds 35 * 30 | 20 | 52 seconds 36 * 60 | 21 | 104 seconds 37 * 38 * Albeit coarse, this granularity would suffice most watchdog uses. 39 * If the platform allows it, the user should be able to change the watchdog 40 * clock rate and achieve a finer timeout granularity. 41 */ 42 43 #include <linux/clk.h> 44 #include <linux/io.h> 45 #include <linux/log2.h> 46 #include <linux/module.h> 47 #include <linux/platform_device.h> 48 #include <linux/slab.h> 49 #include <linux/watchdog.h> 50 51 /* registers */ 52 #define PDC_WDT_SOFT_RESET 0x00 53 #define PDC_WDT_CONFIG 0x04 54 #define PDC_WDT_CONFIG_ENABLE BIT(31) 55 #define PDC_WDT_CONFIG_DELAY_MASK 0x1f 56 57 #define PDC_WDT_TICKLE1 0x08 58 #define PDC_WDT_TICKLE1_MAGIC 0xabcd1234 59 #define PDC_WDT_TICKLE2 0x0c 60 #define PDC_WDT_TICKLE2_MAGIC 0x4321dcba 61 62 #define PDC_WDT_TICKLE_STATUS_MASK 0x7 63 #define PDC_WDT_TICKLE_STATUS_SHIFT 0 64 #define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */ 65 #define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1 /* Timeout */ 66 #define PDC_WDT_TICKLE_STATUS_TICKLE 0x2 /* Tickled incorrectly */ 67 #define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */ 68 #define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */ 69 70 /* Timeout values are in seconds */ 71 #define PDC_WDT_MIN_TIMEOUT 1 72 #define PDC_WDT_DEF_TIMEOUT 64 73 74 static int heartbeat; 75 module_param(heartbeat, int, 0); 76 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds " 77 "(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")"); 78 79 static bool nowayout = WATCHDOG_NOWAYOUT; 80 module_param(nowayout, bool, 0); 81 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " 82 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 83 84 struct pdc_wdt_dev { 85 struct watchdog_device wdt_dev; 86 struct clk *wdt_clk; 87 struct clk *sys_clk; 88 void __iomem *base; 89 }; 90 91 static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev) 92 { 93 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 94 95 writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1); 96 writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2); 97 98 return 0; 99 } 100 101 static int pdc_wdt_stop(struct watchdog_device *wdt_dev) 102 { 103 unsigned int val; 104 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 105 106 val = readl(wdt->base + PDC_WDT_CONFIG); 107 val &= ~PDC_WDT_CONFIG_ENABLE; 108 writel(val, wdt->base + PDC_WDT_CONFIG); 109 110 /* Must tickle to finish the stop */ 111 pdc_wdt_keepalive(wdt_dev); 112 113 return 0; 114 } 115 116 static void __pdc_wdt_set_timeout(struct pdc_wdt_dev *wdt) 117 { 118 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk); 119 unsigned int val; 120 121 val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK; 122 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; 123 writel(val, wdt->base + PDC_WDT_CONFIG); 124 } 125 126 static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev, 127 unsigned int new_timeout) 128 { 129 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 130 131 wdt->wdt_dev.timeout = new_timeout; 132 133 __pdc_wdt_set_timeout(wdt); 134 135 return 0; 136 } 137 138 /* Start the watchdog timer (delay should already be set) */ 139 static int pdc_wdt_start(struct watchdog_device *wdt_dev) 140 { 141 unsigned int val; 142 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 143 144 __pdc_wdt_set_timeout(wdt); 145 146 val = readl(wdt->base + PDC_WDT_CONFIG); 147 val |= PDC_WDT_CONFIG_ENABLE; 148 writel(val, wdt->base + PDC_WDT_CONFIG); 149 150 return 0; 151 } 152 153 static int pdc_wdt_restart(struct watchdog_device *wdt_dev) 154 { 155 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 156 157 /* Assert SOFT_RESET */ 158 writel(0x1, wdt->base + PDC_WDT_SOFT_RESET); 159 160 return 0; 161 } 162 163 static struct watchdog_info pdc_wdt_info = { 164 .identity = "IMG PDC Watchdog", 165 .options = WDIOF_SETTIMEOUT | 166 WDIOF_KEEPALIVEPING | 167 WDIOF_MAGICCLOSE, 168 }; 169 170 static const struct watchdog_ops pdc_wdt_ops = { 171 .owner = THIS_MODULE, 172 .start = pdc_wdt_start, 173 .stop = pdc_wdt_stop, 174 .ping = pdc_wdt_keepalive, 175 .set_timeout = pdc_wdt_set_timeout, 176 .restart = pdc_wdt_restart, 177 }; 178 179 static int pdc_wdt_probe(struct platform_device *pdev) 180 { 181 u64 div; 182 int ret, val; 183 unsigned long clk_rate; 184 struct resource *res; 185 struct pdc_wdt_dev *pdc_wdt; 186 187 pdc_wdt = devm_kzalloc(&pdev->dev, sizeof(*pdc_wdt), GFP_KERNEL); 188 if (!pdc_wdt) 189 return -ENOMEM; 190 191 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 192 pdc_wdt->base = devm_ioremap_resource(&pdev->dev, res); 193 if (IS_ERR(pdc_wdt->base)) 194 return PTR_ERR(pdc_wdt->base); 195 196 pdc_wdt->sys_clk = devm_clk_get(&pdev->dev, "sys"); 197 if (IS_ERR(pdc_wdt->sys_clk)) { 198 dev_err(&pdev->dev, "failed to get the sys clock\n"); 199 return PTR_ERR(pdc_wdt->sys_clk); 200 } 201 202 pdc_wdt->wdt_clk = devm_clk_get(&pdev->dev, "wdt"); 203 if (IS_ERR(pdc_wdt->wdt_clk)) { 204 dev_err(&pdev->dev, "failed to get the wdt clock\n"); 205 return PTR_ERR(pdc_wdt->wdt_clk); 206 } 207 208 ret = clk_prepare_enable(pdc_wdt->sys_clk); 209 if (ret) { 210 dev_err(&pdev->dev, "could not prepare or enable sys clock\n"); 211 return ret; 212 } 213 214 ret = clk_prepare_enable(pdc_wdt->wdt_clk); 215 if (ret) { 216 dev_err(&pdev->dev, "could not prepare or enable wdt clock\n"); 217 goto disable_sys_clk; 218 } 219 220 /* We use the clock rate to calculate the max timeout */ 221 clk_rate = clk_get_rate(pdc_wdt->wdt_clk); 222 if (clk_rate == 0) { 223 dev_err(&pdev->dev, "failed to get clock rate\n"); 224 ret = -EINVAL; 225 goto disable_wdt_clk; 226 } 227 228 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) { 229 dev_err(&pdev->dev, "invalid clock rate\n"); 230 ret = -EINVAL; 231 goto disable_wdt_clk; 232 } 233 234 if (order_base_2(clk_rate) == 0) 235 pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1; 236 else 237 pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT; 238 239 pdc_wdt->wdt_dev.info = &pdc_wdt_info; 240 pdc_wdt->wdt_dev.ops = &pdc_wdt_ops; 241 242 div = 1ULL << (PDC_WDT_CONFIG_DELAY_MASK + 1); 243 do_div(div, clk_rate); 244 pdc_wdt->wdt_dev.max_timeout = div; 245 pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT; 246 pdc_wdt->wdt_dev.parent = &pdev->dev; 247 watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt); 248 249 watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, &pdev->dev); 250 251 pdc_wdt_stop(&pdc_wdt->wdt_dev); 252 253 /* Find what caused the last reset */ 254 val = readl(pdc_wdt->base + PDC_WDT_TICKLE1); 255 val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT; 256 switch (val) { 257 case PDC_WDT_TICKLE_STATUS_TICKLE: 258 case PDC_WDT_TICKLE_STATUS_TIMEOUT: 259 pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET; 260 dev_info(&pdev->dev, 261 "watchdog module last reset due to timeout\n"); 262 break; 263 case PDC_WDT_TICKLE_STATUS_HRESET: 264 dev_info(&pdev->dev, 265 "watchdog module last reset due to hard reset\n"); 266 break; 267 case PDC_WDT_TICKLE_STATUS_SRESET: 268 dev_info(&pdev->dev, 269 "watchdog module last reset due to soft reset\n"); 270 break; 271 case PDC_WDT_TICKLE_STATUS_USER: 272 dev_info(&pdev->dev, 273 "watchdog module last reset due to user reset\n"); 274 break; 275 default: 276 dev_info(&pdev->dev, 277 "contains an illegal status code (%08x)\n", val); 278 break; 279 } 280 281 watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout); 282 watchdog_set_restart_priority(&pdc_wdt->wdt_dev, 128); 283 284 platform_set_drvdata(pdev, pdc_wdt); 285 286 ret = watchdog_register_device(&pdc_wdt->wdt_dev); 287 if (ret) 288 goto disable_wdt_clk; 289 290 return 0; 291 292 disable_wdt_clk: 293 clk_disable_unprepare(pdc_wdt->wdt_clk); 294 disable_sys_clk: 295 clk_disable_unprepare(pdc_wdt->sys_clk); 296 return ret; 297 } 298 299 static void pdc_wdt_shutdown(struct platform_device *pdev) 300 { 301 struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev); 302 303 pdc_wdt_stop(&pdc_wdt->wdt_dev); 304 } 305 306 static int pdc_wdt_remove(struct platform_device *pdev) 307 { 308 struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev); 309 310 pdc_wdt_stop(&pdc_wdt->wdt_dev); 311 watchdog_unregister_device(&pdc_wdt->wdt_dev); 312 clk_disable_unprepare(pdc_wdt->wdt_clk); 313 clk_disable_unprepare(pdc_wdt->sys_clk); 314 315 return 0; 316 } 317 318 static const struct of_device_id pdc_wdt_match[] = { 319 { .compatible = "img,pdc-wdt" }, 320 {} 321 }; 322 MODULE_DEVICE_TABLE(of, pdc_wdt_match); 323 324 static struct platform_driver pdc_wdt_driver = { 325 .driver = { 326 .name = "imgpdc-wdt", 327 .of_match_table = pdc_wdt_match, 328 }, 329 .probe = pdc_wdt_probe, 330 .remove = pdc_wdt_remove, 331 .shutdown = pdc_wdt_shutdown, 332 }; 333 module_platform_driver(pdc_wdt_driver); 334 335 MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>"); 336 MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>"); 337 MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver"); 338 MODULE_LICENSE("GPL v2"); 339