1 /* 2 * Watchdog driver for Atmel AT91SAM9x processors. 3 * 4 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 /* 13 * The Watchdog Timer Mode Register can be only written to once. If the 14 * timeout need to be set from Linux, be sure that the bootstrap or the 15 * bootloader doesn't write to this register. 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/clk.h> 21 #include <linux/errno.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/moduleparam.h> 28 #include <linux/platform_device.h> 29 #include <linux/reboot.h> 30 #include <linux/types.h> 31 #include <linux/watchdog.h> 32 #include <linux/jiffies.h> 33 #include <linux/timer.h> 34 #include <linux/bitops.h> 35 #include <linux/uaccess.h> 36 #include <linux/of.h> 37 #include <linux/of_irq.h> 38 39 #include "at91sam9_wdt.h" 40 41 #define DRV_NAME "AT91SAM9 Watchdog" 42 43 #define wdt_read(wdt, field) \ 44 readl_relaxed((wdt)->base + (field)) 45 #define wdt_write(wtd, field, val) \ 46 writel_relaxed((val), (wdt)->base + (field)) 47 48 /* AT91SAM9 watchdog runs a 12bit counter @ 256Hz, 49 * use this to convert a watchdog 50 * value from/to milliseconds. 51 */ 52 #define ticks_to_hz_rounddown(t) ((((t) + 1) * HZ) >> 8) 53 #define ticks_to_hz_roundup(t) (((((t) + 1) * HZ) + 255) >> 8) 54 #define ticks_to_secs(t) (((t) + 1) >> 8) 55 #define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0) 56 57 #define WDT_MR_RESET 0x3FFF2FFF 58 59 /* Watchdog max counter value in ticks */ 60 #define WDT_COUNTER_MAX_TICKS 0xFFF 61 62 /* Watchdog max delta/value in secs */ 63 #define WDT_COUNTER_MAX_SECS ticks_to_secs(WDT_COUNTER_MAX_TICKS) 64 65 /* Hardware timeout in seconds */ 66 #define WDT_HW_TIMEOUT 2 67 68 /* Timer heartbeat (500ms) */ 69 #define WDT_TIMEOUT (HZ/2) 70 71 /* User land timeout */ 72 #define WDT_HEARTBEAT 15 73 static int heartbeat; 74 module_param(heartbeat, int, 0); 75 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. " 76 "(default = " __MODULE_STRING(WDT_HEARTBEAT) ")"); 77 78 static bool nowayout = WATCHDOG_NOWAYOUT; 79 module_param(nowayout, bool, 0); 80 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " 81 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 82 83 #define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd) 84 struct at91wdt { 85 struct watchdog_device wdd; 86 void __iomem *base; 87 unsigned long next_heartbeat; /* the next_heartbeat for the timer */ 88 struct timer_list timer; /* The timer that pings the watchdog */ 89 u32 mr; 90 u32 mr_mask; 91 unsigned long heartbeat; /* WDT heartbeat in jiffies */ 92 bool nowayout; 93 unsigned int irq; 94 struct clk *sclk; 95 }; 96 97 /* ......................................................................... */ 98 99 static irqreturn_t wdt_interrupt(int irq, void *dev_id) 100 { 101 struct at91wdt *wdt = (struct at91wdt *)dev_id; 102 103 if (wdt_read(wdt, AT91_WDT_SR)) { 104 pr_crit("at91sam9 WDT software reset\n"); 105 emergency_restart(); 106 pr_crit("Reboot didn't ?????\n"); 107 } 108 109 return IRQ_HANDLED; 110 } 111 112 /* 113 * Reload the watchdog timer. (ie, pat the watchdog) 114 */ 115 static inline void at91_wdt_reset(struct at91wdt *wdt) 116 { 117 wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); 118 } 119 120 /* 121 * Timer tick 122 */ 123 static void at91_ping(unsigned long data) 124 { 125 struct at91wdt *wdt = (struct at91wdt *)data; 126 if (time_before(jiffies, wdt->next_heartbeat) || 127 !watchdog_active(&wdt->wdd)) { 128 at91_wdt_reset(wdt); 129 mod_timer(&wdt->timer, jiffies + wdt->heartbeat); 130 } else { 131 pr_crit("I will reset your machine !\n"); 132 } 133 } 134 135 static int at91_wdt_start(struct watchdog_device *wdd) 136 { 137 struct at91wdt *wdt = to_wdt(wdd); 138 /* calculate when the next userspace timeout will be */ 139 wdt->next_heartbeat = jiffies + wdd->timeout * HZ; 140 return 0; 141 } 142 143 static int at91_wdt_stop(struct watchdog_device *wdd) 144 { 145 /* The watchdog timer hardware can not be stopped... */ 146 return 0; 147 } 148 149 static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout) 150 { 151 wdd->timeout = new_timeout; 152 return at91_wdt_start(wdd); 153 } 154 155 static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt) 156 { 157 u32 tmp; 158 u32 delta; 159 u32 value; 160 int err; 161 u32 mask = wdt->mr_mask; 162 unsigned long min_heartbeat = 1; 163 unsigned long max_heartbeat; 164 struct device *dev = &pdev->dev; 165 166 tmp = wdt_read(wdt, AT91_WDT_MR); 167 if ((tmp & mask) != (wdt->mr & mask)) { 168 if (tmp == WDT_MR_RESET) { 169 wdt_write(wdt, AT91_WDT_MR, wdt->mr); 170 tmp = wdt_read(wdt, AT91_WDT_MR); 171 } 172 } 173 174 if (tmp & AT91_WDT_WDDIS) { 175 if (wdt->mr & AT91_WDT_WDDIS) 176 return 0; 177 dev_err(dev, "watchdog is disabled\n"); 178 return -EINVAL; 179 } 180 181 value = tmp & AT91_WDT_WDV; 182 delta = (tmp & AT91_WDT_WDD) >> 16; 183 184 if (delta < value) 185 min_heartbeat = ticks_to_hz_roundup(value - delta); 186 187 max_heartbeat = ticks_to_hz_rounddown(value); 188 if (!max_heartbeat) { 189 dev_err(dev, 190 "heartbeat is too small for the system to handle it correctly\n"); 191 return -EINVAL; 192 } 193 194 /* 195 * Try to reset the watchdog counter 4 or 2 times more often than 196 * actually requested, to avoid spurious watchdog reset. 197 * If this is not possible because of the min_heartbeat value, reset 198 * it at the min_heartbeat period. 199 */ 200 if ((max_heartbeat / 4) >= min_heartbeat) 201 wdt->heartbeat = max_heartbeat / 4; 202 else if ((max_heartbeat / 2) >= min_heartbeat) 203 wdt->heartbeat = max_heartbeat / 2; 204 else 205 wdt->heartbeat = min_heartbeat; 206 207 if (max_heartbeat < min_heartbeat + 4) 208 dev_warn(dev, 209 "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n"); 210 211 if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) { 212 err = request_irq(wdt->irq, wdt_interrupt, 213 IRQF_SHARED | IRQF_IRQPOLL | 214 IRQF_NO_SUSPEND, 215 pdev->name, wdt); 216 if (err) 217 return err; 218 } 219 220 if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask)) 221 dev_warn(dev, 222 "watchdog already configured differently (mr = %x expecting %x)\n", 223 tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask); 224 225 setup_timer(&wdt->timer, at91_ping, (unsigned long)wdt); 226 227 /* 228 * Use min_heartbeat the first time to avoid spurious watchdog reset: 229 * we don't know for how long the watchdog counter is running, and 230 * - resetting it right now might trigger a watchdog fault reset 231 * - waiting for heartbeat time might lead to a watchdog timeout 232 * reset 233 */ 234 mod_timer(&wdt->timer, jiffies + min_heartbeat); 235 236 /* Try to set timeout from device tree first */ 237 if (watchdog_init_timeout(&wdt->wdd, 0, dev)) 238 watchdog_init_timeout(&wdt->wdd, heartbeat, dev); 239 watchdog_set_nowayout(&wdt->wdd, wdt->nowayout); 240 err = watchdog_register_device(&wdt->wdd); 241 if (err) 242 goto out_stop_timer; 243 244 wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ; 245 246 return 0; 247 248 out_stop_timer: 249 del_timer(&wdt->timer); 250 return err; 251 } 252 253 /* ......................................................................... */ 254 255 static const struct watchdog_info at91_wdt_info = { 256 .identity = DRV_NAME, 257 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | 258 WDIOF_MAGICCLOSE, 259 }; 260 261 static const struct watchdog_ops at91_wdt_ops = { 262 .owner = THIS_MODULE, 263 .start = at91_wdt_start, 264 .stop = at91_wdt_stop, 265 .set_timeout = at91_wdt_set_timeout, 266 }; 267 268 #if defined(CONFIG_OF) 269 static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt) 270 { 271 u32 min = 0; 272 u32 max = WDT_COUNTER_MAX_SECS; 273 const char *tmp; 274 275 /* Get the interrupts property */ 276 wdt->irq = irq_of_parse_and_map(np, 0); 277 if (!wdt->irq) 278 dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n"); 279 280 if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0, 281 &max)) { 282 if (!max || max > WDT_COUNTER_MAX_SECS) 283 max = WDT_COUNTER_MAX_SECS; 284 285 if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec", 286 0, &min)) { 287 if (min >= max) 288 min = max - 1; 289 } 290 } 291 292 min = secs_to_ticks(min); 293 max = secs_to_ticks(max); 294 295 wdt->mr_mask = 0x3FFFFFFF; 296 wdt->mr = 0; 297 if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) && 298 !strcmp(tmp, "software")) { 299 wdt->mr |= AT91_WDT_WDFIEN; 300 wdt->mr_mask &= ~AT91_WDT_WDRPROC; 301 } else { 302 wdt->mr |= AT91_WDT_WDRSTEN; 303 } 304 305 if (!of_property_read_string(np, "atmel,reset-type", &tmp) && 306 !strcmp(tmp, "proc")) 307 wdt->mr |= AT91_WDT_WDRPROC; 308 309 if (of_property_read_bool(np, "atmel,disable")) { 310 wdt->mr |= AT91_WDT_WDDIS; 311 wdt->mr_mask &= AT91_WDT_WDDIS; 312 } 313 314 if (of_property_read_bool(np, "atmel,idle-halt")) 315 wdt->mr |= AT91_WDT_WDIDLEHLT; 316 317 if (of_property_read_bool(np, "atmel,dbg-halt")) 318 wdt->mr |= AT91_WDT_WDDBGHLT; 319 320 wdt->mr |= max | ((max - min) << 16); 321 322 return 0; 323 } 324 #else 325 static inline int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt) 326 { 327 return 0; 328 } 329 #endif 330 331 static int __init at91wdt_probe(struct platform_device *pdev) 332 { 333 struct resource *r; 334 int err; 335 struct at91wdt *wdt; 336 337 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); 338 if (!wdt) 339 return -ENOMEM; 340 341 wdt->mr = (WDT_HW_TIMEOUT * 256) | AT91_WDT_WDRSTEN | AT91_WDT_WDD | 342 AT91_WDT_WDDBGHLT | AT91_WDT_WDIDLEHLT; 343 wdt->mr_mask = 0x3FFFFFFF; 344 wdt->nowayout = nowayout; 345 wdt->wdd.parent = &pdev->dev; 346 wdt->wdd.info = &at91_wdt_info; 347 wdt->wdd.ops = &at91_wdt_ops; 348 wdt->wdd.timeout = WDT_HEARTBEAT; 349 wdt->wdd.min_timeout = 1; 350 wdt->wdd.max_timeout = 0xFFFF; 351 352 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 353 wdt->base = devm_ioremap_resource(&pdev->dev, r); 354 if (IS_ERR(wdt->base)) 355 return PTR_ERR(wdt->base); 356 357 wdt->sclk = devm_clk_get(&pdev->dev, NULL); 358 if (IS_ERR(wdt->sclk)) 359 return PTR_ERR(wdt->sclk); 360 361 err = clk_prepare_enable(wdt->sclk); 362 if (err) { 363 dev_err(&pdev->dev, "Could not enable slow clock\n"); 364 return err; 365 } 366 367 if (pdev->dev.of_node) { 368 err = of_at91wdt_init(pdev->dev.of_node, wdt); 369 if (err) 370 goto err_clk; 371 } 372 373 err = at91_wdt_init(pdev, wdt); 374 if (err) 375 goto err_clk; 376 377 platform_set_drvdata(pdev, wdt); 378 379 pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n", 380 wdt->wdd.timeout, wdt->nowayout); 381 382 return 0; 383 384 err_clk: 385 clk_disable_unprepare(wdt->sclk); 386 387 return err; 388 } 389 390 static int __exit at91wdt_remove(struct platform_device *pdev) 391 { 392 struct at91wdt *wdt = platform_get_drvdata(pdev); 393 watchdog_unregister_device(&wdt->wdd); 394 395 pr_warn("I quit now, hardware will probably reboot!\n"); 396 del_timer(&wdt->timer); 397 clk_disable_unprepare(wdt->sclk); 398 399 return 0; 400 } 401 402 #if defined(CONFIG_OF) 403 static const struct of_device_id at91_wdt_dt_ids[] = { 404 { .compatible = "atmel,at91sam9260-wdt" }, 405 { /* sentinel */ } 406 }; 407 408 MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids); 409 #endif 410 411 static struct platform_driver at91wdt_driver = { 412 .remove = __exit_p(at91wdt_remove), 413 .driver = { 414 .name = "at91_wdt", 415 .of_match_table = of_match_ptr(at91_wdt_dt_ids), 416 }, 417 }; 418 419 module_platform_driver_probe(at91wdt_driver, at91wdt_probe); 420 421 MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>"); 422 MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors"); 423 MODULE_LICENSE("GPL"); 424