1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 2 /* 3 * Apple SoC Watchdog driver 4 * 5 * Copyright (C) The Asahi Linux Contributors 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/limits.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/watchdog.h> 18 19 /* 20 * Apple Watchdog MMIO registers 21 * 22 * This HW block has three separate watchdogs. WD0 resets the machine 23 * to recovery mode and is not very useful for us. WD1 and WD2 trigger a normal 24 * machine reset. WD0 additionally supports a configurable interrupt. 25 * This information can be used to implement pretimeout support at a later time. 26 * 27 * APPLE_WDT_WDx_CUR_TIME is a simple counter incremented for each tick of the 28 * reference clock. It can also be overwritten to any value. 29 * Whenever APPLE_WDT_CTRL_RESET_EN is set in APPLE_WDT_WDx_CTRL and 30 * APPLE_WDT_WDx_CUR_TIME >= APPLE_WDT_WDx_BITE_TIME the entire machine is 31 * reset. 32 * Whenever APPLE_WDT_CTRL_IRQ_EN is set and APPLE_WDTx_WD1_CUR_TIME >= 33 * APPLE_WDTx_WD1_BARK_TIME an interrupt is triggered and 34 * APPLE_WDT_CTRL_IRQ_STATUS is set. The interrupt can be cleared by writing 35 * 1 to APPLE_WDT_CTRL_IRQ_STATUS. 36 */ 37 #define APPLE_WDT_WD0_CUR_TIME 0x00 38 #define APPLE_WDT_WD0_BITE_TIME 0x04 39 #define APPLE_WDT_WD0_BARK_TIME 0x08 40 #define APPLE_WDT_WD0_CTRL 0x0c 41 42 #define APPLE_WDT_WD1_CUR_TIME 0x10 43 #define APPLE_WDT_WD1_BITE_TIME 0x14 44 #define APPLE_WDT_WD1_CTRL 0x1c 45 46 #define APPLE_WDT_WD2_CUR_TIME 0x20 47 #define APPLE_WDT_WD2_BITE_TIME 0x24 48 #define APPLE_WDT_WD2_CTRL 0x2c 49 50 #define APPLE_WDT_CTRL_IRQ_EN BIT(0) 51 #define APPLE_WDT_CTRL_IRQ_STATUS BIT(1) 52 #define APPLE_WDT_CTRL_RESET_EN BIT(2) 53 54 #define APPLE_WDT_TIMEOUT_DEFAULT 30 55 56 struct apple_wdt { 57 struct watchdog_device wdd; 58 void __iomem *regs; 59 unsigned long clk_rate; 60 }; 61 62 static struct apple_wdt *to_apple_wdt(struct watchdog_device *wdd) 63 { 64 return container_of(wdd, struct apple_wdt, wdd); 65 } 66 67 static int apple_wdt_start(struct watchdog_device *wdd) 68 { 69 struct apple_wdt *wdt = to_apple_wdt(wdd); 70 71 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME); 72 writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL); 73 74 return 0; 75 } 76 77 static int apple_wdt_stop(struct watchdog_device *wdd) 78 { 79 struct apple_wdt *wdt = to_apple_wdt(wdd); 80 81 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CTRL); 82 83 return 0; 84 } 85 86 static int apple_wdt_ping(struct watchdog_device *wdd) 87 { 88 struct apple_wdt *wdt = to_apple_wdt(wdd); 89 90 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME); 91 92 return 0; 93 } 94 95 static int apple_wdt_set_timeout(struct watchdog_device *wdd, unsigned int s) 96 { 97 struct apple_wdt *wdt = to_apple_wdt(wdd); 98 u32 actual; 99 100 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME); 101 102 actual = min(s, wdd->max_hw_heartbeat_ms / 1000); 103 writel_relaxed(wdt->clk_rate * actual, wdt->regs + APPLE_WDT_WD1_BITE_TIME); 104 105 wdd->timeout = s; 106 107 return 0; 108 } 109 110 static unsigned int apple_wdt_get_timeleft(struct watchdog_device *wdd) 111 { 112 struct apple_wdt *wdt = to_apple_wdt(wdd); 113 u32 cur_time, reset_time; 114 115 cur_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME); 116 reset_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_BITE_TIME); 117 118 return (reset_time - cur_time) / wdt->clk_rate; 119 } 120 121 static int apple_wdt_restart(struct watchdog_device *wdd, unsigned long mode, 122 void *cmd) 123 { 124 struct apple_wdt *wdt = to_apple_wdt(wdd); 125 126 writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL); 127 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_BITE_TIME); 128 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME); 129 130 /* 131 * Flush writes and then wait for the SoC to reset. Even though the 132 * reset is queued almost immediately experiments have shown that it 133 * can take up to ~120-125ms until the SoC is actually reset. Just 134 * wait 150ms here to be safe. 135 */ 136 (void)readl(wdt->regs + APPLE_WDT_WD1_CUR_TIME); 137 mdelay(150); 138 139 return 0; 140 } 141 142 static struct watchdog_ops apple_wdt_ops = { 143 .owner = THIS_MODULE, 144 .start = apple_wdt_start, 145 .stop = apple_wdt_stop, 146 .ping = apple_wdt_ping, 147 .set_timeout = apple_wdt_set_timeout, 148 .get_timeleft = apple_wdt_get_timeleft, 149 .restart = apple_wdt_restart, 150 }; 151 152 static struct watchdog_info apple_wdt_info = { 153 .identity = "Apple SoC Watchdog", 154 .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 155 }; 156 157 static int apple_wdt_probe(struct platform_device *pdev) 158 { 159 struct device *dev = &pdev->dev; 160 struct apple_wdt *wdt; 161 struct clk *clk; 162 u32 wdt_ctrl; 163 164 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 165 if (!wdt) 166 return -ENOMEM; 167 168 wdt->regs = devm_platform_ioremap_resource(pdev, 0); 169 if (IS_ERR(wdt->regs)) 170 return PTR_ERR(wdt->regs); 171 172 clk = devm_clk_get_enabled(dev, NULL); 173 if (IS_ERR(clk)) 174 return PTR_ERR(clk); 175 wdt->clk_rate = clk_get_rate(clk); 176 if (!wdt->clk_rate) 177 return -EINVAL; 178 179 platform_set_drvdata(pdev, wdt); 180 181 wdt->wdd.ops = &apple_wdt_ops; 182 wdt->wdd.info = &apple_wdt_info; 183 wdt->wdd.max_hw_heartbeat_ms = U32_MAX / wdt->clk_rate * 1000; 184 wdt->wdd.timeout = APPLE_WDT_TIMEOUT_DEFAULT; 185 186 wdt_ctrl = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CTRL); 187 if (wdt_ctrl & APPLE_WDT_CTRL_RESET_EN) 188 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); 189 190 watchdog_init_timeout(&wdt->wdd, 0, dev); 191 apple_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout); 192 watchdog_stop_on_unregister(&wdt->wdd); 193 watchdog_set_restart_priority(&wdt->wdd, 128); 194 195 return devm_watchdog_register_device(dev, &wdt->wdd); 196 } 197 198 static int apple_wdt_resume(struct device *dev) 199 { 200 struct apple_wdt *wdt = dev_get_drvdata(dev); 201 202 if (watchdog_active(&wdt->wdd) || watchdog_hw_running(&wdt->wdd)) 203 apple_wdt_start(&wdt->wdd); 204 205 return 0; 206 } 207 208 static int apple_wdt_suspend(struct device *dev) 209 { 210 struct apple_wdt *wdt = dev_get_drvdata(dev); 211 212 if (watchdog_active(&wdt->wdd) || watchdog_hw_running(&wdt->wdd)) 213 apple_wdt_stop(&wdt->wdd); 214 215 return 0; 216 } 217 218 static DEFINE_SIMPLE_DEV_PM_OPS(apple_wdt_pm_ops, apple_wdt_suspend, apple_wdt_resume); 219 220 static const struct of_device_id apple_wdt_of_match[] = { 221 { .compatible = "apple,wdt" }, 222 {}, 223 }; 224 MODULE_DEVICE_TABLE(of, apple_wdt_of_match); 225 226 static struct platform_driver apple_wdt_driver = { 227 .driver = { 228 .name = "apple-watchdog", 229 .of_match_table = apple_wdt_of_match, 230 .pm = pm_sleep_ptr(&apple_wdt_pm_ops), 231 }, 232 .probe = apple_wdt_probe, 233 }; 234 module_platform_driver(apple_wdt_driver); 235 236 MODULE_DESCRIPTION("Apple SoC watchdog driver"); 237 MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>"); 238 MODULE_LICENSE("Dual MIT/GPL"); 239