1 /* 2 * w1_io.c 3 * 4 * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru> 5 * 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <asm/io.h> 23 24 #include <linux/delay.h> 25 #include <linux/moduleparam.h> 26 27 #include "w1.h" 28 #include "w1_log.h" 29 #include "w1_io.h" 30 31 static int w1_delay_parm = 1; 32 module_param_named(delay_coef, w1_delay_parm, int, 0); 33 34 static u8 w1_crc8_table[] = { 35 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65, 36 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220, 37 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98, 38 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255, 39 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7, 40 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154, 41 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36, 42 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185, 43 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205, 44 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80, 45 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238, 46 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115, 47 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139, 48 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22, 49 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168, 50 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53 51 }; 52 53 void w1_delay(unsigned long tm) 54 { 55 udelay(tm * w1_delay_parm); 56 } 57 58 static void w1_write_bit(struct w1_master *dev, int bit); 59 static u8 w1_read_bit(struct w1_master *dev); 60 61 /** 62 * Generates a write-0 or write-1 cycle and samples the level. 63 */ 64 u8 w1_touch_bit(struct w1_master *dev, int bit) 65 { 66 if (dev->bus_master->touch_bit) 67 return dev->bus_master->touch_bit(dev->bus_master->data, bit); 68 else if (bit) 69 return w1_read_bit(dev); 70 else { 71 w1_write_bit(dev, 0); 72 return(0); 73 } 74 } 75 76 /** 77 * Generates a write-0 or write-1 cycle. 78 * Only call if dev->bus_master->touch_bit is NULL 79 */ 80 static void w1_write_bit(struct w1_master *dev, int bit) 81 { 82 if (bit) { 83 dev->bus_master->write_bit(dev->bus_master->data, 0); 84 w1_delay(6); 85 dev->bus_master->write_bit(dev->bus_master->data, 1); 86 w1_delay(64); 87 } else { 88 dev->bus_master->write_bit(dev->bus_master->data, 0); 89 w1_delay(60); 90 dev->bus_master->write_bit(dev->bus_master->data, 1); 91 w1_delay(10); 92 } 93 } 94 95 /** 96 * Writes 8 bits. 97 * 98 * @param dev the master device 99 * @param byte the byte to write 100 */ 101 void w1_write_8(struct w1_master *dev, u8 byte) 102 { 103 int i; 104 105 if (dev->bus_master->write_byte) 106 dev->bus_master->write_byte(dev->bus_master->data, byte); 107 else 108 for (i = 0; i < 8; ++i) 109 w1_touch_bit(dev, (byte >> i) & 0x1); 110 } 111 112 113 /** 114 * Generates a write-1 cycle and samples the level. 115 * Only call if dev->bus_master->touch_bit is NULL 116 */ 117 static u8 w1_read_bit(struct w1_master *dev) 118 { 119 int result; 120 121 dev->bus_master->write_bit(dev->bus_master->data, 0); 122 w1_delay(6); 123 dev->bus_master->write_bit(dev->bus_master->data, 1); 124 w1_delay(9); 125 126 result = dev->bus_master->read_bit(dev->bus_master->data); 127 w1_delay(55); 128 129 return result & 0x1; 130 } 131 132 /** 133 * Does a triplet - used for searching ROM addresses. 134 * Return bits: 135 * bit 0 = id_bit 136 * bit 1 = comp_bit 137 * bit 2 = dir_taken 138 * If both bits 0 & 1 are set, the search should be restarted. 139 * 140 * @param dev the master device 141 * @param bdir the bit to write if both id_bit and comp_bit are 0 142 * @return bit fields - see above 143 */ 144 u8 w1_triplet(struct w1_master *dev, int bdir) 145 { 146 if ( dev->bus_master->triplet ) 147 return(dev->bus_master->triplet(dev->bus_master->data, bdir)); 148 else { 149 u8 id_bit = w1_touch_bit(dev, 1); 150 u8 comp_bit = w1_touch_bit(dev, 1); 151 u8 retval; 152 153 if ( id_bit && comp_bit ) 154 return(0x03); /* error */ 155 156 if ( !id_bit && !comp_bit ) { 157 /* Both bits are valid, take the direction given */ 158 retval = bdir ? 0x04 : 0; 159 } else { 160 /* Only one bit is valid, take that direction */ 161 bdir = id_bit; 162 retval = id_bit ? 0x05 : 0x02; 163 } 164 165 if ( dev->bus_master->touch_bit ) 166 w1_touch_bit(dev, bdir); 167 else 168 w1_write_bit(dev, bdir); 169 return(retval); 170 } 171 } 172 173 /** 174 * Reads 8 bits. 175 * 176 * @param dev the master device 177 * @return the byte read 178 */ 179 u8 w1_read_8(struct w1_master * dev) 180 { 181 int i; 182 u8 res = 0; 183 184 if (dev->bus_master->read_byte) 185 res = dev->bus_master->read_byte(dev->bus_master->data); 186 else 187 for (i = 0; i < 8; ++i) 188 res |= (w1_touch_bit(dev,1) << i); 189 190 return res; 191 } 192 193 /** 194 * Writes a series of bytes. 195 * 196 * @param dev the master device 197 * @param buf pointer to the data to write 198 * @param len the number of bytes to write 199 * @return the byte read 200 */ 201 void w1_write_block(struct w1_master *dev, const u8 *buf, int len) 202 { 203 int i; 204 205 if (dev->bus_master->write_block) 206 dev->bus_master->write_block(dev->bus_master->data, buf, len); 207 else 208 for (i = 0; i < len; ++i) 209 w1_write_8(dev, buf[i]); 210 } 211 212 /** 213 * Reads a series of bytes. 214 * 215 * @param dev the master device 216 * @param buf pointer to the buffer to fill 217 * @param len the number of bytes to read 218 * @return the number of bytes read 219 */ 220 u8 w1_read_block(struct w1_master *dev, u8 *buf, int len) 221 { 222 int i; 223 u8 ret; 224 225 if (dev->bus_master->read_block) 226 ret = dev->bus_master->read_block(dev->bus_master->data, buf, len); 227 else { 228 for (i = 0; i < len; ++i) 229 buf[i] = w1_read_8(dev); 230 ret = len; 231 } 232 233 return ret; 234 } 235 236 /** 237 * Issues a reset bus sequence. 238 * 239 * @param dev The bus master pointer 240 * @return 0=Device present, 1=No device present or error 241 */ 242 int w1_reset_bus(struct w1_master *dev) 243 { 244 int result; 245 246 if (dev->bus_master->reset_bus) 247 result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1; 248 else { 249 dev->bus_master->write_bit(dev->bus_master->data, 0); 250 w1_delay(480); 251 dev->bus_master->write_bit(dev->bus_master->data, 1); 252 w1_delay(70); 253 254 result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1; 255 w1_delay(410); 256 } 257 258 return result; 259 } 260 261 u8 w1_calc_crc8(u8 * data, int len) 262 { 263 u8 crc = 0; 264 265 while (len--) 266 crc = w1_crc8_table[crc ^ *data++]; 267 268 return crc; 269 } 270 271 void w1_search_devices(struct w1_master *dev, w1_slave_found_callback cb) 272 { 273 dev->attempts++; 274 if (dev->bus_master->search) 275 dev->bus_master->search(dev->bus_master->data, cb); 276 else 277 w1_search(dev, cb); 278 } 279 280 /** 281 * Resets the bus and then selects the slave by sending either a skip rom 282 * or a rom match. 283 * The w1 master lock must be held. 284 * 285 * @param sl the slave to select 286 * @return 0=success, anything else=error 287 */ 288 int w1_reset_select_slave(struct w1_slave *sl) 289 { 290 if (w1_reset_bus(sl->master)) 291 return -1; 292 293 if (sl->master->slave_count == 1) 294 w1_write_8(sl->master, W1_SKIP_ROM); 295 else { 296 u8 match[9] = {W1_MATCH_ROM, }; 297 memcpy(&match[1], (u8 *)&sl->reg_num, 8); 298 w1_write_block(sl->master, match, 9); 299 } 300 return 0; 301 } 302 303 EXPORT_SYMBOL(w1_touch_bit); 304 EXPORT_SYMBOL(w1_write_8); 305 EXPORT_SYMBOL(w1_read_8); 306 EXPORT_SYMBOL(w1_reset_bus); 307 EXPORT_SYMBOL(w1_calc_crc8); 308 EXPORT_SYMBOL(w1_delay); 309 EXPORT_SYMBOL(w1_read_block); 310 EXPORT_SYMBOL(w1_write_block); 311 EXPORT_SYMBOL(w1_search_devices); 312 EXPORT_SYMBOL(w1_reset_select_slave); 313