1 /* 2 * Copyright (c) 2004 Evgeniy Polyakov <zbr@ioremap.net> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <asm/io.h> 16 17 #include <linux/delay.h> 18 #include <linux/moduleparam.h> 19 #include <linux/module.h> 20 21 #include "w1.h" 22 #include "w1_log.h" 23 24 static int w1_delay_parm = 1; 25 module_param_named(delay_coef, w1_delay_parm, int, 0); 26 27 static int w1_disable_irqs = 0; 28 module_param_named(disable_irqs, w1_disable_irqs, int, 0); 29 30 static u8 w1_crc8_table[] = { 31 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65, 32 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220, 33 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98, 34 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255, 35 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7, 36 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154, 37 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36, 38 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185, 39 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205, 40 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80, 41 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238, 42 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115, 43 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139, 44 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22, 45 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168, 46 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53 47 }; 48 49 static void w1_delay(unsigned long tm) 50 { 51 udelay(tm * w1_delay_parm); 52 } 53 54 static void w1_write_bit(struct w1_master *dev, int bit); 55 static u8 w1_read_bit(struct w1_master *dev); 56 57 /** 58 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level. 59 * @dev: the master device 60 * @bit: 0 - write a 0, 1 - write a 0 read the level 61 */ 62 static u8 w1_touch_bit(struct w1_master *dev, int bit) 63 { 64 if (dev->bus_master->touch_bit) 65 return dev->bus_master->touch_bit(dev->bus_master->data, bit); 66 else if (bit) 67 return w1_read_bit(dev); 68 else { 69 w1_write_bit(dev, 0); 70 return 0; 71 } 72 } 73 74 /** 75 * w1_write_bit() - Generates a write-0 or write-1 cycle. 76 * @dev: the master device 77 * @bit: bit to write 78 * 79 * Only call if dev->bus_master->touch_bit is NULL 80 */ 81 static void w1_write_bit(struct w1_master *dev, int bit) 82 { 83 unsigned long flags = 0; 84 85 if(w1_disable_irqs) local_irq_save(flags); 86 87 if (bit) { 88 dev->bus_master->write_bit(dev->bus_master->data, 0); 89 w1_delay(6); 90 dev->bus_master->write_bit(dev->bus_master->data, 1); 91 w1_delay(64); 92 } else { 93 dev->bus_master->write_bit(dev->bus_master->data, 0); 94 w1_delay(60); 95 dev->bus_master->write_bit(dev->bus_master->data, 1); 96 w1_delay(10); 97 } 98 99 if(w1_disable_irqs) local_irq_restore(flags); 100 } 101 102 /** 103 * w1_pre_write() - pre-write operations 104 * @dev: the master device 105 * 106 * Pre-write operation, currently only supporting strong pullups. 107 * Program the hardware for a strong pullup, if one has been requested and 108 * the hardware supports it. 109 */ 110 static void w1_pre_write(struct w1_master *dev) 111 { 112 if (dev->pullup_duration && 113 dev->enable_pullup && dev->bus_master->set_pullup) { 114 dev->bus_master->set_pullup(dev->bus_master->data, 115 dev->pullup_duration); 116 } 117 } 118 119 /** 120 * w1_post_write() - post-write options 121 * @dev: the master device 122 * 123 * Post-write operation, currently only supporting strong pullups. 124 * If a strong pullup was requested, clear it if the hardware supports 125 * them, or execute the delay otherwise, in either case clear the request. 126 */ 127 static void w1_post_write(struct w1_master *dev) 128 { 129 if (dev->pullup_duration) { 130 if (dev->enable_pullup && dev->bus_master->set_pullup) 131 dev->bus_master->set_pullup(dev->bus_master->data, 0); 132 else 133 msleep(dev->pullup_duration); 134 dev->pullup_duration = 0; 135 } 136 } 137 138 /** 139 * w1_write_8() - Writes 8 bits. 140 * @dev: the master device 141 * @byte: the byte to write 142 */ 143 void w1_write_8(struct w1_master *dev, u8 byte) 144 { 145 int i; 146 147 if (dev->bus_master->write_byte) { 148 w1_pre_write(dev); 149 dev->bus_master->write_byte(dev->bus_master->data, byte); 150 } 151 else 152 for (i = 0; i < 8; ++i) { 153 if (i == 7) 154 w1_pre_write(dev); 155 w1_touch_bit(dev, (byte >> i) & 0x1); 156 } 157 w1_post_write(dev); 158 } 159 EXPORT_SYMBOL_GPL(w1_write_8); 160 161 162 /** 163 * w1_read_bit() - Generates a write-1 cycle and samples the level. 164 * @dev: the master device 165 * 166 * Only call if dev->bus_master->touch_bit is NULL 167 */ 168 static u8 w1_read_bit(struct w1_master *dev) 169 { 170 int result; 171 unsigned long flags = 0; 172 173 /* sample timing is critical here */ 174 local_irq_save(flags); 175 dev->bus_master->write_bit(dev->bus_master->data, 0); 176 w1_delay(6); 177 dev->bus_master->write_bit(dev->bus_master->data, 1); 178 w1_delay(9); 179 180 result = dev->bus_master->read_bit(dev->bus_master->data); 181 local_irq_restore(flags); 182 183 w1_delay(55); 184 185 return result & 0x1; 186 } 187 188 /** 189 * w1_triplet() - * Does a triplet - used for searching ROM addresses. 190 * @dev: the master device 191 * @bdir: the bit to write if both id_bit and comp_bit are 0 192 * 193 * Return bits: 194 * bit 0 = id_bit 195 * bit 1 = comp_bit 196 * bit 2 = dir_taken 197 * If both bits 0 & 1 are set, the search should be restarted. 198 * 199 * Return: bit fields - see above 200 */ 201 u8 w1_triplet(struct w1_master *dev, int bdir) 202 { 203 if (dev->bus_master->triplet) 204 return dev->bus_master->triplet(dev->bus_master->data, bdir); 205 else { 206 u8 id_bit = w1_touch_bit(dev, 1); 207 u8 comp_bit = w1_touch_bit(dev, 1); 208 u8 retval; 209 210 if (id_bit && comp_bit) 211 return 0x03; /* error */ 212 213 if (!id_bit && !comp_bit) { 214 /* Both bits are valid, take the direction given */ 215 retval = bdir ? 0x04 : 0; 216 } else { 217 /* Only one bit is valid, take that direction */ 218 bdir = id_bit; 219 retval = id_bit ? 0x05 : 0x02; 220 } 221 222 if (dev->bus_master->touch_bit) 223 w1_touch_bit(dev, bdir); 224 else 225 w1_write_bit(dev, bdir); 226 return retval; 227 } 228 } 229 EXPORT_SYMBOL_GPL(w1_triplet); 230 231 /** 232 * w1_read_8() - Reads 8 bits. 233 * @dev: the master device 234 * 235 * Return: the byte read 236 */ 237 u8 w1_read_8(struct w1_master *dev) 238 { 239 int i; 240 u8 res = 0; 241 242 if (dev->bus_master->read_byte) 243 res = dev->bus_master->read_byte(dev->bus_master->data); 244 else 245 for (i = 0; i < 8; ++i) 246 res |= (w1_touch_bit(dev,1) << i); 247 248 return res; 249 } 250 EXPORT_SYMBOL_GPL(w1_read_8); 251 252 /** 253 * w1_write_block() - Writes a series of bytes. 254 * @dev: the master device 255 * @buf: pointer to the data to write 256 * @len: the number of bytes to write 257 */ 258 void w1_write_block(struct w1_master *dev, const u8 *buf, int len) 259 { 260 int i; 261 262 if (dev->bus_master->write_block) { 263 w1_pre_write(dev); 264 dev->bus_master->write_block(dev->bus_master->data, buf, len); 265 } 266 else 267 for (i = 0; i < len; ++i) 268 w1_write_8(dev, buf[i]); /* calls w1_pre_write */ 269 w1_post_write(dev); 270 } 271 EXPORT_SYMBOL_GPL(w1_write_block); 272 273 /** 274 * w1_touch_block() - Touches a series of bytes. 275 * @dev: the master device 276 * @buf: pointer to the data to write 277 * @len: the number of bytes to write 278 */ 279 void w1_touch_block(struct w1_master *dev, u8 *buf, int len) 280 { 281 int i, j; 282 u8 tmp; 283 284 for (i = 0; i < len; ++i) { 285 tmp = 0; 286 for (j = 0; j < 8; ++j) { 287 if (j == 7) 288 w1_pre_write(dev); 289 tmp |= w1_touch_bit(dev, (buf[i] >> j) & 0x1) << j; 290 } 291 292 buf[i] = tmp; 293 } 294 } 295 EXPORT_SYMBOL_GPL(w1_touch_block); 296 297 /** 298 * w1_read_block() - Reads a series of bytes. 299 * @dev: the master device 300 * @buf: pointer to the buffer to fill 301 * @len: the number of bytes to read 302 * Return: the number of bytes read 303 */ 304 u8 w1_read_block(struct w1_master *dev, u8 *buf, int len) 305 { 306 int i; 307 u8 ret; 308 309 if (dev->bus_master->read_block) 310 ret = dev->bus_master->read_block(dev->bus_master->data, buf, len); 311 else { 312 for (i = 0; i < len; ++i) 313 buf[i] = w1_read_8(dev); 314 ret = len; 315 } 316 317 return ret; 318 } 319 EXPORT_SYMBOL_GPL(w1_read_block); 320 321 /** 322 * w1_reset_bus() - Issues a reset bus sequence. 323 * @dev: the master device 324 * Return: 0=Device present, 1=No device present or error 325 */ 326 int w1_reset_bus(struct w1_master *dev) 327 { 328 int result; 329 unsigned long flags = 0; 330 331 if(w1_disable_irqs) local_irq_save(flags); 332 333 if (dev->bus_master->reset_bus) 334 result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1; 335 else { 336 dev->bus_master->write_bit(dev->bus_master->data, 0); 337 /* minimum 480, max ? us 338 * be nice and sleep, except 18b20 spec lists 960us maximum, 339 * so until we can sleep with microsecond accuracy, spin. 340 * Feel free to come up with some other way to give up the 341 * cpu for such a short amount of time AND get it back in 342 * the maximum amount of time. 343 */ 344 w1_delay(500); 345 dev->bus_master->write_bit(dev->bus_master->data, 1); 346 w1_delay(70); 347 348 result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1; 349 /* minimum 70 (above) + 430 = 500 us 350 * There aren't any timing requirements between a reset and 351 * the following transactions. Sleeping is safe here. 352 */ 353 /* w1_delay(430); min required time */ 354 msleep(1); 355 } 356 357 if(w1_disable_irqs) local_irq_restore(flags); 358 359 return result; 360 } 361 EXPORT_SYMBOL_GPL(w1_reset_bus); 362 363 u8 w1_calc_crc8(u8 * data, int len) 364 { 365 u8 crc = 0; 366 367 while (len--) 368 crc = w1_crc8_table[crc ^ *data++]; 369 370 return crc; 371 } 372 EXPORT_SYMBOL_GPL(w1_calc_crc8); 373 374 void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb) 375 { 376 dev->attempts++; 377 if (dev->bus_master->search) 378 dev->bus_master->search(dev->bus_master->data, dev, 379 search_type, cb); 380 else 381 w1_search(dev, search_type, cb); 382 } 383 384 /** 385 * w1_reset_select_slave() - reset and select a slave 386 * @sl: the slave to select 387 * 388 * Resets the bus and then selects the slave by sending either a skip rom 389 * or a rom match. A skip rom is issued if there is only one device 390 * registered on the bus. 391 * The w1 master lock must be held. 392 * 393 * Return: 0=success, anything else=error 394 */ 395 int w1_reset_select_slave(struct w1_slave *sl) 396 { 397 if (w1_reset_bus(sl->master)) 398 return -1; 399 400 if (sl->master->slave_count == 1) 401 w1_write_8(sl->master, W1_SKIP_ROM); 402 else { 403 u8 match[9] = {W1_MATCH_ROM, }; 404 u64 rn = le64_to_cpu(*((u64*)&sl->reg_num)); 405 406 memcpy(&match[1], &rn, 8); 407 w1_write_block(sl->master, match, 9); 408 } 409 return 0; 410 } 411 EXPORT_SYMBOL_GPL(w1_reset_select_slave); 412 413 /** 414 * w1_reset_resume_command() - resume instead of another match ROM 415 * @dev: the master device 416 * 417 * When the workflow with a slave amongst many requires several 418 * successive commands a reset between each, this function is similar 419 * to doing a reset then a match ROM for the last matched ROM. The 420 * advantage being that the matched ROM step is skipped in favor of the 421 * resume command. The slave must support the command of course. 422 * 423 * If the bus has only one slave, traditionnaly the match ROM is skipped 424 * and a "SKIP ROM" is done for efficiency. On multi-slave busses, this 425 * doesn't work of course, but the resume command is the next best thing. 426 * 427 * The w1 master lock must be held. 428 */ 429 int w1_reset_resume_command(struct w1_master *dev) 430 { 431 if (w1_reset_bus(dev)) 432 return -1; 433 434 /* This will make only the last matched slave perform a skip ROM. */ 435 w1_write_8(dev, W1_RESUME_CMD); 436 return 0; 437 } 438 EXPORT_SYMBOL_GPL(w1_reset_resume_command); 439 440 /** 441 * w1_next_pullup() - register for a strong pullup 442 * @dev: the master device 443 * @delay: time in milliseconds 444 * 445 * Put out a strong pull-up of the specified duration after the next write 446 * operation. Not all hardware supports strong pullups. Hardware that 447 * doesn't support strong pullups will sleep for the given time after the 448 * write operation without a strong pullup. This is a one shot request for 449 * the next write, specifying zero will clear a previous request. 450 * The w1 master lock must be held. 451 * 452 * Return: 0=success, anything else=error 453 */ 454 void w1_next_pullup(struct w1_master *dev, int delay) 455 { 456 dev->pullup_duration = delay; 457 } 458 EXPORT_SYMBOL_GPL(w1_next_pullup); 459