xref: /linux/drivers/video/fbdev/tridentfb.c (revision dec1c62e91ba268ab2a6e339d4d7a59287d5eba1)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Frame buffer driver for Trident TGUI, Blade and Image series
4  *
5  * Copyright 2001, 2002 - Jani Monoses   <jani@iv.ro>
6  * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl>
7  *
8  * CREDITS:(in order of appearance)
9  *	skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
10  *	Special thanks ;) to Mattia Crivellini <tia@mclink.it>
11  *	much inspired by the XFree86 4.x Trident driver sources
12  *	by Alan Hourihane the FreeVGA project
13  *	Francesco Salvestrini <salvestrini@users.sf.net> XP support,
14  *	code, suggestions
15  * TODO:
16  *	timing value tweaking so it looks good on every monitor in every mode
17  */
18 
19 #include <linux/module.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/slab.h>
24 
25 #include <linux/delay.h>
26 #include <video/vga.h>
27 #include <video/trident.h>
28 
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 
32 struct tridentfb_par {
33 	void __iomem *io_virt;	/* iospace virtual memory address */
34 	u32 pseudo_pal[16];
35 	int chip_id;
36 	int flatpanel;
37 	void (*init_accel) (struct tridentfb_par *, int, int);
38 	void (*wait_engine) (struct tridentfb_par *);
39 	void (*fill_rect)
40 		(struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
41 	void (*copy_rect)
42 		(struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 	void (*image_blit)
44 		(struct tridentfb_par *par, const char*,
45 		 u32, u32, u32, u32, u32, u32);
46 	unsigned char eng_oper;	/* engine operation... */
47 	bool ddc_registered;
48 	struct i2c_adapter ddc_adapter;
49 	struct i2c_algo_bit_data ddc_algo;
50 };
51 
52 static struct fb_fix_screeninfo tridentfb_fix = {
53 	.id = "Trident",
54 	.type = FB_TYPE_PACKED_PIXELS,
55 	.ypanstep = 1,
56 	.visual = FB_VISUAL_PSEUDOCOLOR,
57 	.accel = FB_ACCEL_NONE,
58 };
59 
60 /* defaults which are normally overriden by user values */
61 
62 /* video mode */
63 static char *mode_option;
64 static int bpp = 8;
65 
66 static int noaccel;
67 
68 static int center;
69 static int stretch;
70 
71 static int fp;
72 static int crt;
73 
74 static int memsize;
75 static int memdiff;
76 static int nativex;
77 
78 module_param(mode_option, charp, 0);
79 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
80 module_param_named(mode, mode_option, charp, 0);
81 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
82 module_param(bpp, int, 0);
83 module_param(center, int, 0);
84 module_param(stretch, int, 0);
85 module_param(noaccel, int, 0);
86 module_param(memsize, int, 0);
87 module_param(memdiff, int, 0);
88 module_param(nativex, int, 0);
89 module_param(fp, int, 0);
90 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
91 module_param(crt, int, 0);
92 MODULE_PARM_DESC(crt, "Define if CRT is connected");
93 
94 static inline int is_oldclock(int id)
95 {
96 	return	(id == TGUI9440) ||
97 		(id == TGUI9660) ||
98 		(id == CYBER9320);
99 }
100 
101 static inline int is_oldprotect(int id)
102 {
103 	return	is_oldclock(id) ||
104 		(id == PROVIDIA9685) ||
105 		(id == CYBER9382) ||
106 		(id == CYBER9385);
107 }
108 
109 static inline int is_blade(int id)
110 {
111 	return	(id == BLADE3D) ||
112 		(id == CYBERBLADEE4) ||
113 		(id == CYBERBLADEi7) ||
114 		(id == CYBERBLADEi7D) ||
115 		(id == CYBERBLADEi1) ||
116 		(id == CYBERBLADEi1D) ||
117 		(id == CYBERBLADEAi1) ||
118 		(id == CYBERBLADEAi1D);
119 }
120 
121 static inline int is_xp(int id)
122 {
123 	return	(id == CYBERBLADEXPAi1) ||
124 		(id == CYBERBLADEXPm8) ||
125 		(id == CYBERBLADEXPm16);
126 }
127 
128 static inline int is3Dchip(int id)
129 {
130 	return	is_blade(id) || is_xp(id) ||
131 		(id == CYBER9397) || (id == CYBER9397DVD) ||
132 		(id == CYBER9520) || (id == CYBER9525DVD) ||
133 		(id == IMAGE975) || (id == IMAGE985);
134 }
135 
136 static inline int iscyber(int id)
137 {
138 	switch (id) {
139 	case CYBER9388:
140 	case CYBER9382:
141 	case CYBER9385:
142 	case CYBER9397:
143 	case CYBER9397DVD:
144 	case CYBER9520:
145 	case CYBER9525DVD:
146 	case CYBERBLADEE4:
147 	case CYBERBLADEi7D:
148 	case CYBERBLADEi1:
149 	case CYBERBLADEi1D:
150 	case CYBERBLADEAi1:
151 	case CYBERBLADEAi1D:
152 	case CYBERBLADEXPAi1:
153 		return 1;
154 
155 	case CYBER9320:
156 	case CYBERBLADEi7:	/* VIA MPV4 integrated version */
157 	default:
158 		/* case CYBERBLDAEXPm8:  Strange */
159 		/* case CYBERBLDAEXPm16: Strange */
160 		return 0;
161 	}
162 }
163 
164 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
165 {
166 	fb_writeb(val, p->io_virt + reg);
167 }
168 
169 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
170 {
171 	return fb_readb(p->io_virt + reg);
172 }
173 
174 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
175 {
176 	fb_writel(v, par->io_virt + r);
177 }
178 
179 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
180 {
181 	return fb_readl(par->io_virt + r);
182 }
183 
184 #define DDC_SDA_TGUI		BIT(0)
185 #define DDC_SCL_TGUI		BIT(1)
186 #define DDC_SCL_DRIVE_TGUI	BIT(2)
187 #define DDC_SDA_DRIVE_TGUI	BIT(3)
188 #define DDC_MASK_TGUI		(DDC_SCL_DRIVE_TGUI | DDC_SDA_DRIVE_TGUI)
189 
190 static void tridentfb_ddc_setscl_tgui(void *data, int val)
191 {
192 	struct tridentfb_par *par = data;
193 	u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
194 
195 	if (val)
196 		reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */
197 	else
198 		reg |= DDC_SCL_DRIVE_TGUI; /* drive low */
199 
200 	vga_mm_wcrt(par->io_virt, I2C, reg);
201 }
202 
203 static void tridentfb_ddc_setsda_tgui(void *data, int val)
204 {
205 	struct tridentfb_par *par = data;
206 	u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
207 
208 	if (val)
209 		reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */
210 	else
211 		reg |= DDC_SDA_DRIVE_TGUI; /* drive low */
212 
213 	vga_mm_wcrt(par->io_virt, I2C, reg);
214 }
215 
216 static int tridentfb_ddc_getsda_tgui(void *data)
217 {
218 	struct tridentfb_par *par = data;
219 
220 	return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
221 }
222 
223 #define DDC_SDA_IN	BIT(0)
224 #define DDC_SCL_OUT	BIT(1)
225 #define DDC_SDA_OUT	BIT(3)
226 #define DDC_SCL_IN	BIT(6)
227 #define DDC_MASK	(DDC_SCL_OUT | DDC_SDA_OUT)
228 
229 static void tridentfb_ddc_setscl(void *data, int val)
230 {
231 	struct tridentfb_par *par = data;
232 	unsigned char reg;
233 
234 	reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
235 	if (val)
236 		reg |= DDC_SCL_OUT;
237 	else
238 		reg &= ~DDC_SCL_OUT;
239 	vga_mm_wcrt(par->io_virt, I2C, reg);
240 }
241 
242 static void tridentfb_ddc_setsda(void *data, int val)
243 {
244 	struct tridentfb_par *par = data;
245 	unsigned char reg;
246 
247 	reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
248 	if (!val)
249 		reg |= DDC_SDA_OUT;
250 	else
251 		reg &= ~DDC_SDA_OUT;
252 	vga_mm_wcrt(par->io_virt, I2C, reg);
253 }
254 
255 static int tridentfb_ddc_getscl(void *data)
256 {
257 	struct tridentfb_par *par = data;
258 
259 	return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
260 }
261 
262 static int tridentfb_ddc_getsda(void *data)
263 {
264 	struct tridentfb_par *par = data;
265 
266 	return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
267 }
268 
269 static int tridentfb_setup_ddc_bus(struct fb_info *info)
270 {
271 	struct tridentfb_par *par = info->par;
272 
273 	strlcpy(par->ddc_adapter.name, info->fix.id,
274 		sizeof(par->ddc_adapter.name));
275 	par->ddc_adapter.owner		= THIS_MODULE;
276 	par->ddc_adapter.class		= I2C_CLASS_DDC;
277 	par->ddc_adapter.algo_data	= &par->ddc_algo;
278 	par->ddc_adapter.dev.parent	= info->device;
279 	if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
280 		par->ddc_algo.setsda	= tridentfb_ddc_setsda_tgui;
281 		par->ddc_algo.setscl	= tridentfb_ddc_setscl_tgui;
282 		par->ddc_algo.getsda	= tridentfb_ddc_getsda_tgui;
283 		/* no getscl */
284 	} else {
285 		par->ddc_algo.setsda	= tridentfb_ddc_setsda;
286 		par->ddc_algo.setscl	= tridentfb_ddc_setscl;
287 		par->ddc_algo.getsda	= tridentfb_ddc_getsda;
288 		par->ddc_algo.getscl	= tridentfb_ddc_getscl;
289 	}
290 	par->ddc_algo.udelay		= 10;
291 	par->ddc_algo.timeout		= 20;
292 	par->ddc_algo.data		= par;
293 
294 	i2c_set_adapdata(&par->ddc_adapter, par);
295 
296 	return i2c_bit_add_bus(&par->ddc_adapter);
297 }
298 
299 /*
300  * Blade specific acceleration.
301  */
302 
303 #define point(x, y) ((y) << 16 | (x))
304 
305 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
306 {
307 	int v1 = (pitch >> 3) << 20;
308 	int tmp = bpp == 24 ? 2 : (bpp >> 4);
309 	int v2 = v1 | (tmp << 29);
310 
311 	writemmr(par, 0x21C0, v2);
312 	writemmr(par, 0x21C4, v2);
313 	writemmr(par, 0x21B8, v2);
314 	writemmr(par, 0x21BC, v2);
315 	writemmr(par, 0x21D0, v1);
316 	writemmr(par, 0x21D4, v1);
317 	writemmr(par, 0x21C8, v1);
318 	writemmr(par, 0x21CC, v1);
319 	writemmr(par, 0x216C, 0);
320 }
321 
322 static void blade_wait_engine(struct tridentfb_par *par)
323 {
324 	while (readmmr(par, STATUS) & 0xFA800000)
325 		cpu_relax();
326 }
327 
328 static void blade_fill_rect(struct tridentfb_par *par,
329 			    u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
330 {
331 	writemmr(par, COLOR, c);
332 	writemmr(par, ROP, rop ? ROP_X : ROP_S);
333 	writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
334 
335 	writemmr(par, DST1, point(x, y));
336 	writemmr(par, DST2, point(x + w - 1, y + h - 1));
337 }
338 
339 static void blade_image_blit(struct tridentfb_par *par, const char *data,
340 			     u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
341 {
342 	unsigned size = ((w + 31) >> 5) * h;
343 
344 	writemmr(par, COLOR, c);
345 	writemmr(par, BGCOLOR, b);
346 	writemmr(par, CMD, 0xa0000000 | 3 << 19);
347 
348 	writemmr(par, DST1, point(x, y));
349 	writemmr(par, DST2, point(x + w - 1, y + h - 1));
350 
351 	iowrite32_rep(par->io_virt + 0x10000, data, size);
352 }
353 
354 static void blade_copy_rect(struct tridentfb_par *par,
355 			    u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
356 {
357 	int direction = 2;
358 	u32 s1 = point(x1, y1);
359 	u32 s2 = point(x1 + w - 1, y1 + h - 1);
360 	u32 d1 = point(x2, y2);
361 	u32 d2 = point(x2 + w - 1, y2 + h - 1);
362 
363 	if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
364 		direction = 0;
365 
366 	writemmr(par, ROP, ROP_S);
367 	writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
368 
369 	writemmr(par, SRC1, direction ? s2 : s1);
370 	writemmr(par, SRC2, direction ? s1 : s2);
371 	writemmr(par, DST1, direction ? d2 : d1);
372 	writemmr(par, DST2, direction ? d1 : d2);
373 }
374 
375 /*
376  * BladeXP specific acceleration functions
377  */
378 
379 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
380 {
381 	unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
382 	int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
383 
384 	switch (pitch << (bpp >> 3)) {
385 	case 8192:
386 	case 512:
387 		x |= 0x00;
388 		break;
389 	case 1024:
390 		x |= 0x04;
391 		break;
392 	case 2048:
393 		x |= 0x08;
394 		break;
395 	case 4096:
396 		x |= 0x0C;
397 		break;
398 	}
399 
400 	t_outb(par, x, 0x2125);
401 
402 	par->eng_oper = x | 0x40;
403 
404 	writemmr(par, 0x2154, v1);
405 	writemmr(par, 0x2150, v1);
406 	t_outb(par, 3, 0x2126);
407 }
408 
409 static void xp_wait_engine(struct tridentfb_par *par)
410 {
411 	int count = 0;
412 	int timeout = 0;
413 
414 	while (t_inb(par, STATUS) & 0x80) {
415 		count++;
416 		if (count == 10000000) {
417 			/* Timeout */
418 			count = 9990000;
419 			timeout++;
420 			if (timeout == 8) {
421 				/* Reset engine */
422 				t_outb(par, 0x00, STATUS);
423 				return;
424 			}
425 		}
426 		cpu_relax();
427 	}
428 }
429 
430 static void xp_fill_rect(struct tridentfb_par *par,
431 			 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
432 {
433 	writemmr(par, 0x2127, ROP_P);
434 	writemmr(par, 0x2158, c);
435 	writemmr(par, DRAWFL, 0x4000);
436 	writemmr(par, OLDDIM, point(h, w));
437 	writemmr(par, OLDDST, point(y, x));
438 	t_outb(par, 0x01, OLDCMD);
439 	t_outb(par, par->eng_oper, 0x2125);
440 }
441 
442 static void xp_copy_rect(struct tridentfb_par *par,
443 			 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
444 {
445 	u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
446 	int direction = 0x0004;
447 
448 	if ((x1 < x2) && (y1 == y2)) {
449 		direction |= 0x0200;
450 		x1_tmp = x1 + w - 1;
451 		x2_tmp = x2 + w - 1;
452 	} else {
453 		x1_tmp = x1;
454 		x2_tmp = x2;
455 	}
456 
457 	if (y1 < y2) {
458 		direction |= 0x0100;
459 		y1_tmp = y1 + h - 1;
460 		y2_tmp = y2 + h - 1;
461 	} else {
462 		y1_tmp = y1;
463 		y2_tmp = y2;
464 	}
465 
466 	writemmr(par, DRAWFL, direction);
467 	t_outb(par, ROP_S, 0x2127);
468 	writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
469 	writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
470 	writemmr(par, OLDDIM, point(h, w));
471 	t_outb(par, 0x01, OLDCMD);
472 }
473 
474 /*
475  * Image specific acceleration functions
476  */
477 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
478 {
479 	int tmp = bpp == 24 ? 2: (bpp >> 4);
480 
481 	writemmr(par, 0x2120, 0xF0000000);
482 	writemmr(par, 0x2120, 0x40000000 | tmp);
483 	writemmr(par, 0x2120, 0x80000000);
484 	writemmr(par, 0x2144, 0x00000000);
485 	writemmr(par, 0x2148, 0x00000000);
486 	writemmr(par, 0x2150, 0x00000000);
487 	writemmr(par, 0x2154, 0x00000000);
488 	writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
489 	writemmr(par, 0x216C, 0x00000000);
490 	writemmr(par, 0x2170, 0x00000000);
491 	writemmr(par, 0x217C, 0x00000000);
492 	writemmr(par, 0x2120, 0x10000000);
493 	writemmr(par, 0x2130, (2047 << 16) | 2047);
494 }
495 
496 static void image_wait_engine(struct tridentfb_par *par)
497 {
498 	while (readmmr(par, 0x2164) & 0xF0000000)
499 		cpu_relax();
500 }
501 
502 static void image_fill_rect(struct tridentfb_par *par,
503 			    u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
504 {
505 	writemmr(par, 0x2120, 0x80000000);
506 	writemmr(par, 0x2120, 0x90000000 | ROP_S);
507 
508 	writemmr(par, 0x2144, c);
509 
510 	writemmr(par, DST1, point(x, y));
511 	writemmr(par, DST2, point(x + w - 1, y + h - 1));
512 
513 	writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
514 }
515 
516 static void image_copy_rect(struct tridentfb_par *par,
517 			    u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
518 {
519 	int direction = 0x4;
520 	u32 s1 = point(x1, y1);
521 	u32 s2 = point(x1 + w - 1, y1 + h - 1);
522 	u32 d1 = point(x2, y2);
523 	u32 d2 = point(x2 + w - 1, y2 + h - 1);
524 
525 	if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
526 		direction = 0;
527 
528 	writemmr(par, 0x2120, 0x80000000);
529 	writemmr(par, 0x2120, 0x90000000 | ROP_S);
530 
531 	writemmr(par, SRC1, direction ? s2 : s1);
532 	writemmr(par, SRC2, direction ? s1 : s2);
533 	writemmr(par, DST1, direction ? d2 : d1);
534 	writemmr(par, DST2, direction ? d1 : d2);
535 	writemmr(par, 0x2124,
536 		 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
537 }
538 
539 /*
540  * TGUI 9440/96XX acceleration
541  */
542 
543 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
544 {
545 	unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
546 
547 	/* disable clipping */
548 	writemmr(par, 0x2148, 0);
549 	writemmr(par, 0x214C, point(4095, 2047));
550 
551 	switch ((pitch * bpp) / 8) {
552 	case 8192:
553 	case 512:
554 		x |= 0x00;
555 		break;
556 	case 1024:
557 		x |= 0x04;
558 		break;
559 	case 2048:
560 		x |= 0x08;
561 		break;
562 	case 4096:
563 		x |= 0x0C;
564 		break;
565 	}
566 
567 	fb_writew(x, par->io_virt + 0x2122);
568 }
569 
570 static void tgui_fill_rect(struct tridentfb_par *par,
571 			   u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
572 {
573 	t_outb(par, ROP_P, 0x2127);
574 	writemmr(par, OLDCLR, c);
575 	writemmr(par, DRAWFL, 0x4020);
576 	writemmr(par, OLDDIM, point(w - 1, h - 1));
577 	writemmr(par, OLDDST, point(x, y));
578 	t_outb(par, 1, OLDCMD);
579 }
580 
581 static void tgui_copy_rect(struct tridentfb_par *par,
582 			   u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
583 {
584 	int flags = 0;
585 	u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
586 
587 	if ((x1 < x2) && (y1 == y2)) {
588 		flags |= 0x0200;
589 		x1_tmp = x1 + w - 1;
590 		x2_tmp = x2 + w - 1;
591 	} else {
592 		x1_tmp = x1;
593 		x2_tmp = x2;
594 	}
595 
596 	if (y1 < y2) {
597 		flags |= 0x0100;
598 		y1_tmp = y1 + h - 1;
599 		y2_tmp = y2 + h - 1;
600 	} else {
601 		y1_tmp = y1;
602 		y2_tmp = y2;
603 	}
604 
605 	writemmr(par, DRAWFL, 0x4 | flags);
606 	t_outb(par, ROP_S, 0x2127);
607 	writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
608 	writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
609 	writemmr(par, OLDDIM, point(w - 1, h - 1));
610 	t_outb(par, 1, OLDCMD);
611 }
612 
613 /*
614  * Accel functions called by the upper layers
615  */
616 static void tridentfb_fillrect(struct fb_info *info,
617 			       const struct fb_fillrect *fr)
618 {
619 	struct tridentfb_par *par = info->par;
620 	int col;
621 
622 	if (info->flags & FBINFO_HWACCEL_DISABLED) {
623 		cfb_fillrect(info, fr);
624 		return;
625 	}
626 	if (info->var.bits_per_pixel == 8) {
627 		col = fr->color;
628 		col |= col << 8;
629 		col |= col << 16;
630 	} else
631 		col = ((u32 *)(info->pseudo_palette))[fr->color];
632 
633 	par->wait_engine(par);
634 	par->fill_rect(par, fr->dx, fr->dy, fr->width,
635 		       fr->height, col, fr->rop);
636 }
637 
638 static void tridentfb_imageblit(struct fb_info *info,
639 				const struct fb_image *img)
640 {
641 	struct tridentfb_par *par = info->par;
642 	int col, bgcol;
643 
644 	if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
645 		cfb_imageblit(info, img);
646 		return;
647 	}
648 	if (info->var.bits_per_pixel == 8) {
649 		col = img->fg_color;
650 		col |= col << 8;
651 		col |= col << 16;
652 		bgcol = img->bg_color;
653 		bgcol |= bgcol << 8;
654 		bgcol |= bgcol << 16;
655 	} else {
656 		col = ((u32 *)(info->pseudo_palette))[img->fg_color];
657 		bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
658 	}
659 
660 	par->wait_engine(par);
661 	if (par->image_blit)
662 		par->image_blit(par, img->data, img->dx, img->dy,
663 				img->width, img->height, col, bgcol);
664 	else
665 		cfb_imageblit(info, img);
666 }
667 
668 static void tridentfb_copyarea(struct fb_info *info,
669 			       const struct fb_copyarea *ca)
670 {
671 	struct tridentfb_par *par = info->par;
672 
673 	if (info->flags & FBINFO_HWACCEL_DISABLED) {
674 		cfb_copyarea(info, ca);
675 		return;
676 	}
677 	par->wait_engine(par);
678 	par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
679 		       ca->width, ca->height);
680 }
681 
682 static int tridentfb_sync(struct fb_info *info)
683 {
684 	struct tridentfb_par *par = info->par;
685 
686 	if (!(info->flags & FBINFO_HWACCEL_DISABLED))
687 		par->wait_engine(par);
688 	return 0;
689 }
690 
691 /*
692  * Hardware access functions
693  */
694 
695 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
696 {
697 	return vga_mm_rcrt(par->io_virt, reg);
698 }
699 
700 static inline void write3X4(struct tridentfb_par *par, int reg,
701 			    unsigned char val)
702 {
703 	vga_mm_wcrt(par->io_virt, reg, val);
704 }
705 
706 static inline unsigned char read3CE(struct tridentfb_par *par,
707 				    unsigned char reg)
708 {
709 	return vga_mm_rgfx(par->io_virt, reg);
710 }
711 
712 static inline void writeAttr(struct tridentfb_par *par, int reg,
713 			     unsigned char val)
714 {
715 	fb_readb(par->io_virt + VGA_IS1_RC);	/* flip-flop to index */
716 	vga_mm_wattr(par->io_virt, reg, val);
717 }
718 
719 static inline void write3CE(struct tridentfb_par *par, int reg,
720 			    unsigned char val)
721 {
722 	vga_mm_wgfx(par->io_virt, reg, val);
723 }
724 
725 static void enable_mmio(struct tridentfb_par *par)
726 {
727 	/* Goto New Mode */
728 	vga_io_rseq(0x0B);
729 
730 	/* Unprotect registers */
731 	vga_io_wseq(NewMode1, 0x80);
732 	if (!is_oldprotect(par->chip_id))
733 		vga_io_wseq(Protection, 0x92);
734 
735 	/* Enable MMIO */
736 	outb(PCIReg, 0x3D4);
737 	outb(inb(0x3D5) | 0x01, 0x3D5);
738 }
739 
740 static void disable_mmio(struct tridentfb_par *par)
741 {
742 	/* Goto New Mode */
743 	vga_mm_rseq(par->io_virt, 0x0B);
744 
745 	/* Unprotect registers */
746 	vga_mm_wseq(par->io_virt, NewMode1, 0x80);
747 	if (!is_oldprotect(par->chip_id))
748 		vga_mm_wseq(par->io_virt, Protection, 0x92);
749 
750 	/* Disable MMIO */
751 	t_outb(par, PCIReg, 0x3D4);
752 	t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
753 }
754 
755 static inline void crtc_unlock(struct tridentfb_par *par)
756 {
757 	write3X4(par, VGA_CRTC_V_SYNC_END,
758 		 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
759 }
760 
761 /*  Return flat panel's maximum x resolution */
762 static int get_nativex(struct tridentfb_par *par)
763 {
764 	int x, y, tmp;
765 
766 	if (nativex)
767 		return nativex;
768 
769 	tmp = (read3CE(par, VertStretch) >> 4) & 3;
770 
771 	switch (tmp) {
772 	case 0:
773 		x = 1280; y = 1024;
774 		break;
775 	case 2:
776 		x = 1024; y = 768;
777 		break;
778 	case 3:
779 		x = 800; y = 600;
780 		break;
781 	case 1:
782 	default:
783 		x = 640;  y = 480;
784 		break;
785 	}
786 
787 	output("%dx%d flat panel found\n", x, y);
788 	return x;
789 }
790 
791 /* Set pitch */
792 static inline void set_lwidth(struct tridentfb_par *par, int width)
793 {
794 	write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
795 	/* chips older than TGUI9660 have only 1 width bit in AddColReg */
796 	/* touching the other one breaks I2C/DDC */
797 	if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
798 		write3X4(par, AddColReg,
799 		     (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
800 	else
801 		write3X4(par, AddColReg,
802 		     (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
803 }
804 
805 /* For resolutions smaller than FP resolution stretch */
806 static void screen_stretch(struct tridentfb_par *par)
807 {
808 	if (par->chip_id != CYBERBLADEXPAi1)
809 		write3CE(par, BiosReg, 0);
810 	else
811 		write3CE(par, BiosReg, 8);
812 	write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
813 	write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
814 }
815 
816 /* For resolutions smaller than FP resolution center */
817 static inline void screen_center(struct tridentfb_par *par)
818 {
819 	write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
820 	write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
821 }
822 
823 /* Address of first shown pixel in display memory */
824 static void set_screen_start(struct tridentfb_par *par, int base)
825 {
826 	u8 tmp;
827 	write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
828 	write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
829 	tmp = read3X4(par, CRTCModuleTest) & 0xDF;
830 	write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
831 	tmp = read3X4(par, CRTHiOrd) & 0xF8;
832 	write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
833 }
834 
835 /* Set dotclock frequency */
836 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
837 {
838 	int m, n, k;
839 	unsigned long fi, d, di;
840 	unsigned char best_m = 0, best_n = 0, best_k = 0;
841 	unsigned char hi, lo;
842 	unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
843 
844 	d = 20000;
845 	for (k = shift; k >= 0; k--)
846 		for (m = 1; m < 32; m++) {
847 			n = ((m + 2) << shift) - 8;
848 			for (n = (n < 0 ? 0 : n); n < 122; n++) {
849 				fi = ((14318l * (n + 8)) / (m + 2)) >> k;
850 				di = abs(fi - freq);
851 				if (di < d || (di == d && k == best_k)) {
852 					d = di;
853 					best_n = n;
854 					best_m = m;
855 					best_k = k;
856 				}
857 				if (fi > freq)
858 					break;
859 			}
860 		}
861 
862 	if (is_oldclock(par->chip_id)) {
863 		lo = best_n | (best_m << 7);
864 		hi = (best_m >> 1) | (best_k << 4);
865 	} else {
866 		lo = best_n;
867 		hi = best_m | (best_k << 6);
868 	}
869 
870 	if (is3Dchip(par->chip_id)) {
871 		vga_mm_wseq(par->io_virt, ClockHigh, hi);
872 		vga_mm_wseq(par->io_virt, ClockLow, lo);
873 	} else {
874 		t_outb(par, lo, 0x43C8);
875 		t_outb(par, hi, 0x43C9);
876 	}
877 	debug("VCLK = %X %X\n", hi, lo);
878 }
879 
880 /* Set number of lines for flat panels*/
881 static void set_number_of_lines(struct tridentfb_par *par, int lines)
882 {
883 	int tmp = read3CE(par, CyberEnhance) & 0x8F;
884 	if (lines > 1024)
885 		tmp |= 0x50;
886 	else if (lines > 768)
887 		tmp |= 0x30;
888 	else if (lines > 600)
889 		tmp |= 0x20;
890 	else if (lines > 480)
891 		tmp |= 0x10;
892 	write3CE(par, CyberEnhance, tmp);
893 }
894 
895 /*
896  * If we see that FP is active we assume we have one.
897  * Otherwise we have a CRT display. User can override.
898  */
899 static int is_flatpanel(struct tridentfb_par *par)
900 {
901 	if (fp)
902 		return 1;
903 	if (crt || !iscyber(par->chip_id))
904 		return 0;
905 	return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
906 }
907 
908 /* Try detecting the video memory size */
909 static unsigned int get_memsize(struct tridentfb_par *par)
910 {
911 	unsigned char tmp, tmp2;
912 	unsigned int k;
913 
914 	/* If memory size provided by user */
915 	if (memsize)
916 		k = memsize * Kb;
917 	else
918 		switch (par->chip_id) {
919 		case CYBER9525DVD:
920 			k = 2560 * Kb;
921 			break;
922 		default:
923 			tmp = read3X4(par, SPR) & 0x0F;
924 			switch (tmp) {
925 
926 			case 0x01:
927 				k = 512 * Kb;
928 				break;
929 			case 0x02:
930 				k = 6 * Mb;	/* XP */
931 				break;
932 			case 0x03:
933 				k = 1 * Mb;
934 				break;
935 			case 0x04:
936 				k = 8 * Mb;
937 				break;
938 			case 0x06:
939 				k = 10 * Mb;	/* XP */
940 				break;
941 			case 0x07:
942 				k = 2 * Mb;
943 				break;
944 			case 0x08:
945 				k = 12 * Mb;	/* XP */
946 				break;
947 			case 0x0A:
948 				k = 14 * Mb;	/* XP */
949 				break;
950 			case 0x0C:
951 				k = 16 * Mb;	/* XP */
952 				break;
953 			case 0x0E:		/* XP */
954 
955 				tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
956 				switch (tmp2) {
957 				case 0x00:
958 					k = 20 * Mb;
959 					break;
960 				case 0x01:
961 					k = 24 * Mb;
962 					break;
963 				case 0x10:
964 					k = 28 * Mb;
965 					break;
966 				case 0x11:
967 					k = 32 * Mb;
968 					break;
969 				default:
970 					k = 1 * Mb;
971 					break;
972 				}
973 				break;
974 
975 			case 0x0F:
976 				k = 4 * Mb;
977 				break;
978 			default:
979 				k = 1 * Mb;
980 				break;
981 			}
982 		}
983 
984 	k -= memdiff * Kb;
985 	output("framebuffer size = %d Kb\n", k / Kb);
986 	return k;
987 }
988 
989 /* See if we can handle the video mode described in var */
990 static int tridentfb_check_var(struct fb_var_screeninfo *var,
991 			       struct fb_info *info)
992 {
993 	struct tridentfb_par *par = info->par;
994 	int bpp = var->bits_per_pixel;
995 	int line_length;
996 	int ramdac = 230000; /* 230MHz for most 3D chips */
997 	debug("enter\n");
998 
999 	if (!var->pixclock)
1000 		return -EINVAL;
1001 
1002 	/* check color depth */
1003 	if (bpp == 24)
1004 		bpp = var->bits_per_pixel = 32;
1005 	if (bpp != 8 && bpp != 16 && bpp != 32)
1006 		return -EINVAL;
1007 	if (par->chip_id == TGUI9440 && bpp == 32)
1008 		return -EINVAL;
1009 	/* check whether resolution fits on panel and in memory */
1010 	if (par->flatpanel && nativex && var->xres > nativex)
1011 		return -EINVAL;
1012 	/* various resolution checks */
1013 	var->xres = (var->xres + 7) & ~0x7;
1014 	if (var->xres > var->xres_virtual)
1015 		var->xres_virtual = var->xres;
1016 	if (var->yres > var->yres_virtual)
1017 		var->yres_virtual = var->yres;
1018 	if (var->xres_virtual > 4095 || var->yres > 2048)
1019 		return -EINVAL;
1020 	/* prevent from position overflow for acceleration */
1021 	if (var->yres_virtual > 0xffff)
1022 		return -EINVAL;
1023 	line_length = var->xres_virtual * bpp / 8;
1024 
1025 	if (!is3Dchip(par->chip_id) &&
1026 	    !(info->flags & FBINFO_HWACCEL_DISABLED)) {
1027 		/* acceleration requires line length to be power of 2 */
1028 		if (line_length <= 512)
1029 			var->xres_virtual = 512 * 8 / bpp;
1030 		else if (line_length <= 1024)
1031 			var->xres_virtual = 1024 * 8 / bpp;
1032 		else if (line_length <= 2048)
1033 			var->xres_virtual = 2048 * 8 / bpp;
1034 		else if (line_length <= 4096)
1035 			var->xres_virtual = 4096 * 8 / bpp;
1036 		else if (line_length <= 8192)
1037 			var->xres_virtual = 8192 * 8 / bpp;
1038 		else
1039 			return -EINVAL;
1040 
1041 		line_length = var->xres_virtual * bpp / 8;
1042 	}
1043 
1044 	/* datasheet specifies how to set panning only up to 4 MB */
1045 	if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
1046 		var->yres_virtual = ((4 << 20) / line_length) + var->yres;
1047 
1048 	if (line_length * var->yres_virtual > info->fix.smem_len)
1049 		return -EINVAL;
1050 
1051 	switch (bpp) {
1052 	case 8:
1053 		var->red.offset = 0;
1054 		var->red.length = 8;
1055 		var->green = var->red;
1056 		var->blue = var->red;
1057 		break;
1058 	case 16:
1059 		var->red.offset = 11;
1060 		var->green.offset = 5;
1061 		var->blue.offset = 0;
1062 		var->red.length = 5;
1063 		var->green.length = 6;
1064 		var->blue.length = 5;
1065 		break;
1066 	case 32:
1067 		var->red.offset = 16;
1068 		var->green.offset = 8;
1069 		var->blue.offset = 0;
1070 		var->red.length = 8;
1071 		var->green.length = 8;
1072 		var->blue.length = 8;
1073 		break;
1074 	default:
1075 		return -EINVAL;
1076 	}
1077 
1078 	if (is_xp(par->chip_id))
1079 		ramdac = 350000;
1080 
1081 	switch (par->chip_id) {
1082 	case TGUI9440:
1083 		ramdac = (bpp >= 16) ? 45000 : 90000;
1084 		break;
1085 	case CYBER9320:
1086 	case TGUI9660:
1087 		ramdac = 135000;
1088 		break;
1089 	case PROVIDIA9685:
1090 	case CYBER9388:
1091 	case CYBER9382:
1092 	case CYBER9385:
1093 		ramdac = 170000;
1094 		break;
1095 	}
1096 
1097 	/* The clock is doubled for 32 bpp */
1098 	if (bpp == 32)
1099 		ramdac /= 2;
1100 
1101 	if (PICOS2KHZ(var->pixclock) > ramdac)
1102 		return -EINVAL;
1103 
1104 	debug("exit\n");
1105 
1106 	return 0;
1107 
1108 }
1109 
1110 /* Pan the display */
1111 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
1112 				 struct fb_info *info)
1113 {
1114 	struct tridentfb_par *par = info->par;
1115 	unsigned int offset;
1116 
1117 	debug("enter\n");
1118 	offset = (var->xoffset + (var->yoffset * info->var.xres_virtual))
1119 		* info->var.bits_per_pixel / 32;
1120 	set_screen_start(par, offset);
1121 	debug("exit\n");
1122 	return 0;
1123 }
1124 
1125 static inline void shadowmode_on(struct tridentfb_par *par)
1126 {
1127 	write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1128 }
1129 
1130 static inline void shadowmode_off(struct tridentfb_par *par)
1131 {
1132 	write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1133 }
1134 
1135 /* Set the hardware to the requested video mode */
1136 static int tridentfb_set_par(struct fb_info *info)
1137 {
1138 	struct tridentfb_par *par = info->par;
1139 	u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1140 	u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1141 	struct fb_var_screeninfo *var = &info->var;
1142 	int bpp = var->bits_per_pixel;
1143 	unsigned char tmp;
1144 	unsigned long vclk;
1145 
1146 	debug("enter\n");
1147 	hdispend = var->xres / 8 - 1;
1148 	hsyncstart = (var->xres + var->right_margin) / 8;
1149 	hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
1150 	htotal = (var->xres + var->left_margin + var->right_margin +
1151 		  var->hsync_len) / 8 - 5;
1152 	hblankstart = hdispend + 1;
1153 	hblankend = htotal + 3;
1154 
1155 	vdispend = var->yres - 1;
1156 	vsyncstart = var->yres + var->lower_margin;
1157 	vsyncend = vsyncstart + var->vsync_len;
1158 	vtotal = var->upper_margin + vsyncend - 2;
1159 	vblankstart = vdispend + 1;
1160 	vblankend = vtotal;
1161 
1162 	if (info->var.vmode & FB_VMODE_INTERLACED) {
1163 		vtotal /= 2;
1164 		vdispend /= 2;
1165 		vsyncstart /= 2;
1166 		vsyncend /= 2;
1167 		vblankstart /= 2;
1168 		vblankend /= 2;
1169 	}
1170 
1171 	enable_mmio(par);
1172 	crtc_unlock(par);
1173 	write3CE(par, CyberControl, 8);
1174 	tmp = 0xEB;
1175 	if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1176 		tmp &= ~0x40;
1177 	if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1178 		tmp &= ~0x80;
1179 
1180 	if (par->flatpanel && var->xres < nativex) {
1181 		/*
1182 		 * on flat panels with native size larger
1183 		 * than requested resolution decide whether
1184 		 * we stretch or center
1185 		 */
1186 		t_outb(par, tmp | 0xC0, VGA_MIS_W);
1187 
1188 		shadowmode_on(par);
1189 
1190 		if (center)
1191 			screen_center(par);
1192 		else if (stretch)
1193 			screen_stretch(par);
1194 
1195 	} else {
1196 		t_outb(par, tmp, VGA_MIS_W);
1197 		write3CE(par, CyberControl, 8);
1198 	}
1199 
1200 	/* vertical timing values */
1201 	write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1202 	write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1203 	write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1204 	write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1205 	write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1206 	write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1207 
1208 	/* horizontal timing values */
1209 	write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1210 	write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1211 	write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1212 	write3X4(par, VGA_CRTC_H_SYNC_END,
1213 		 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1214 	write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1215 	write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1216 
1217 	/* higher bits of vertical timing values */
1218 	tmp = 0x10;
1219 	if (vtotal & 0x100) tmp |= 0x01;
1220 	if (vdispend & 0x100) tmp |= 0x02;
1221 	if (vsyncstart & 0x100) tmp |= 0x04;
1222 	if (vblankstart & 0x100) tmp |= 0x08;
1223 
1224 	if (vtotal & 0x200) tmp |= 0x20;
1225 	if (vdispend & 0x200) tmp |= 0x40;
1226 	if (vsyncstart & 0x200) tmp |= 0x80;
1227 	write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1228 
1229 	tmp = read3X4(par, CRTHiOrd) & 0x07;
1230 	tmp |= 0x08;	/* line compare bit 10 */
1231 	if (vtotal & 0x400) tmp |= 0x80;
1232 	if (vblankstart & 0x400) tmp |= 0x40;
1233 	if (vsyncstart & 0x400) tmp |= 0x20;
1234 	if (vdispend & 0x400) tmp |= 0x10;
1235 	write3X4(par, CRTHiOrd, tmp);
1236 
1237 	tmp = (htotal >> 8) & 0x01;
1238 	tmp |= (hdispend >> 7) & 0x02;
1239 	tmp |= (hsyncstart >> 5) & 0x08;
1240 	tmp |= (hblankstart >> 4) & 0x10;
1241 	write3X4(par, HorizOverflow, tmp);
1242 
1243 	tmp = 0x40;
1244 	if (vblankstart & 0x200) tmp |= 0x20;
1245 //FIXME	if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80;  /* double scan for 200 line modes */
1246 	write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1247 
1248 	write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1249 	write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1250 	write3X4(par, VGA_CRTC_MODE, 0xC3);
1251 
1252 	write3X4(par, LinearAddReg, 0x20);	/* enable linear addressing */
1253 
1254 	tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1255 	/* enable access extended memory */
1256 	write3X4(par, CRTCModuleTest, tmp);
1257 	tmp = read3CE(par, MiscIntContReg) & ~0x4;
1258 	if (info->var.vmode & FB_VMODE_INTERLACED)
1259 		tmp |= 0x4;
1260 	write3CE(par, MiscIntContReg, tmp);
1261 
1262 	/* enable GE for text acceleration */
1263 	write3X4(par, GraphEngReg, 0x80);
1264 
1265 	switch (bpp) {
1266 	case 8:
1267 		tmp = 0x00;
1268 		break;
1269 	case 16:
1270 		tmp = 0x05;
1271 		break;
1272 	case 24:
1273 		tmp = 0x29;
1274 		break;
1275 	case 32:
1276 		tmp = 0x09;
1277 		break;
1278 	}
1279 
1280 	write3X4(par, PixelBusReg, tmp);
1281 
1282 	tmp = read3X4(par, DRAMControl);
1283 	if (!is_oldprotect(par->chip_id))
1284 		tmp |= 0x10;
1285 	if (iscyber(par->chip_id))
1286 		tmp |= 0x20;
1287 	write3X4(par, DRAMControl, tmp);	/* both IO, linear enable */
1288 
1289 	write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1290 	if (!is_xp(par->chip_id))
1291 		write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1292 	/* MMIO & PCI read and write burst enable */
1293 	if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1294 		write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1295 
1296 	vga_mm_wseq(par->io_virt, 0, 3);
1297 	vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1298 	/* enable 4 maps because needed in chain4 mode */
1299 	vga_mm_wseq(par->io_virt, 2, 0x0F);
1300 	vga_mm_wseq(par->io_virt, 3, 0);
1301 	vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1302 
1303 	/* convert from picoseconds to kHz */
1304 	vclk = PICOS2KHZ(info->var.pixclock);
1305 
1306 	/* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1307 	tmp = read3CE(par, MiscExtFunc) & 0xF0;
1308 	if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1309 		tmp |= 8;
1310 		vclk *= 2;
1311 	}
1312 	set_vclk(par, vclk);
1313 	write3CE(par, MiscExtFunc, tmp | 0x12);
1314 	write3CE(par, 0x5, 0x40);	/* no CGA compat, allow 256 col */
1315 	write3CE(par, 0x6, 0x05);	/* graphics mode */
1316 	write3CE(par, 0x7, 0x0F);	/* planes? */
1317 
1318 	/* graphics mode and support 256 color modes */
1319 	writeAttr(par, 0x10, 0x41);
1320 	writeAttr(par, 0x12, 0x0F);	/* planes */
1321 	writeAttr(par, 0x13, 0);	/* horizontal pel panning */
1322 
1323 	/* colors */
1324 	for (tmp = 0; tmp < 0x10; tmp++)
1325 		writeAttr(par, tmp, tmp);
1326 	fb_readb(par->io_virt + VGA_IS1_RC);	/* flip-flop to index */
1327 	t_outb(par, 0x20, VGA_ATT_W);		/* enable attr */
1328 
1329 	switch (bpp) {
1330 	case 8:
1331 		tmp = 0;
1332 		break;
1333 	case 16:
1334 		tmp = 0x30;
1335 		break;
1336 	case 24:
1337 	case 32:
1338 		tmp = 0xD0;
1339 		break;
1340 	}
1341 
1342 	t_inb(par, VGA_PEL_IW);
1343 	t_inb(par, VGA_PEL_MSK);
1344 	t_inb(par, VGA_PEL_MSK);
1345 	t_inb(par, VGA_PEL_MSK);
1346 	t_inb(par, VGA_PEL_MSK);
1347 	t_outb(par, tmp, VGA_PEL_MSK);
1348 	t_inb(par, VGA_PEL_IW);
1349 
1350 	if (par->flatpanel)
1351 		set_number_of_lines(par, info->var.yres);
1352 	info->fix.line_length = info->var.xres_virtual * bpp / 8;
1353 	set_lwidth(par, info->fix.line_length / 8);
1354 
1355 	if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1356 		par->init_accel(par, info->var.xres_virtual, bpp);
1357 
1358 	info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1359 	info->cmap.len = (bpp == 8) ? 256 : 16;
1360 	debug("exit\n");
1361 	return 0;
1362 }
1363 
1364 /* Set one color register */
1365 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1366 			       unsigned blue, unsigned transp,
1367 			       struct fb_info *info)
1368 {
1369 	int bpp = info->var.bits_per_pixel;
1370 	struct tridentfb_par *par = info->par;
1371 
1372 	if (regno >= info->cmap.len)
1373 		return 1;
1374 
1375 	if (bpp == 8) {
1376 		t_outb(par, 0xFF, VGA_PEL_MSK);
1377 		t_outb(par, regno, VGA_PEL_IW);
1378 
1379 		t_outb(par, red >> 10, VGA_PEL_D);
1380 		t_outb(par, green >> 10, VGA_PEL_D);
1381 		t_outb(par, blue >> 10, VGA_PEL_D);
1382 
1383 	} else if (regno < 16) {
1384 		if (bpp == 16) {	/* RGB 565 */
1385 			u32 col;
1386 
1387 			col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1388 				((blue & 0xF800) >> 11);
1389 			col |= col << 16;
1390 			((u32 *)(info->pseudo_palette))[regno] = col;
1391 		} else if (bpp == 32)		/* ARGB 8888 */
1392 			((u32 *)info->pseudo_palette)[regno] =
1393 				((transp & 0xFF00) << 16)	|
1394 				((red & 0xFF00) << 8)		|
1395 				((green & 0xFF00))		|
1396 				((blue & 0xFF00) >> 8);
1397 	}
1398 
1399 	return 0;
1400 }
1401 
1402 /* Try blanking the screen. For flat panels it does nothing */
1403 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1404 {
1405 	unsigned char PMCont, DPMSCont;
1406 	struct tridentfb_par *par = info->par;
1407 
1408 	debug("enter\n");
1409 	if (par->flatpanel)
1410 		return 0;
1411 	t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1412 	PMCont = t_inb(par, 0x83C6) & 0xFC;
1413 	DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1414 	switch (blank_mode) {
1415 	case FB_BLANK_UNBLANK:
1416 		/* Screen: On, HSync: On, VSync: On */
1417 	case FB_BLANK_NORMAL:
1418 		/* Screen: Off, HSync: On, VSync: On */
1419 		PMCont |= 0x03;
1420 		DPMSCont |= 0x00;
1421 		break;
1422 	case FB_BLANK_HSYNC_SUSPEND:
1423 		/* Screen: Off, HSync: Off, VSync: On */
1424 		PMCont |= 0x02;
1425 		DPMSCont |= 0x01;
1426 		break;
1427 	case FB_BLANK_VSYNC_SUSPEND:
1428 		/* Screen: Off, HSync: On, VSync: Off */
1429 		PMCont |= 0x02;
1430 		DPMSCont |= 0x02;
1431 		break;
1432 	case FB_BLANK_POWERDOWN:
1433 		/* Screen: Off, HSync: Off, VSync: Off */
1434 		PMCont |= 0x00;
1435 		DPMSCont |= 0x03;
1436 		break;
1437 	}
1438 
1439 	write3CE(par, PowerStatus, DPMSCont);
1440 	t_outb(par, 4, 0x83C8);
1441 	t_outb(par, PMCont, 0x83C6);
1442 
1443 	debug("exit\n");
1444 
1445 	/* let fbcon do a softblank for us */
1446 	return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1447 }
1448 
1449 static const struct fb_ops tridentfb_ops = {
1450 	.owner = THIS_MODULE,
1451 	.fb_setcolreg = tridentfb_setcolreg,
1452 	.fb_pan_display = tridentfb_pan_display,
1453 	.fb_blank = tridentfb_blank,
1454 	.fb_check_var = tridentfb_check_var,
1455 	.fb_set_par = tridentfb_set_par,
1456 	.fb_fillrect = tridentfb_fillrect,
1457 	.fb_copyarea = tridentfb_copyarea,
1458 	.fb_imageblit = tridentfb_imageblit,
1459 	.fb_sync = tridentfb_sync,
1460 };
1461 
1462 static int trident_pci_probe(struct pci_dev *dev,
1463 			     const struct pci_device_id *id)
1464 {
1465 	int err;
1466 	unsigned char revision;
1467 	struct fb_info *info;
1468 	struct tridentfb_par *default_par;
1469 	int chip3D;
1470 	int chip_id;
1471 	bool found = false;
1472 
1473 	err = pci_enable_device(dev);
1474 	if (err)
1475 		return err;
1476 
1477 	info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1478 	if (!info)
1479 		return -ENOMEM;
1480 	default_par = info->par;
1481 
1482 	chip_id = id->device;
1483 
1484 	/* If PCI id is 0x9660 then further detect chip type */
1485 
1486 	if (chip_id == TGUI9660) {
1487 		revision = vga_io_rseq(RevisionID);
1488 
1489 		switch (revision) {
1490 		case 0x21:
1491 			chip_id = PROVIDIA9685;
1492 			break;
1493 		case 0x22:
1494 		case 0x23:
1495 			chip_id = CYBER9397;
1496 			break;
1497 		case 0x2A:
1498 			chip_id = CYBER9397DVD;
1499 			break;
1500 		case 0x30:
1501 		case 0x33:
1502 		case 0x34:
1503 		case 0x35:
1504 		case 0x38:
1505 		case 0x3A:
1506 		case 0xB3:
1507 			chip_id = CYBER9385;
1508 			break;
1509 		case 0x40 ... 0x43:
1510 			chip_id = CYBER9382;
1511 			break;
1512 		case 0x4A:
1513 			chip_id = CYBER9388;
1514 			break;
1515 		default:
1516 			break;
1517 		}
1518 	}
1519 
1520 	chip3D = is3Dchip(chip_id);
1521 
1522 	if (is_xp(chip_id)) {
1523 		default_par->init_accel = xp_init_accel;
1524 		default_par->wait_engine = xp_wait_engine;
1525 		default_par->fill_rect = xp_fill_rect;
1526 		default_par->copy_rect = xp_copy_rect;
1527 		tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1528 	} else if (is_blade(chip_id)) {
1529 		default_par->init_accel = blade_init_accel;
1530 		default_par->wait_engine = blade_wait_engine;
1531 		default_par->fill_rect = blade_fill_rect;
1532 		default_par->copy_rect = blade_copy_rect;
1533 		default_par->image_blit = blade_image_blit;
1534 		tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1535 	} else if (chip3D) {			/* 3DImage family left */
1536 		default_par->init_accel = image_init_accel;
1537 		default_par->wait_engine = image_wait_engine;
1538 		default_par->fill_rect = image_fill_rect;
1539 		default_par->copy_rect = image_copy_rect;
1540 		tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1541 	} else { 				/* TGUI 9440/96XX family */
1542 		default_par->init_accel = tgui_init_accel;
1543 		default_par->wait_engine = xp_wait_engine;
1544 		default_par->fill_rect = tgui_fill_rect;
1545 		default_par->copy_rect = tgui_copy_rect;
1546 		tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1547 	}
1548 
1549 	default_par->chip_id = chip_id;
1550 
1551 	/* setup MMIO region */
1552 	tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1553 	tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1554 
1555 	if (!request_mem_region(tridentfb_fix.mmio_start,
1556 				tridentfb_fix.mmio_len, "tridentfb")) {
1557 		debug("request_region failed!\n");
1558 		framebuffer_release(info);
1559 		return -1;
1560 	}
1561 
1562 	default_par->io_virt = ioremap(tridentfb_fix.mmio_start,
1563 					       tridentfb_fix.mmio_len);
1564 
1565 	if (!default_par->io_virt) {
1566 		debug("ioremap failed\n");
1567 		err = -1;
1568 		goto out_unmap1;
1569 	}
1570 
1571 	enable_mmio(default_par);
1572 
1573 	/* setup framebuffer memory */
1574 	tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1575 	tridentfb_fix.smem_len = get_memsize(default_par);
1576 
1577 	if (!request_mem_region(tridentfb_fix.smem_start,
1578 				tridentfb_fix.smem_len, "tridentfb")) {
1579 		debug("request_mem_region failed!\n");
1580 		disable_mmio(info->par);
1581 		err = -1;
1582 		goto out_unmap1;
1583 	}
1584 
1585 	info->screen_base = ioremap(tridentfb_fix.smem_start,
1586 					    tridentfb_fix.smem_len);
1587 
1588 	if (!info->screen_base) {
1589 		debug("ioremap failed\n");
1590 		err = -1;
1591 		goto out_unmap2;
1592 	}
1593 
1594 	default_par->flatpanel = is_flatpanel(default_par);
1595 
1596 	if (default_par->flatpanel)
1597 		nativex = get_nativex(default_par);
1598 
1599 	info->fix = tridentfb_fix;
1600 	info->fbops = &tridentfb_ops;
1601 	info->pseudo_palette = default_par->pseudo_pal;
1602 
1603 	info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1604 	if (!noaccel && default_par->init_accel) {
1605 		info->flags &= ~FBINFO_HWACCEL_DISABLED;
1606 		info->flags |= FBINFO_HWACCEL_COPYAREA;
1607 		info->flags |= FBINFO_HWACCEL_FILLRECT;
1608 	} else
1609 		info->flags |= FBINFO_HWACCEL_DISABLED;
1610 
1611 	if (is_blade(chip_id) && chip_id != BLADE3D)
1612 		info->flags |= FBINFO_READS_FAST;
1613 
1614 	info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1615 	if (!info->pixmap.addr) {
1616 		err = -ENOMEM;
1617 		goto out_unmap2;
1618 	}
1619 
1620 	info->pixmap.size = 4096;
1621 	info->pixmap.buf_align = 4;
1622 	info->pixmap.scan_align = 1;
1623 	info->pixmap.access_align = 32;
1624 	info->pixmap.flags = FB_PIXMAP_SYSTEM;
1625 	info->var.bits_per_pixel = 8;
1626 
1627 	if (default_par->image_blit) {
1628 		info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1629 		info->pixmap.scan_align = 4;
1630 	}
1631 
1632 	if (noaccel) {
1633 		printk(KERN_DEBUG "disabling acceleration\n");
1634 		info->flags |= FBINFO_HWACCEL_DISABLED;
1635 		info->pixmap.scan_align = 1;
1636 	}
1637 
1638 	if (tridentfb_setup_ddc_bus(info) == 0) {
1639 		u8 *edid = fb_ddc_read(&default_par->ddc_adapter);
1640 
1641 		default_par->ddc_registered = true;
1642 		if (edid) {
1643 			fb_edid_to_monspecs(edid, &info->monspecs);
1644 			kfree(edid);
1645 			if (!info->monspecs.modedb)
1646 				dev_err(info->device, "error getting mode database\n");
1647 			else {
1648 				const struct fb_videomode *m;
1649 
1650 				fb_videomode_to_modelist(info->monspecs.modedb,
1651 						 info->monspecs.modedb_len,
1652 						 &info->modelist);
1653 				m = fb_find_best_display(&info->monspecs,
1654 							 &info->modelist);
1655 				if (m) {
1656 					fb_videomode_to_var(&info->var, m);
1657 					/* fill all other info->var's fields */
1658 					if (tridentfb_check_var(&info->var,
1659 								info) == 0)
1660 						found = true;
1661 				}
1662 			}
1663 		}
1664 	}
1665 
1666 	if (!mode_option && !found)
1667 		mode_option = "640x480-8@60";
1668 
1669 	/* Prepare startup mode */
1670 	if (mode_option) {
1671 		err = fb_find_mode(&info->var, info, mode_option,
1672 				   info->monspecs.modedb,
1673 				   info->monspecs.modedb_len,
1674 				   NULL, info->var.bits_per_pixel);
1675 		if (!err || err == 4) {
1676 			err = -EINVAL;
1677 			dev_err(info->device, "mode %s not found\n",
1678 								mode_option);
1679 			fb_destroy_modedb(info->monspecs.modedb);
1680 			info->monspecs.modedb = NULL;
1681 			goto out_unmap2;
1682 		}
1683 	}
1684 
1685 	fb_destroy_modedb(info->monspecs.modedb);
1686 	info->monspecs.modedb = NULL;
1687 
1688 	err = fb_alloc_cmap(&info->cmap, 256, 0);
1689 	if (err < 0)
1690 		goto out_unmap2;
1691 
1692 	info->var.activate |= FB_ACTIVATE_NOW;
1693 	info->device = &dev->dev;
1694 	if (register_framebuffer(info) < 0) {
1695 		printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1696 		fb_dealloc_cmap(&info->cmap);
1697 		err = -EINVAL;
1698 		goto out_unmap2;
1699 	}
1700 	output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1701 	   info->node, info->fix.id, info->var.xres,
1702 	   info->var.yres, info->var.bits_per_pixel);
1703 
1704 	pci_set_drvdata(dev, info);
1705 	return 0;
1706 
1707 out_unmap2:
1708 	if (default_par->ddc_registered)
1709 		i2c_del_adapter(&default_par->ddc_adapter);
1710 	kfree(info->pixmap.addr);
1711 	if (info->screen_base)
1712 		iounmap(info->screen_base);
1713 	release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1714 	disable_mmio(info->par);
1715 out_unmap1:
1716 	if (default_par->io_virt)
1717 		iounmap(default_par->io_virt);
1718 	release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1719 	framebuffer_release(info);
1720 	return err;
1721 }
1722 
1723 static void trident_pci_remove(struct pci_dev *dev)
1724 {
1725 	struct fb_info *info = pci_get_drvdata(dev);
1726 	struct tridentfb_par *par = info->par;
1727 
1728 	unregister_framebuffer(info);
1729 	if (par->ddc_registered)
1730 		i2c_del_adapter(&par->ddc_adapter);
1731 	iounmap(par->io_virt);
1732 	iounmap(info->screen_base);
1733 	release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1734 	release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1735 	kfree(info->pixmap.addr);
1736 	fb_dealloc_cmap(&info->cmap);
1737 	framebuffer_release(info);
1738 }
1739 
1740 /* List of boards that we are trying to support */
1741 static const struct pci_device_id trident_devices[] = {
1742 	{PCI_VENDOR_ID_TRIDENT,	BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1743 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1744 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1745 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1746 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1747 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1748 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1749 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1750 	{PCI_VENDOR_ID_TRIDENT,	TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1751 	{PCI_VENDOR_ID_TRIDENT,	TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1752 	{PCI_VENDOR_ID_TRIDENT,	IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1753 	{PCI_VENDOR_ID_TRIDENT,	IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1754 	{PCI_VENDOR_ID_TRIDENT,	CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1755 	{PCI_VENDOR_ID_TRIDENT,	CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1756 	{PCI_VENDOR_ID_TRIDENT,	CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1757 	{PCI_VENDOR_ID_TRIDENT,	CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1758 	{PCI_VENDOR_ID_TRIDENT,	CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1759 	{PCI_VENDOR_ID_TRIDENT,	CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1760 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1761 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1762 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1763 	{0,}
1764 };
1765 
1766 MODULE_DEVICE_TABLE(pci, trident_devices);
1767 
1768 static struct pci_driver tridentfb_pci_driver = {
1769 	.name = "tridentfb",
1770 	.id_table = trident_devices,
1771 	.probe = trident_pci_probe,
1772 	.remove = trident_pci_remove,
1773 };
1774 
1775 /*
1776  * Parse user specified options (`video=trident:')
1777  * example:
1778  *	video=trident:800x600,bpp=16,noaccel
1779  */
1780 #ifndef MODULE
1781 static int __init tridentfb_setup(char *options)
1782 {
1783 	char *opt;
1784 	if (!options || !*options)
1785 		return 0;
1786 	while ((opt = strsep(&options, ",")) != NULL) {
1787 		if (!*opt)
1788 			continue;
1789 		if (!strncmp(opt, "noaccel", 7))
1790 			noaccel = 1;
1791 		else if (!strncmp(opt, "fp", 2))
1792 			fp = 1;
1793 		else if (!strncmp(opt, "crt", 3))
1794 			fp = 0;
1795 		else if (!strncmp(opt, "bpp=", 4))
1796 			bpp = simple_strtoul(opt + 4, NULL, 0);
1797 		else if (!strncmp(opt, "center", 6))
1798 			center = 1;
1799 		else if (!strncmp(opt, "stretch", 7))
1800 			stretch = 1;
1801 		else if (!strncmp(opt, "memsize=", 8))
1802 			memsize = simple_strtoul(opt + 8, NULL, 0);
1803 		else if (!strncmp(opt, "memdiff=", 8))
1804 			memdiff = simple_strtoul(opt + 8, NULL, 0);
1805 		else if (!strncmp(opt, "nativex=", 8))
1806 			nativex = simple_strtoul(opt + 8, NULL, 0);
1807 		else
1808 			mode_option = opt;
1809 	}
1810 	return 0;
1811 }
1812 #endif
1813 
1814 static int __init tridentfb_init(void)
1815 {
1816 #ifndef MODULE
1817 	char *option = NULL;
1818 
1819 	if (fb_get_options("tridentfb", &option))
1820 		return -ENODEV;
1821 	tridentfb_setup(option);
1822 #endif
1823 	return pci_register_driver(&tridentfb_pci_driver);
1824 }
1825 
1826 static void __exit tridentfb_exit(void)
1827 {
1828 	pci_unregister_driver(&tridentfb_pci_driver);
1829 }
1830 
1831 module_init(tridentfb_init);
1832 module_exit(tridentfb_exit);
1833 
1834 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1835 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1836 MODULE_LICENSE("GPL");
1837 MODULE_ALIAS("cyblafb");
1838 
1839