1 /* 2 * Frame buffer driver for Trident TGUI, Blade and Image series 3 * 4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro> 5 * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl> 6 * 7 * CREDITS:(in order of appearance) 8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video 9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it> 10 * much inspired by the XFree86 4.x Trident driver sources 11 * by Alan Hourihane the FreeVGA project 12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support, 13 * code, suggestions 14 * TODO: 15 * timing value tweaking so it looks good on every monitor in every mode 16 */ 17 18 #include <linux/module.h> 19 #include <linux/fb.h> 20 #include <linux/init.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 24 #include <linux/delay.h> 25 #include <video/vga.h> 26 #include <video/trident.h> 27 28 struct tridentfb_par { 29 void __iomem *io_virt; /* iospace virtual memory address */ 30 u32 pseudo_pal[16]; 31 int chip_id; 32 int flatpanel; 33 void (*init_accel) (struct tridentfb_par *, int, int); 34 void (*wait_engine) (struct tridentfb_par *); 35 void (*fill_rect) 36 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); 37 void (*copy_rect) 38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); 39 void (*image_blit) 40 (struct tridentfb_par *par, const char*, 41 u32, u32, u32, u32, u32, u32); 42 unsigned char eng_oper; /* engine operation... */ 43 }; 44 45 static struct fb_fix_screeninfo tridentfb_fix = { 46 .id = "Trident", 47 .type = FB_TYPE_PACKED_PIXELS, 48 .ypanstep = 1, 49 .visual = FB_VISUAL_PSEUDOCOLOR, 50 .accel = FB_ACCEL_NONE, 51 }; 52 53 /* defaults which are normally overriden by user values */ 54 55 /* video mode */ 56 static char *mode_option = "640x480-8@60"; 57 static int bpp = 8; 58 59 static int noaccel; 60 61 static int center; 62 static int stretch; 63 64 static int fp; 65 static int crt; 66 67 static int memsize; 68 static int memdiff; 69 static int nativex; 70 71 module_param(mode_option, charp, 0); 72 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); 73 module_param_named(mode, mode_option, charp, 0); 74 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)"); 75 module_param(bpp, int, 0); 76 module_param(center, int, 0); 77 module_param(stretch, int, 0); 78 module_param(noaccel, int, 0); 79 module_param(memsize, int, 0); 80 module_param(memdiff, int, 0); 81 module_param(nativex, int, 0); 82 module_param(fp, int, 0); 83 MODULE_PARM_DESC(fp, "Define if flatpanel is connected"); 84 module_param(crt, int, 0); 85 MODULE_PARM_DESC(crt, "Define if CRT is connected"); 86 87 static inline int is_oldclock(int id) 88 { 89 return (id == TGUI9440) || 90 (id == TGUI9660) || 91 (id == CYBER9320); 92 } 93 94 static inline int is_oldprotect(int id) 95 { 96 return is_oldclock(id) || 97 (id == PROVIDIA9685) || 98 (id == CYBER9382) || 99 (id == CYBER9385); 100 } 101 102 static inline int is_blade(int id) 103 { 104 return (id == BLADE3D) || 105 (id == CYBERBLADEE4) || 106 (id == CYBERBLADEi7) || 107 (id == CYBERBLADEi7D) || 108 (id == CYBERBLADEi1) || 109 (id == CYBERBLADEi1D) || 110 (id == CYBERBLADEAi1) || 111 (id == CYBERBLADEAi1D); 112 } 113 114 static inline int is_xp(int id) 115 { 116 return (id == CYBERBLADEXPAi1) || 117 (id == CYBERBLADEXPm8) || 118 (id == CYBERBLADEXPm16); 119 } 120 121 static inline int is3Dchip(int id) 122 { 123 return is_blade(id) || is_xp(id) || 124 (id == CYBER9397) || (id == CYBER9397DVD) || 125 (id == CYBER9520) || (id == CYBER9525DVD) || 126 (id == IMAGE975) || (id == IMAGE985); 127 } 128 129 static inline int iscyber(int id) 130 { 131 switch (id) { 132 case CYBER9388: 133 case CYBER9382: 134 case CYBER9385: 135 case CYBER9397: 136 case CYBER9397DVD: 137 case CYBER9520: 138 case CYBER9525DVD: 139 case CYBERBLADEE4: 140 case CYBERBLADEi7D: 141 case CYBERBLADEi1: 142 case CYBERBLADEi1D: 143 case CYBERBLADEAi1: 144 case CYBERBLADEAi1D: 145 case CYBERBLADEXPAi1: 146 return 1; 147 148 case CYBER9320: 149 case CYBERBLADEi7: /* VIA MPV4 integrated version */ 150 default: 151 /* case CYBERBLDAEXPm8: Strange */ 152 /* case CYBERBLDAEXPm16: Strange */ 153 return 0; 154 } 155 } 156 157 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) 158 { 159 fb_writeb(val, p->io_virt + reg); 160 } 161 162 static inline u8 t_inb(struct tridentfb_par *p, u16 reg) 163 { 164 return fb_readb(p->io_virt + reg); 165 } 166 167 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) 168 { 169 fb_writel(v, par->io_virt + r); 170 } 171 172 static inline u32 readmmr(struct tridentfb_par *par, u16 r) 173 { 174 return fb_readl(par->io_virt + r); 175 } 176 177 /* 178 * Blade specific acceleration. 179 */ 180 181 #define point(x, y) ((y) << 16 | (x)) 182 183 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) 184 { 185 int v1 = (pitch >> 3) << 20; 186 int tmp = bpp == 24 ? 2 : (bpp >> 4); 187 int v2 = v1 | (tmp << 29); 188 189 writemmr(par, 0x21C0, v2); 190 writemmr(par, 0x21C4, v2); 191 writemmr(par, 0x21B8, v2); 192 writemmr(par, 0x21BC, v2); 193 writemmr(par, 0x21D0, v1); 194 writemmr(par, 0x21D4, v1); 195 writemmr(par, 0x21C8, v1); 196 writemmr(par, 0x21CC, v1); 197 writemmr(par, 0x216C, 0); 198 } 199 200 static void blade_wait_engine(struct tridentfb_par *par) 201 { 202 while (readmmr(par, STATUS) & 0xFA800000) 203 cpu_relax(); 204 } 205 206 static void blade_fill_rect(struct tridentfb_par *par, 207 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) 208 { 209 writemmr(par, COLOR, c); 210 writemmr(par, ROP, rop ? ROP_X : ROP_S); 211 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2); 212 213 writemmr(par, DST1, point(x, y)); 214 writemmr(par, DST2, point(x + w - 1, y + h - 1)); 215 } 216 217 static void blade_image_blit(struct tridentfb_par *par, const char *data, 218 u32 x, u32 y, u32 w, u32 h, u32 c, u32 b) 219 { 220 unsigned size = ((w + 31) >> 5) * h; 221 222 writemmr(par, COLOR, c); 223 writemmr(par, BGCOLOR, b); 224 writemmr(par, CMD, 0xa0000000 | 3 << 19); 225 226 writemmr(par, DST1, point(x, y)); 227 writemmr(par, DST2, point(x + w - 1, y + h - 1)); 228 229 iowrite32_rep(par->io_virt + 0x10000, data, size); 230 } 231 232 static void blade_copy_rect(struct tridentfb_par *par, 233 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) 234 { 235 int direction = 2; 236 u32 s1 = point(x1, y1); 237 u32 s2 = point(x1 + w - 1, y1 + h - 1); 238 u32 d1 = point(x2, y2); 239 u32 d2 = point(x2 + w - 1, y2 + h - 1); 240 241 if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) 242 direction = 0; 243 244 writemmr(par, ROP, ROP_S); 245 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction); 246 247 writemmr(par, SRC1, direction ? s2 : s1); 248 writemmr(par, SRC2, direction ? s1 : s2); 249 writemmr(par, DST1, direction ? d2 : d1); 250 writemmr(par, DST2, direction ? d1 : d2); 251 } 252 253 /* 254 * BladeXP specific acceleration functions 255 */ 256 257 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) 258 { 259 unsigned char x = bpp == 24 ? 3 : (bpp >> 4); 260 int v1 = pitch << (bpp == 24 ? 20 : (18 + x)); 261 262 switch (pitch << (bpp >> 3)) { 263 case 8192: 264 case 512: 265 x |= 0x00; 266 break; 267 case 1024: 268 x |= 0x04; 269 break; 270 case 2048: 271 x |= 0x08; 272 break; 273 case 4096: 274 x |= 0x0C; 275 break; 276 } 277 278 t_outb(par, x, 0x2125); 279 280 par->eng_oper = x | 0x40; 281 282 writemmr(par, 0x2154, v1); 283 writemmr(par, 0x2150, v1); 284 t_outb(par, 3, 0x2126); 285 } 286 287 static void xp_wait_engine(struct tridentfb_par *par) 288 { 289 int count = 0; 290 int timeout = 0; 291 292 while (t_inb(par, STATUS) & 0x80) { 293 count++; 294 if (count == 10000000) { 295 /* Timeout */ 296 count = 9990000; 297 timeout++; 298 if (timeout == 8) { 299 /* Reset engine */ 300 t_outb(par, 0x00, STATUS); 301 return; 302 } 303 } 304 cpu_relax(); 305 } 306 } 307 308 static void xp_fill_rect(struct tridentfb_par *par, 309 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) 310 { 311 writemmr(par, 0x2127, ROP_P); 312 writemmr(par, 0x2158, c); 313 writemmr(par, DRAWFL, 0x4000); 314 writemmr(par, OLDDIM, point(h, w)); 315 writemmr(par, OLDDST, point(y, x)); 316 t_outb(par, 0x01, OLDCMD); 317 t_outb(par, par->eng_oper, 0x2125); 318 } 319 320 static void xp_copy_rect(struct tridentfb_par *par, 321 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) 322 { 323 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; 324 int direction = 0x0004; 325 326 if ((x1 < x2) && (y1 == y2)) { 327 direction |= 0x0200; 328 x1_tmp = x1 + w - 1; 329 x2_tmp = x2 + w - 1; 330 } else { 331 x1_tmp = x1; 332 x2_tmp = x2; 333 } 334 335 if (y1 < y2) { 336 direction |= 0x0100; 337 y1_tmp = y1 + h - 1; 338 y2_tmp = y2 + h - 1; 339 } else { 340 y1_tmp = y1; 341 y2_tmp = y2; 342 } 343 344 writemmr(par, DRAWFL, direction); 345 t_outb(par, ROP_S, 0x2127); 346 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp)); 347 writemmr(par, OLDDST, point(y2_tmp, x2_tmp)); 348 writemmr(par, OLDDIM, point(h, w)); 349 t_outb(par, 0x01, OLDCMD); 350 } 351 352 /* 353 * Image specific acceleration functions 354 */ 355 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) 356 { 357 int tmp = bpp == 24 ? 2: (bpp >> 4); 358 359 writemmr(par, 0x2120, 0xF0000000); 360 writemmr(par, 0x2120, 0x40000000 | tmp); 361 writemmr(par, 0x2120, 0x80000000); 362 writemmr(par, 0x2144, 0x00000000); 363 writemmr(par, 0x2148, 0x00000000); 364 writemmr(par, 0x2150, 0x00000000); 365 writemmr(par, 0x2154, 0x00000000); 366 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch); 367 writemmr(par, 0x216C, 0x00000000); 368 writemmr(par, 0x2170, 0x00000000); 369 writemmr(par, 0x217C, 0x00000000); 370 writemmr(par, 0x2120, 0x10000000); 371 writemmr(par, 0x2130, (2047 << 16) | 2047); 372 } 373 374 static void image_wait_engine(struct tridentfb_par *par) 375 { 376 while (readmmr(par, 0x2164) & 0xF0000000) 377 cpu_relax(); 378 } 379 380 static void image_fill_rect(struct tridentfb_par *par, 381 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) 382 { 383 writemmr(par, 0x2120, 0x80000000); 384 writemmr(par, 0x2120, 0x90000000 | ROP_S); 385 386 writemmr(par, 0x2144, c); 387 388 writemmr(par, DST1, point(x, y)); 389 writemmr(par, DST2, point(x + w - 1, y + h - 1)); 390 391 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9); 392 } 393 394 static void image_copy_rect(struct tridentfb_par *par, 395 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) 396 { 397 int direction = 0x4; 398 u32 s1 = point(x1, y1); 399 u32 s2 = point(x1 + w - 1, y1 + h - 1); 400 u32 d1 = point(x2, y2); 401 u32 d2 = point(x2 + w - 1, y2 + h - 1); 402 403 if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) 404 direction = 0; 405 406 writemmr(par, 0x2120, 0x80000000); 407 writemmr(par, 0x2120, 0x90000000 | ROP_S); 408 409 writemmr(par, SRC1, direction ? s2 : s1); 410 writemmr(par, SRC2, direction ? s1 : s2); 411 writemmr(par, DST1, direction ? d2 : d1); 412 writemmr(par, DST2, direction ? d1 : d2); 413 writemmr(par, 0x2124, 414 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction); 415 } 416 417 /* 418 * TGUI 9440/96XX acceleration 419 */ 420 421 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp) 422 { 423 unsigned char x = bpp == 24 ? 3 : (bpp >> 4); 424 425 /* disable clipping */ 426 writemmr(par, 0x2148, 0); 427 writemmr(par, 0x214C, point(4095, 2047)); 428 429 switch ((pitch * bpp) / 8) { 430 case 8192: 431 case 512: 432 x |= 0x00; 433 break; 434 case 1024: 435 x |= 0x04; 436 break; 437 case 2048: 438 x |= 0x08; 439 break; 440 case 4096: 441 x |= 0x0C; 442 break; 443 } 444 445 fb_writew(x, par->io_virt + 0x2122); 446 } 447 448 static void tgui_fill_rect(struct tridentfb_par *par, 449 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) 450 { 451 t_outb(par, ROP_P, 0x2127); 452 writemmr(par, OLDCLR, c); 453 writemmr(par, DRAWFL, 0x4020); 454 writemmr(par, OLDDIM, point(w - 1, h - 1)); 455 writemmr(par, OLDDST, point(x, y)); 456 t_outb(par, 1, OLDCMD); 457 } 458 459 static void tgui_copy_rect(struct tridentfb_par *par, 460 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) 461 { 462 int flags = 0; 463 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp; 464 465 if ((x1 < x2) && (y1 == y2)) { 466 flags |= 0x0200; 467 x1_tmp = x1 + w - 1; 468 x2_tmp = x2 + w - 1; 469 } else { 470 x1_tmp = x1; 471 x2_tmp = x2; 472 } 473 474 if (y1 < y2) { 475 flags |= 0x0100; 476 y1_tmp = y1 + h - 1; 477 y2_tmp = y2 + h - 1; 478 } else { 479 y1_tmp = y1; 480 y2_tmp = y2; 481 } 482 483 writemmr(par, DRAWFL, 0x4 | flags); 484 t_outb(par, ROP_S, 0x2127); 485 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp)); 486 writemmr(par, OLDDST, point(x2_tmp, y2_tmp)); 487 writemmr(par, OLDDIM, point(w - 1, h - 1)); 488 t_outb(par, 1, OLDCMD); 489 } 490 491 /* 492 * Accel functions called by the upper layers 493 */ 494 static void tridentfb_fillrect(struct fb_info *info, 495 const struct fb_fillrect *fr) 496 { 497 struct tridentfb_par *par = info->par; 498 int col; 499 500 if (info->flags & FBINFO_HWACCEL_DISABLED) { 501 cfb_fillrect(info, fr); 502 return; 503 } 504 if (info->var.bits_per_pixel == 8) { 505 col = fr->color; 506 col |= col << 8; 507 col |= col << 16; 508 } else 509 col = ((u32 *)(info->pseudo_palette))[fr->color]; 510 511 par->wait_engine(par); 512 par->fill_rect(par, fr->dx, fr->dy, fr->width, 513 fr->height, col, fr->rop); 514 } 515 516 static void tridentfb_imageblit(struct fb_info *info, 517 const struct fb_image *img) 518 { 519 struct tridentfb_par *par = info->par; 520 int col, bgcol; 521 522 if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) { 523 cfb_imageblit(info, img); 524 return; 525 } 526 if (info->var.bits_per_pixel == 8) { 527 col = img->fg_color; 528 col |= col << 8; 529 col |= col << 16; 530 bgcol = img->bg_color; 531 bgcol |= bgcol << 8; 532 bgcol |= bgcol << 16; 533 } else { 534 col = ((u32 *)(info->pseudo_palette))[img->fg_color]; 535 bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color]; 536 } 537 538 par->wait_engine(par); 539 if (par->image_blit) 540 par->image_blit(par, img->data, img->dx, img->dy, 541 img->width, img->height, col, bgcol); 542 else 543 cfb_imageblit(info, img); 544 } 545 546 static void tridentfb_copyarea(struct fb_info *info, 547 const struct fb_copyarea *ca) 548 { 549 struct tridentfb_par *par = info->par; 550 551 if (info->flags & FBINFO_HWACCEL_DISABLED) { 552 cfb_copyarea(info, ca); 553 return; 554 } 555 par->wait_engine(par); 556 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy, 557 ca->width, ca->height); 558 } 559 560 static int tridentfb_sync(struct fb_info *info) 561 { 562 struct tridentfb_par *par = info->par; 563 564 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 565 par->wait_engine(par); 566 return 0; 567 } 568 569 /* 570 * Hardware access functions 571 */ 572 573 static inline unsigned char read3X4(struct tridentfb_par *par, int reg) 574 { 575 return vga_mm_rcrt(par->io_virt, reg); 576 } 577 578 static inline void write3X4(struct tridentfb_par *par, int reg, 579 unsigned char val) 580 { 581 vga_mm_wcrt(par->io_virt, reg, val); 582 } 583 584 static inline unsigned char read3CE(struct tridentfb_par *par, 585 unsigned char reg) 586 { 587 return vga_mm_rgfx(par->io_virt, reg); 588 } 589 590 static inline void writeAttr(struct tridentfb_par *par, int reg, 591 unsigned char val) 592 { 593 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ 594 vga_mm_wattr(par->io_virt, reg, val); 595 } 596 597 static inline void write3CE(struct tridentfb_par *par, int reg, 598 unsigned char val) 599 { 600 vga_mm_wgfx(par->io_virt, reg, val); 601 } 602 603 static void enable_mmio(struct tridentfb_par *par) 604 { 605 /* Goto New Mode */ 606 vga_io_rseq(0x0B); 607 608 /* Unprotect registers */ 609 vga_io_wseq(NewMode1, 0x80); 610 if (!is_oldprotect(par->chip_id)) 611 vga_io_wseq(Protection, 0x92); 612 613 /* Enable MMIO */ 614 outb(PCIReg, 0x3D4); 615 outb(inb(0x3D5) | 0x01, 0x3D5); 616 } 617 618 static void disable_mmio(struct tridentfb_par *par) 619 { 620 /* Goto New Mode */ 621 vga_mm_rseq(par->io_virt, 0x0B); 622 623 /* Unprotect registers */ 624 vga_mm_wseq(par->io_virt, NewMode1, 0x80); 625 if (!is_oldprotect(par->chip_id)) 626 vga_mm_wseq(par->io_virt, Protection, 0x92); 627 628 /* Disable MMIO */ 629 t_outb(par, PCIReg, 0x3D4); 630 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5); 631 } 632 633 static inline void crtc_unlock(struct tridentfb_par *par) 634 { 635 write3X4(par, VGA_CRTC_V_SYNC_END, 636 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F); 637 } 638 639 /* Return flat panel's maximum x resolution */ 640 static int get_nativex(struct tridentfb_par *par) 641 { 642 int x, y, tmp; 643 644 if (nativex) 645 return nativex; 646 647 tmp = (read3CE(par, VertStretch) >> 4) & 3; 648 649 switch (tmp) { 650 case 0: 651 x = 1280; y = 1024; 652 break; 653 case 2: 654 x = 1024; y = 768; 655 break; 656 case 3: 657 x = 800; y = 600; 658 break; 659 case 4: 660 x = 1400; y = 1050; 661 break; 662 case 1: 663 default: 664 x = 640; y = 480; 665 break; 666 } 667 668 output("%dx%d flat panel found\n", x, y); 669 return x; 670 } 671 672 /* Set pitch */ 673 static inline void set_lwidth(struct tridentfb_par *par, int width) 674 { 675 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF); 676 /* chips older than TGUI9660 have only 1 width bit in AddColReg */ 677 /* touching the other one breaks I2C/DDC */ 678 if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320) 679 write3X4(par, AddColReg, 680 (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4)); 681 else 682 write3X4(par, AddColReg, 683 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4)); 684 } 685 686 /* For resolutions smaller than FP resolution stretch */ 687 static void screen_stretch(struct tridentfb_par *par) 688 { 689 if (par->chip_id != CYBERBLADEXPAi1) 690 write3CE(par, BiosReg, 0); 691 else 692 write3CE(par, BiosReg, 8); 693 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1); 694 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1); 695 } 696 697 /* For resolutions smaller than FP resolution center */ 698 static inline void screen_center(struct tridentfb_par *par) 699 { 700 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80); 701 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80); 702 } 703 704 /* Address of first shown pixel in display memory */ 705 static void set_screen_start(struct tridentfb_par *par, int base) 706 { 707 u8 tmp; 708 write3X4(par, VGA_CRTC_START_LO, base & 0xFF); 709 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8); 710 tmp = read3X4(par, CRTCModuleTest) & 0xDF; 711 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); 712 tmp = read3X4(par, CRTHiOrd) & 0xF8; 713 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17)); 714 } 715 716 /* Set dotclock frequency */ 717 static void set_vclk(struct tridentfb_par *par, unsigned long freq) 718 { 719 int m, n, k; 720 unsigned long fi, d, di; 721 unsigned char best_m = 0, best_n = 0, best_k = 0; 722 unsigned char hi, lo; 723 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1; 724 725 d = 20000; 726 for (k = shift; k >= 0; k--) 727 for (m = 1; m < 32; m++) { 728 n = ((m + 2) << shift) - 8; 729 for (n = (n < 0 ? 0 : n); n < 122; n++) { 730 fi = ((14318l * (n + 8)) / (m + 2)) >> k; 731 di = abs(fi - freq); 732 if (di < d || (di == d && k == best_k)) { 733 d = di; 734 best_n = n; 735 best_m = m; 736 best_k = k; 737 } 738 if (fi > freq) 739 break; 740 } 741 } 742 743 if (is_oldclock(par->chip_id)) { 744 lo = best_n | (best_m << 7); 745 hi = (best_m >> 1) | (best_k << 4); 746 } else { 747 lo = best_n; 748 hi = best_m | (best_k << 6); 749 } 750 751 if (is3Dchip(par->chip_id)) { 752 vga_mm_wseq(par->io_virt, ClockHigh, hi); 753 vga_mm_wseq(par->io_virt, ClockLow, lo); 754 } else { 755 t_outb(par, lo, 0x43C8); 756 t_outb(par, hi, 0x43C9); 757 } 758 debug("VCLK = %X %X\n", hi, lo); 759 } 760 761 /* Set number of lines for flat panels*/ 762 static void set_number_of_lines(struct tridentfb_par *par, int lines) 763 { 764 int tmp = read3CE(par, CyberEnhance) & 0x8F; 765 if (lines > 1024) 766 tmp |= 0x50; 767 else if (lines > 768) 768 tmp |= 0x30; 769 else if (lines > 600) 770 tmp |= 0x20; 771 else if (lines > 480) 772 tmp |= 0x10; 773 write3CE(par, CyberEnhance, tmp); 774 } 775 776 /* 777 * If we see that FP is active we assume we have one. 778 * Otherwise we have a CRT display. User can override. 779 */ 780 static int is_flatpanel(struct tridentfb_par *par) 781 { 782 if (fp) 783 return 1; 784 if (crt || !iscyber(par->chip_id)) 785 return 0; 786 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0; 787 } 788 789 /* Try detecting the video memory size */ 790 static unsigned int get_memsize(struct tridentfb_par *par) 791 { 792 unsigned char tmp, tmp2; 793 unsigned int k; 794 795 /* If memory size provided by user */ 796 if (memsize) 797 k = memsize * Kb; 798 else 799 switch (par->chip_id) { 800 case CYBER9525DVD: 801 k = 2560 * Kb; 802 break; 803 default: 804 tmp = read3X4(par, SPR) & 0x0F; 805 switch (tmp) { 806 807 case 0x01: 808 k = 512 * Kb; 809 break; 810 case 0x02: 811 k = 6 * Mb; /* XP */ 812 break; 813 case 0x03: 814 k = 1 * Mb; 815 break; 816 case 0x04: 817 k = 8 * Mb; 818 break; 819 case 0x06: 820 k = 10 * Mb; /* XP */ 821 break; 822 case 0x07: 823 k = 2 * Mb; 824 break; 825 case 0x08: 826 k = 12 * Mb; /* XP */ 827 break; 828 case 0x0A: 829 k = 14 * Mb; /* XP */ 830 break; 831 case 0x0C: 832 k = 16 * Mb; /* XP */ 833 break; 834 case 0x0E: /* XP */ 835 836 tmp2 = vga_mm_rseq(par->io_virt, 0xC1); 837 switch (tmp2) { 838 case 0x00: 839 k = 20 * Mb; 840 break; 841 case 0x01: 842 k = 24 * Mb; 843 break; 844 case 0x10: 845 k = 28 * Mb; 846 break; 847 case 0x11: 848 k = 32 * Mb; 849 break; 850 default: 851 k = 1 * Mb; 852 break; 853 } 854 break; 855 856 case 0x0F: 857 k = 4 * Mb; 858 break; 859 default: 860 k = 1 * Mb; 861 break; 862 } 863 } 864 865 k -= memdiff * Kb; 866 output("framebuffer size = %d Kb\n", k / Kb); 867 return k; 868 } 869 870 /* See if we can handle the video mode described in var */ 871 static int tridentfb_check_var(struct fb_var_screeninfo *var, 872 struct fb_info *info) 873 { 874 struct tridentfb_par *par = info->par; 875 int bpp = var->bits_per_pixel; 876 int line_length; 877 int ramdac = 230000; /* 230MHz for most 3D chips */ 878 debug("enter\n"); 879 880 /* check color depth */ 881 if (bpp == 24) 882 bpp = var->bits_per_pixel = 32; 883 if (bpp != 8 && bpp != 16 && bpp != 32) 884 return -EINVAL; 885 if (par->chip_id == TGUI9440 && bpp == 32) 886 return -EINVAL; 887 /* check whether resolution fits on panel and in memory */ 888 if (par->flatpanel && nativex && var->xres > nativex) 889 return -EINVAL; 890 /* various resolution checks */ 891 var->xres = (var->xres + 7) & ~0x7; 892 if (var->xres > var->xres_virtual) 893 var->xres_virtual = var->xres; 894 if (var->yres > var->yres_virtual) 895 var->yres_virtual = var->yres; 896 if (var->xres_virtual > 4095 || var->yres > 2048) 897 return -EINVAL; 898 /* prevent from position overflow for acceleration */ 899 if (var->yres_virtual > 0xffff) 900 return -EINVAL; 901 line_length = var->xres_virtual * bpp / 8; 902 903 if (!is3Dchip(par->chip_id) && 904 !(info->flags & FBINFO_HWACCEL_DISABLED)) { 905 /* acceleration requires line length to be power of 2 */ 906 if (line_length <= 512) 907 var->xres_virtual = 512 * 8 / bpp; 908 else if (line_length <= 1024) 909 var->xres_virtual = 1024 * 8 / bpp; 910 else if (line_length <= 2048) 911 var->xres_virtual = 2048 * 8 / bpp; 912 else if (line_length <= 4096) 913 var->xres_virtual = 4096 * 8 / bpp; 914 else if (line_length <= 8192) 915 var->xres_virtual = 8192 * 8 / bpp; 916 else 917 return -EINVAL; 918 919 line_length = var->xres_virtual * bpp / 8; 920 } 921 922 /* datasheet specifies how to set panning only up to 4 MB */ 923 if (line_length * (var->yres_virtual - var->yres) > (4 << 20)) 924 var->yres_virtual = ((4 << 20) / line_length) + var->yres; 925 926 if (line_length * var->yres_virtual > info->fix.smem_len) 927 return -EINVAL; 928 929 switch (bpp) { 930 case 8: 931 var->red.offset = 0; 932 var->red.length = 8; 933 var->green = var->red; 934 var->blue = var->red; 935 break; 936 case 16: 937 var->red.offset = 11; 938 var->green.offset = 5; 939 var->blue.offset = 0; 940 var->red.length = 5; 941 var->green.length = 6; 942 var->blue.length = 5; 943 break; 944 case 32: 945 var->red.offset = 16; 946 var->green.offset = 8; 947 var->blue.offset = 0; 948 var->red.length = 8; 949 var->green.length = 8; 950 var->blue.length = 8; 951 break; 952 default: 953 return -EINVAL; 954 } 955 956 if (is_xp(par->chip_id)) 957 ramdac = 350000; 958 959 switch (par->chip_id) { 960 case TGUI9440: 961 ramdac = (bpp >= 16) ? 45000 : 90000; 962 break; 963 case CYBER9320: 964 case TGUI9660: 965 ramdac = 135000; 966 break; 967 case PROVIDIA9685: 968 case CYBER9388: 969 case CYBER9382: 970 case CYBER9385: 971 ramdac = 170000; 972 break; 973 } 974 975 /* The clock is doubled for 32 bpp */ 976 if (bpp == 32) 977 ramdac /= 2; 978 979 if (PICOS2KHZ(var->pixclock) > ramdac) 980 return -EINVAL; 981 982 debug("exit\n"); 983 984 return 0; 985 986 } 987 988 /* Pan the display */ 989 static int tridentfb_pan_display(struct fb_var_screeninfo *var, 990 struct fb_info *info) 991 { 992 struct tridentfb_par *par = info->par; 993 unsigned int offset; 994 995 debug("enter\n"); 996 offset = (var->xoffset + (var->yoffset * info->var.xres_virtual)) 997 * info->var.bits_per_pixel / 32; 998 set_screen_start(par, offset); 999 debug("exit\n"); 1000 return 0; 1001 } 1002 1003 static inline void shadowmode_on(struct tridentfb_par *par) 1004 { 1005 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81); 1006 } 1007 1008 static inline void shadowmode_off(struct tridentfb_par *par) 1009 { 1010 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E); 1011 } 1012 1013 /* Set the hardware to the requested video mode */ 1014 static int tridentfb_set_par(struct fb_info *info) 1015 { 1016 struct tridentfb_par *par = info->par; 1017 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend; 1018 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend; 1019 struct fb_var_screeninfo *var = &info->var; 1020 int bpp = var->bits_per_pixel; 1021 unsigned char tmp; 1022 unsigned long vclk; 1023 1024 debug("enter\n"); 1025 hdispend = var->xres / 8 - 1; 1026 hsyncstart = (var->xres + var->right_margin) / 8; 1027 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8; 1028 htotal = (var->xres + var->left_margin + var->right_margin + 1029 var->hsync_len) / 8 - 5; 1030 hblankstart = hdispend + 1; 1031 hblankend = htotal + 3; 1032 1033 vdispend = var->yres - 1; 1034 vsyncstart = var->yres + var->lower_margin; 1035 vsyncend = vsyncstart + var->vsync_len; 1036 vtotal = var->upper_margin + vsyncend - 2; 1037 vblankstart = vdispend + 1; 1038 vblankend = vtotal; 1039 1040 if (info->var.vmode & FB_VMODE_INTERLACED) { 1041 vtotal /= 2; 1042 vdispend /= 2; 1043 vsyncstart /= 2; 1044 vsyncend /= 2; 1045 vblankstart /= 2; 1046 vblankend /= 2; 1047 } 1048 1049 enable_mmio(par); 1050 crtc_unlock(par); 1051 write3CE(par, CyberControl, 8); 1052 tmp = 0xEB; 1053 if (var->sync & FB_SYNC_HOR_HIGH_ACT) 1054 tmp &= ~0x40; 1055 if (var->sync & FB_SYNC_VERT_HIGH_ACT) 1056 tmp &= ~0x80; 1057 1058 if (par->flatpanel && var->xres < nativex) { 1059 /* 1060 * on flat panels with native size larger 1061 * than requested resolution decide whether 1062 * we stretch or center 1063 */ 1064 t_outb(par, tmp | 0xC0, VGA_MIS_W); 1065 1066 shadowmode_on(par); 1067 1068 if (center) 1069 screen_center(par); 1070 else if (stretch) 1071 screen_stretch(par); 1072 1073 } else { 1074 t_outb(par, tmp, VGA_MIS_W); 1075 write3CE(par, CyberControl, 8); 1076 } 1077 1078 /* vertical timing values */ 1079 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF); 1080 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF); 1081 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF); 1082 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F)); 1083 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF); 1084 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF); 1085 1086 /* horizontal timing values */ 1087 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF); 1088 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF); 1089 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF); 1090 write3X4(par, VGA_CRTC_H_SYNC_END, 1091 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); 1092 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF); 1093 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F); 1094 1095 /* higher bits of vertical timing values */ 1096 tmp = 0x10; 1097 if (vtotal & 0x100) tmp |= 0x01; 1098 if (vdispend & 0x100) tmp |= 0x02; 1099 if (vsyncstart & 0x100) tmp |= 0x04; 1100 if (vblankstart & 0x100) tmp |= 0x08; 1101 1102 if (vtotal & 0x200) tmp |= 0x20; 1103 if (vdispend & 0x200) tmp |= 0x40; 1104 if (vsyncstart & 0x200) tmp |= 0x80; 1105 write3X4(par, VGA_CRTC_OVERFLOW, tmp); 1106 1107 tmp = read3X4(par, CRTHiOrd) & 0x07; 1108 tmp |= 0x08; /* line compare bit 10 */ 1109 if (vtotal & 0x400) tmp |= 0x80; 1110 if (vblankstart & 0x400) tmp |= 0x40; 1111 if (vsyncstart & 0x400) tmp |= 0x20; 1112 if (vdispend & 0x400) tmp |= 0x10; 1113 write3X4(par, CRTHiOrd, tmp); 1114 1115 tmp = (htotal >> 8) & 0x01; 1116 tmp |= (hdispend >> 7) & 0x02; 1117 tmp |= (hsyncstart >> 5) & 0x08; 1118 tmp |= (hblankstart >> 4) & 0x10; 1119 write3X4(par, HorizOverflow, tmp); 1120 1121 tmp = 0x40; 1122 if (vblankstart & 0x200) tmp |= 0x20; 1123 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ 1124 write3X4(par, VGA_CRTC_MAX_SCAN, tmp); 1125 1126 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF); 1127 write3X4(par, VGA_CRTC_PRESET_ROW, 0); 1128 write3X4(par, VGA_CRTC_MODE, 0xC3); 1129 1130 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */ 1131 1132 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80; 1133 /* enable access extended memory */ 1134 write3X4(par, CRTCModuleTest, tmp); 1135 tmp = read3CE(par, MiscIntContReg) & ~0x4; 1136 if (info->var.vmode & FB_VMODE_INTERLACED) 1137 tmp |= 0x4; 1138 write3CE(par, MiscIntContReg, tmp); 1139 1140 /* enable GE for text acceleration */ 1141 write3X4(par, GraphEngReg, 0x80); 1142 1143 switch (bpp) { 1144 case 8: 1145 tmp = 0x00; 1146 break; 1147 case 16: 1148 tmp = 0x05; 1149 break; 1150 case 24: 1151 tmp = 0x29; 1152 break; 1153 case 32: 1154 tmp = 0x09; 1155 break; 1156 } 1157 1158 write3X4(par, PixelBusReg, tmp); 1159 1160 tmp = read3X4(par, DRAMControl); 1161 if (!is_oldprotect(par->chip_id)) 1162 tmp |= 0x10; 1163 if (iscyber(par->chip_id)) 1164 tmp |= 0x20; 1165 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */ 1166 1167 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40); 1168 if (!is_xp(par->chip_id)) 1169 write3X4(par, Performance, read3X4(par, Performance) | 0x10); 1170 /* MMIO & PCI read and write burst enable */ 1171 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975) 1172 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06); 1173 1174 vga_mm_wseq(par->io_virt, 0, 3); 1175 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */ 1176 /* enable 4 maps because needed in chain4 mode */ 1177 vga_mm_wseq(par->io_virt, 2, 0x0F); 1178 vga_mm_wseq(par->io_virt, 3, 0); 1179 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */ 1180 1181 /* convert from picoseconds to kHz */ 1182 vclk = PICOS2KHZ(info->var.pixclock); 1183 1184 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ 1185 tmp = read3CE(par, MiscExtFunc) & 0xF0; 1186 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) { 1187 tmp |= 8; 1188 vclk *= 2; 1189 } 1190 set_vclk(par, vclk); 1191 write3CE(par, MiscExtFunc, tmp | 0x12); 1192 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */ 1193 write3CE(par, 0x6, 0x05); /* graphics mode */ 1194 write3CE(par, 0x7, 0x0F); /* planes? */ 1195 1196 /* graphics mode and support 256 color modes */ 1197 writeAttr(par, 0x10, 0x41); 1198 writeAttr(par, 0x12, 0x0F); /* planes */ 1199 writeAttr(par, 0x13, 0); /* horizontal pel panning */ 1200 1201 /* colors */ 1202 for (tmp = 0; tmp < 0x10; tmp++) 1203 writeAttr(par, tmp, tmp); 1204 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ 1205 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */ 1206 1207 switch (bpp) { 1208 case 8: 1209 tmp = 0; 1210 break; 1211 case 16: 1212 tmp = 0x30; 1213 break; 1214 case 24: 1215 case 32: 1216 tmp = 0xD0; 1217 break; 1218 } 1219 1220 t_inb(par, VGA_PEL_IW); 1221 t_inb(par, VGA_PEL_MSK); 1222 t_inb(par, VGA_PEL_MSK); 1223 t_inb(par, VGA_PEL_MSK); 1224 t_inb(par, VGA_PEL_MSK); 1225 t_outb(par, tmp, VGA_PEL_MSK); 1226 t_inb(par, VGA_PEL_IW); 1227 1228 if (par->flatpanel) 1229 set_number_of_lines(par, info->var.yres); 1230 info->fix.line_length = info->var.xres_virtual * bpp / 8; 1231 set_lwidth(par, info->fix.line_length / 8); 1232 1233 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 1234 par->init_accel(par, info->var.xres_virtual, bpp); 1235 1236 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 1237 info->cmap.len = (bpp == 8) ? 256 : 16; 1238 debug("exit\n"); 1239 return 0; 1240 } 1241 1242 /* Set one color register */ 1243 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, 1244 unsigned blue, unsigned transp, 1245 struct fb_info *info) 1246 { 1247 int bpp = info->var.bits_per_pixel; 1248 struct tridentfb_par *par = info->par; 1249 1250 if (regno >= info->cmap.len) 1251 return 1; 1252 1253 if (bpp == 8) { 1254 t_outb(par, 0xFF, VGA_PEL_MSK); 1255 t_outb(par, regno, VGA_PEL_IW); 1256 1257 t_outb(par, red >> 10, VGA_PEL_D); 1258 t_outb(par, green >> 10, VGA_PEL_D); 1259 t_outb(par, blue >> 10, VGA_PEL_D); 1260 1261 } else if (regno < 16) { 1262 if (bpp == 16) { /* RGB 565 */ 1263 u32 col; 1264 1265 col = (red & 0xF800) | ((green & 0xFC00) >> 5) | 1266 ((blue & 0xF800) >> 11); 1267 col |= col << 16; 1268 ((u32 *)(info->pseudo_palette))[regno] = col; 1269 } else if (bpp == 32) /* ARGB 8888 */ 1270 ((u32 *)info->pseudo_palette)[regno] = 1271 ((transp & 0xFF00) << 16) | 1272 ((red & 0xFF00) << 8) | 1273 ((green & 0xFF00)) | 1274 ((blue & 0xFF00) >> 8); 1275 } 1276 1277 return 0; 1278 } 1279 1280 /* Try blanking the screen. For flat panels it does nothing */ 1281 static int tridentfb_blank(int blank_mode, struct fb_info *info) 1282 { 1283 unsigned char PMCont, DPMSCont; 1284 struct tridentfb_par *par = info->par; 1285 1286 debug("enter\n"); 1287 if (par->flatpanel) 1288 return 0; 1289 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */ 1290 PMCont = t_inb(par, 0x83C6) & 0xFC; 1291 DPMSCont = read3CE(par, PowerStatus) & 0xFC; 1292 switch (blank_mode) { 1293 case FB_BLANK_UNBLANK: 1294 /* Screen: On, HSync: On, VSync: On */ 1295 case FB_BLANK_NORMAL: 1296 /* Screen: Off, HSync: On, VSync: On */ 1297 PMCont |= 0x03; 1298 DPMSCont |= 0x00; 1299 break; 1300 case FB_BLANK_HSYNC_SUSPEND: 1301 /* Screen: Off, HSync: Off, VSync: On */ 1302 PMCont |= 0x02; 1303 DPMSCont |= 0x01; 1304 break; 1305 case FB_BLANK_VSYNC_SUSPEND: 1306 /* Screen: Off, HSync: On, VSync: Off */ 1307 PMCont |= 0x02; 1308 DPMSCont |= 0x02; 1309 break; 1310 case FB_BLANK_POWERDOWN: 1311 /* Screen: Off, HSync: Off, VSync: Off */ 1312 PMCont |= 0x00; 1313 DPMSCont |= 0x03; 1314 break; 1315 } 1316 1317 write3CE(par, PowerStatus, DPMSCont); 1318 t_outb(par, 4, 0x83C8); 1319 t_outb(par, PMCont, 0x83C6); 1320 1321 debug("exit\n"); 1322 1323 /* let fbcon do a softblank for us */ 1324 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; 1325 } 1326 1327 static struct fb_ops tridentfb_ops = { 1328 .owner = THIS_MODULE, 1329 .fb_setcolreg = tridentfb_setcolreg, 1330 .fb_pan_display = tridentfb_pan_display, 1331 .fb_blank = tridentfb_blank, 1332 .fb_check_var = tridentfb_check_var, 1333 .fb_set_par = tridentfb_set_par, 1334 .fb_fillrect = tridentfb_fillrect, 1335 .fb_copyarea = tridentfb_copyarea, 1336 .fb_imageblit = tridentfb_imageblit, 1337 .fb_sync = tridentfb_sync, 1338 }; 1339 1340 static int trident_pci_probe(struct pci_dev *dev, 1341 const struct pci_device_id *id) 1342 { 1343 int err; 1344 unsigned char revision; 1345 struct fb_info *info; 1346 struct tridentfb_par *default_par; 1347 int chip3D; 1348 int chip_id; 1349 1350 err = pci_enable_device(dev); 1351 if (err) 1352 return err; 1353 1354 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev); 1355 if (!info) 1356 return -ENOMEM; 1357 default_par = info->par; 1358 1359 chip_id = id->device; 1360 1361 /* If PCI id is 0x9660 then further detect chip type */ 1362 1363 if (chip_id == TGUI9660) { 1364 revision = vga_io_rseq(RevisionID); 1365 1366 switch (revision) { 1367 case 0x21: 1368 chip_id = PROVIDIA9685; 1369 break; 1370 case 0x22: 1371 case 0x23: 1372 chip_id = CYBER9397; 1373 break; 1374 case 0x2A: 1375 chip_id = CYBER9397DVD; 1376 break; 1377 case 0x30: 1378 case 0x33: 1379 case 0x34: 1380 case 0x35: 1381 case 0x38: 1382 case 0x3A: 1383 case 0xB3: 1384 chip_id = CYBER9385; 1385 break; 1386 case 0x40 ... 0x43: 1387 chip_id = CYBER9382; 1388 break; 1389 case 0x4A: 1390 chip_id = CYBER9388; 1391 break; 1392 default: 1393 break; 1394 } 1395 } 1396 1397 chip3D = is3Dchip(chip_id); 1398 1399 if (is_xp(chip_id)) { 1400 default_par->init_accel = xp_init_accel; 1401 default_par->wait_engine = xp_wait_engine; 1402 default_par->fill_rect = xp_fill_rect; 1403 default_par->copy_rect = xp_copy_rect; 1404 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP; 1405 } else if (is_blade(chip_id)) { 1406 default_par->init_accel = blade_init_accel; 1407 default_par->wait_engine = blade_wait_engine; 1408 default_par->fill_rect = blade_fill_rect; 1409 default_par->copy_rect = blade_copy_rect; 1410 default_par->image_blit = blade_image_blit; 1411 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D; 1412 } else if (chip3D) { /* 3DImage family left */ 1413 default_par->init_accel = image_init_accel; 1414 default_par->wait_engine = image_wait_engine; 1415 default_par->fill_rect = image_fill_rect; 1416 default_par->copy_rect = image_copy_rect; 1417 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE; 1418 } else { /* TGUI 9440/96XX family */ 1419 default_par->init_accel = tgui_init_accel; 1420 default_par->wait_engine = xp_wait_engine; 1421 default_par->fill_rect = tgui_fill_rect; 1422 default_par->copy_rect = tgui_copy_rect; 1423 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI; 1424 } 1425 1426 default_par->chip_id = chip_id; 1427 1428 /* setup MMIO region */ 1429 tridentfb_fix.mmio_start = pci_resource_start(dev, 1); 1430 tridentfb_fix.mmio_len = pci_resource_len(dev, 1); 1431 1432 if (!request_mem_region(tridentfb_fix.mmio_start, 1433 tridentfb_fix.mmio_len, "tridentfb")) { 1434 debug("request_region failed!\n"); 1435 framebuffer_release(info); 1436 return -1; 1437 } 1438 1439 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start, 1440 tridentfb_fix.mmio_len); 1441 1442 if (!default_par->io_virt) { 1443 debug("ioremap failed\n"); 1444 err = -1; 1445 goto out_unmap1; 1446 } 1447 1448 enable_mmio(default_par); 1449 1450 /* setup framebuffer memory */ 1451 tridentfb_fix.smem_start = pci_resource_start(dev, 0); 1452 tridentfb_fix.smem_len = get_memsize(default_par); 1453 1454 if (!request_mem_region(tridentfb_fix.smem_start, 1455 tridentfb_fix.smem_len, "tridentfb")) { 1456 debug("request_mem_region failed!\n"); 1457 disable_mmio(info->par); 1458 err = -1; 1459 goto out_unmap1; 1460 } 1461 1462 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start, 1463 tridentfb_fix.smem_len); 1464 1465 if (!info->screen_base) { 1466 debug("ioremap failed\n"); 1467 err = -1; 1468 goto out_unmap2; 1469 } 1470 1471 default_par->flatpanel = is_flatpanel(default_par); 1472 1473 if (default_par->flatpanel) 1474 nativex = get_nativex(default_par); 1475 1476 info->fix = tridentfb_fix; 1477 info->fbops = &tridentfb_ops; 1478 info->pseudo_palette = default_par->pseudo_pal; 1479 1480 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 1481 if (!noaccel && default_par->init_accel) { 1482 info->flags &= ~FBINFO_HWACCEL_DISABLED; 1483 info->flags |= FBINFO_HWACCEL_COPYAREA; 1484 info->flags |= FBINFO_HWACCEL_FILLRECT; 1485 } else 1486 info->flags |= FBINFO_HWACCEL_DISABLED; 1487 1488 if (is_blade(chip_id) && chip_id != BLADE3D) 1489 info->flags |= FBINFO_READS_FAST; 1490 1491 info->pixmap.addr = kmalloc(4096, GFP_KERNEL); 1492 if (!info->pixmap.addr) { 1493 err = -ENOMEM; 1494 goto out_unmap2; 1495 } 1496 1497 info->pixmap.size = 4096; 1498 info->pixmap.buf_align = 4; 1499 info->pixmap.scan_align = 1; 1500 info->pixmap.access_align = 32; 1501 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1502 1503 if (default_par->image_blit) { 1504 info->flags |= FBINFO_HWACCEL_IMAGEBLIT; 1505 info->pixmap.scan_align = 4; 1506 } 1507 1508 if (noaccel) { 1509 printk(KERN_DEBUG "disabling acceleration\n"); 1510 info->flags |= FBINFO_HWACCEL_DISABLED; 1511 info->pixmap.scan_align = 1; 1512 } 1513 1514 if (!fb_find_mode(&info->var, info, 1515 mode_option, NULL, 0, NULL, bpp)) { 1516 err = -EINVAL; 1517 goto out_unmap2; 1518 } 1519 err = fb_alloc_cmap(&info->cmap, 256, 0); 1520 if (err < 0) 1521 goto out_unmap2; 1522 1523 info->var.activate |= FB_ACTIVATE_NOW; 1524 info->device = &dev->dev; 1525 if (register_framebuffer(info) < 0) { 1526 printk(KERN_ERR "tridentfb: could not register framebuffer\n"); 1527 fb_dealloc_cmap(&info->cmap); 1528 err = -EINVAL; 1529 goto out_unmap2; 1530 } 1531 output("fb%d: %s frame buffer device %dx%d-%dbpp\n", 1532 info->node, info->fix.id, info->var.xres, 1533 info->var.yres, info->var.bits_per_pixel); 1534 1535 pci_set_drvdata(dev, info); 1536 return 0; 1537 1538 out_unmap2: 1539 kfree(info->pixmap.addr); 1540 if (info->screen_base) 1541 iounmap(info->screen_base); 1542 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); 1543 disable_mmio(info->par); 1544 out_unmap1: 1545 if (default_par->io_virt) 1546 iounmap(default_par->io_virt); 1547 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); 1548 framebuffer_release(info); 1549 return err; 1550 } 1551 1552 static void trident_pci_remove(struct pci_dev *dev) 1553 { 1554 struct fb_info *info = pci_get_drvdata(dev); 1555 struct tridentfb_par *par = info->par; 1556 1557 unregister_framebuffer(info); 1558 iounmap(par->io_virt); 1559 iounmap(info->screen_base); 1560 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); 1561 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); 1562 kfree(info->pixmap.addr); 1563 fb_dealloc_cmap(&info->cmap); 1564 framebuffer_release(info); 1565 } 1566 1567 /* List of boards that we are trying to support */ 1568 static struct pci_device_id trident_devices[] = { 1569 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1570 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1571 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1572 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1573 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1574 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1575 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1576 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1577 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1578 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1579 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1580 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1581 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1582 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1583 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1584 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1585 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1586 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1587 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1588 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1589 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1590 {0,} 1591 }; 1592 1593 MODULE_DEVICE_TABLE(pci, trident_devices); 1594 1595 static struct pci_driver tridentfb_pci_driver = { 1596 .name = "tridentfb", 1597 .id_table = trident_devices, 1598 .probe = trident_pci_probe, 1599 .remove = trident_pci_remove, 1600 }; 1601 1602 /* 1603 * Parse user specified options (`video=trident:') 1604 * example: 1605 * video=trident:800x600,bpp=16,noaccel 1606 */ 1607 #ifndef MODULE 1608 static int __init tridentfb_setup(char *options) 1609 { 1610 char *opt; 1611 if (!options || !*options) 1612 return 0; 1613 while ((opt = strsep(&options, ",")) != NULL) { 1614 if (!*opt) 1615 continue; 1616 if (!strncmp(opt, "noaccel", 7)) 1617 noaccel = 1; 1618 else if (!strncmp(opt, "fp", 2)) 1619 fp = 1; 1620 else if (!strncmp(opt, "crt", 3)) 1621 fp = 0; 1622 else if (!strncmp(opt, "bpp=", 4)) 1623 bpp = simple_strtoul(opt + 4, NULL, 0); 1624 else if (!strncmp(opt, "center", 6)) 1625 center = 1; 1626 else if (!strncmp(opt, "stretch", 7)) 1627 stretch = 1; 1628 else if (!strncmp(opt, "memsize=", 8)) 1629 memsize = simple_strtoul(opt + 8, NULL, 0); 1630 else if (!strncmp(opt, "memdiff=", 8)) 1631 memdiff = simple_strtoul(opt + 8, NULL, 0); 1632 else if (!strncmp(opt, "nativex=", 8)) 1633 nativex = simple_strtoul(opt + 8, NULL, 0); 1634 else 1635 mode_option = opt; 1636 } 1637 return 0; 1638 } 1639 #endif 1640 1641 static int __init tridentfb_init(void) 1642 { 1643 #ifndef MODULE 1644 char *option = NULL; 1645 1646 if (fb_get_options("tridentfb", &option)) 1647 return -ENODEV; 1648 tridentfb_setup(option); 1649 #endif 1650 return pci_register_driver(&tridentfb_pci_driver); 1651 } 1652 1653 static void __exit tridentfb_exit(void) 1654 { 1655 pci_unregister_driver(&tridentfb_pci_driver); 1656 } 1657 1658 module_init(tridentfb_init); 1659 module_exit(tridentfb_exit); 1660 1661 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>"); 1662 MODULE_DESCRIPTION("Framebuffer driver for Trident cards"); 1663 MODULE_LICENSE("GPL"); 1664 MODULE_ALIAS("cyblafb"); 1665 1666