1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * tdfxfb.c 5 * 6 * Author: Hannu Mallat <hmallat@cc.hut.fi> 7 * 8 * Copyright © 1999 Hannu Mallat 9 * All rights reserved 10 * 11 * Created : Thu Sep 23 18:17:43 1999, hmallat 12 * Last modified: Tue Nov 2 21:19:47 1999, hmallat 13 * 14 * I2C part copied from the i2c-voodoo3.c driver by: 15 * Frodo Looijaard <frodol@dds.nl>, 16 * Philip Edelbrock <phil@netroedge.com>, 17 * Ralph Metzler <rjkm@thp.uni-koeln.de>, and 18 * Mark D. Studebaker <mdsxyz123@yahoo.com> 19 * 20 * Lots of the information here comes from the Daryll Strauss' Banshee 21 * patches to the XF86 server, and the rest comes from the 3dfx 22 * Banshee specification. I'm very much indebted to Daryll for his 23 * work on the X server. 24 * 25 * Voodoo3 support was contributed Harold Oga. Lots of additions 26 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila 27 * Kesmarki. Thanks guys! 28 * 29 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they 30 * behave very differently from the Voodoo3/4/5. For anyone wanting to 31 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is 32 * located at http://www.sourceforge.net/projects/sstfb). 33 * 34 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee, 35 * I do wish the next version is a bit more complete. Without the XF86 36 * patches I couldn't have gotten even this far... for instance, the 37 * extensions to the VGA register set go completely unmentioned in the 38 * spec! Also, lots of references are made to the 'SST core', but no 39 * spec is publicly available, AFAIK. 40 * 41 * The structure of this driver comes pretty much from the Permedia 42 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb. 43 * 44 * TODO: 45 * - multihead support (basically need to support an array of fb_infos) 46 * - support other architectures (PPC, Alpha); does the fact that the VGA 47 * core can be accessed only thru I/O (not memory mapped) complicate 48 * things? 49 * 50 * Version history: 51 * 52 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons 53 * 54 * 0.1.3 (released 1999-11-02) added Attila's panning support, code 55 * reorg, hwcursor address page size alignment 56 * (for mmapping both frame buffer and regs), 57 * and my changes to get rid of hardcoded 58 * VGA i/o register locations (uses PCI 59 * configuration info now) 60 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and 61 * improvements 62 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga. 63 * 0.1.0 (released 1999-10-06) initial version 64 * 65 */ 66 67 #include <linux/aperture.h> 68 #include <linux/module.h> 69 #include <linux/kernel.h> 70 #include <linux/delay.h> 71 #include <linux/errno.h> 72 #include <linux/string.h> 73 #include <linux/mm.h> 74 #include <linux/slab.h> 75 #include <linux/vmalloc.h> 76 #include <linux/fb.h> 77 #include <linux/init.h> 78 #include <linux/pci.h> 79 #include <asm/io.h> 80 81 #include <video/tdfx.h> 82 #include <video/vga.h> 83 84 #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b) 85 86 #define BANSHEE_MAX_PIXCLOCK 270000 87 #define VOODOO3_MAX_PIXCLOCK 300000 88 #define VOODOO5_MAX_PIXCLOCK 350000 89 90 static const struct fb_fix_screeninfo tdfx_fix = { 91 .type = FB_TYPE_PACKED_PIXELS, 92 .visual = FB_VISUAL_PSEUDOCOLOR, 93 .ypanstep = 1, 94 .ywrapstep = 1, 95 .accel = FB_ACCEL_3DFX_BANSHEE 96 }; 97 98 static const struct fb_var_screeninfo tdfx_var = { 99 /* "640x480, 8 bpp @ 60 Hz */ 100 .xres = 640, 101 .yres = 480, 102 .xres_virtual = 640, 103 .yres_virtual = 1024, 104 .bits_per_pixel = 8, 105 .red = {0, 8, 0}, 106 .blue = {0, 8, 0}, 107 .green = {0, 8, 0}, 108 .activate = FB_ACTIVATE_NOW, 109 .height = -1, 110 .width = -1, 111 .accel_flags = FB_ACCELF_TEXT, 112 .pixclock = 39722, 113 .left_margin = 40, 114 .right_margin = 24, 115 .upper_margin = 32, 116 .lower_margin = 11, 117 .hsync_len = 96, 118 .vsync_len = 2, 119 .vmode = FB_VMODE_NONINTERLACED 120 }; 121 122 /* 123 * PCI driver prototypes 124 */ 125 static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id); 126 static void tdfxfb_remove(struct pci_dev *pdev); 127 128 static const struct pci_device_id tdfxfb_id_table[] = { 129 { 130 PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE), 131 .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff0000, 132 }, { 133 PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3), 134 .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff0000, 135 }, { 136 PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5), 137 .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff0000, 138 }, 139 { } 140 }; 141 142 static struct pci_driver tdfxfb_driver = { 143 .name = "tdfxfb", 144 .id_table = tdfxfb_id_table, 145 .probe = tdfxfb_probe, 146 .remove = tdfxfb_remove, 147 }; 148 149 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table); 150 151 /* 152 * Driver data 153 */ 154 static int nopan; 155 static int nowrap = 1; /* not implemented (yet) */ 156 static int hwcursor = 1; 157 static char *mode_option; 158 static bool nomtrr; 159 160 /* ------------------------------------------------------------------------- 161 * Hardware-specific funcions 162 * ------------------------------------------------------------------------- */ 163 164 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) 165 { 166 return inb(par->iobase + reg - 0x300); 167 } 168 169 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) 170 { 171 outb(val, par->iobase + reg - 0x300); 172 } 173 174 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) 175 { 176 vga_outb(par, GRA_I, idx); 177 wmb(); 178 vga_outb(par, GRA_D, val); 179 wmb(); 180 } 181 182 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) 183 { 184 vga_outb(par, SEQ_I, idx); 185 wmb(); 186 vga_outb(par, SEQ_D, val); 187 wmb(); 188 } 189 190 static inline u8 seq_inb(struct tdfx_par *par, u32 idx) 191 { 192 vga_outb(par, SEQ_I, idx); 193 mb(); 194 return vga_inb(par, SEQ_D); 195 } 196 197 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) 198 { 199 vga_outb(par, CRT_I, idx); 200 wmb(); 201 vga_outb(par, CRT_D, val); 202 wmb(); 203 } 204 205 static inline u8 crt_inb(struct tdfx_par *par, u32 idx) 206 { 207 vga_outb(par, CRT_I, idx); 208 mb(); 209 return vga_inb(par, CRT_D); 210 } 211 212 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val) 213 { 214 vga_inb(par, IS1_R); 215 vga_outb(par, ATT_IW, idx); 216 vga_outb(par, ATT_IW, val); 217 } 218 219 static inline void vga_disable_video(struct tdfx_par *par) 220 { 221 unsigned char s; 222 223 s = seq_inb(par, 0x01) | 0x20; 224 seq_outb(par, 0x00, 0x01); 225 seq_outb(par, 0x01, s); 226 seq_outb(par, 0x00, 0x03); 227 } 228 229 static inline void vga_enable_video(struct tdfx_par *par) 230 { 231 unsigned char s; 232 233 s = seq_inb(par, 0x01) & 0xdf; 234 seq_outb(par, 0x00, 0x01); 235 seq_outb(par, 0x01, s); 236 seq_outb(par, 0x00, 0x03); 237 } 238 239 static inline void vga_enable_palette(struct tdfx_par *par) 240 { 241 vga_inb(par, IS1_R); 242 mb(); 243 vga_outb(par, ATT_IW, 0x20); 244 } 245 246 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg) 247 { 248 return readl(par->regbase_virt + reg); 249 } 250 251 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val) 252 { 253 writel(val, par->regbase_virt + reg); 254 } 255 256 static inline void banshee_make_room(struct tdfx_par *par, int size) 257 { 258 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop 259 * won't quit if you ask for more. */ 260 while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1) 261 cpu_relax(); 262 } 263 264 static int banshee_wait_idle(struct fb_info *info) 265 { 266 struct tdfx_par *par = info->par; 267 int i = 0; 268 269 banshee_make_room(par, 1); 270 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP); 271 272 do { 273 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0) 274 i++; 275 } while (i < 3); 276 277 return 0; 278 } 279 280 /* 281 * Set the color of a palette entry in 8bpp mode 282 */ 283 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c) 284 { 285 banshee_make_room(par, 2); 286 tdfx_outl(par, DACADDR, regno); 287 /* read after write makes it working */ 288 tdfx_inl(par, DACADDR); 289 tdfx_outl(par, DACDATA, c); 290 } 291 292 static u32 do_calc_pll(int freq, int *freq_out) 293 { 294 int m, n, k, best_m, best_n, best_k, best_error; 295 int fref = 14318; 296 297 best_error = freq; 298 best_n = best_m = best_k = 0; 299 300 for (k = 3; k >= 0; k--) { 301 for (m = 63; m >= 0; m--) { 302 /* 303 * Estimate value of n that produces target frequency 304 * with current m and k 305 */ 306 int n_estimated = ((freq * (m + 2) << k) / fref) - 2; 307 308 /* Search neighborhood of estimated n */ 309 for (n = max(0, n_estimated); 310 n <= min(255, n_estimated + 1); 311 n++) { 312 /* 313 * Calculate PLL freqency with current m, k and 314 * estimated n 315 */ 316 int f = (fref * (n + 2) / (m + 2)) >> k; 317 int error = abs(f - freq); 318 319 /* 320 * If this is the closest we've come to the 321 * target frequency then remember n, m and k 322 */ 323 if (error < best_error) { 324 best_error = error; 325 best_n = n; 326 best_m = m; 327 best_k = k; 328 } 329 } 330 } 331 } 332 333 n = best_n; 334 m = best_m; 335 k = best_k; 336 *freq_out = (fref * (n + 2) / (m + 2)) >> k; 337 338 return (n << 8) | (m << 2) | k; 339 } 340 341 /* 342 * Convert a pllctrl register value back to a frequency in kHz. 343 * Formula from 3dfx documentation. 344 */ 345 static u32 tdfx_pll_to_khz(u32 pll) 346 { 347 return (14318 * (((pll >> 8) & 0xff) + 2) / 348 (((pll >> 2) & 0x3f) + 2)) >> (pll & 3); 349 } 350 351 /* Layout of the "OEM config" table in voodoo 3 BIOS */ 352 struct tdfx_bios_cfg { 353 __le32 pciinit0; /* 0x00 */ 354 __le32 miscinit0; /* 0x04 */ 355 __le32 miscinit1; /* 0x08 */ 356 __le32 draminit0; /* 0x0c */ 357 __le32 draminit1; /* 0x10 */ 358 __le32 agpinit0; /* 0x14 */ 359 __le32 pllctrl1; /* 0x18 - memory PLL */ 360 __le32 pllctrl2; /* 0x1c - graphics PLL */ 361 __le32 sgrammode; /* 0x20 - SGRAM/SDRAM mode register data */ 362 } __packed; 363 364 #define TDFX_ROM_CFG_PTR 0x50 365 366 static bool tdfxfb_get_bios_cfg(struct pci_dev *pdev, 367 struct tdfx_bios_cfg *cfg) 368 { 369 u16 romcfg, oemcfg; 370 void __iomem *rom; 371 size_t romsize; 372 u8 *image; 373 u32 khz; 374 375 /* This only works for the Voodoo 3 for now */ 376 if (pdev->device != PCI_DEVICE_ID_3DFX_VOODOO3) 377 return false; 378 379 rom = pci_map_rom(pdev, &romsize); 380 if (!rom || !romsize) 381 return false; 382 383 image = vmalloc(romsize); 384 if (!image) { 385 pci_unmap_rom(pdev, rom); 386 return false; 387 } 388 memcpy_fromio(image, rom, romsize); 389 pci_unmap_rom(pdev, rom); 390 391 /* ROM[0x50] -> ROM config table -> OEM config table */ 392 if (TDFX_ROM_CFG_PTR + 2 > romsize) 393 goto out; 394 romcfg = image[TDFX_ROM_CFG_PTR] | image[TDFX_ROM_CFG_PTR + 1] << 8; 395 if (romcfg == 0xffff || romcfg + 2 > romsize) 396 goto out; 397 oemcfg = image[romcfg] | image[romcfg + 1] << 8; 398 if (oemcfg == 0xffff || oemcfg + sizeof(*cfg) > romsize) 399 goto out; 400 memcpy(cfg, image + oemcfg, sizeof(*cfg)); 401 vfree(image); 402 403 /* 404 * Make sure we didn't read garbage from the BIOS and will 405 * end up setting a frequency that explodes someone's expensive 406 * card. 407 */ 408 khz = tdfx_pll_to_khz(le32_to_cpu(cfg->pllctrl1)); 409 if (khz < 40000 || khz > 250000 || !le32_to_cpu(cfg->draminit0)) 410 return false; 411 return true; 412 413 out: 414 vfree(image); 415 return false; 416 } 417 418 /* 419 * Try to work out if the card was booted or not, just checks if 420 * one of the dram config registers matches what is in the config 421 * table if there is one. 422 * 423 * If we have a BIOS config table attempt to manually boot the 424 * card if needed. 425 */ 426 static int tdfxfb_hw_init(struct fb_info *info, struct pci_dev *pdev) 427 { 428 u32 mempll, gfxpll, draminit0, draminit1, miscinit1, dram_mode; 429 struct tdfx_par *par = info->par; 430 struct tdfx_bios_cfg cfg; 431 bool have_cfg = tdfxfb_get_bios_cfg(pdev, &cfg); 432 433 /* 434 * Can't tell if the card is booted or not, 435 * also cannot boot it. Card might not function. 436 */ 437 if (!have_cfg) 438 return 0; 439 440 /* Card is, probably, already configured. */ 441 if (tdfx_inl(par, DRAMINIT0) == le32_to_cpu(cfg.draminit0)) 442 return 0; 443 444 dev_info(&pdev->dev, 445 "Manually booting card using config table\n"); 446 447 mempll = le32_to_cpu(cfg.pllctrl1); 448 gfxpll = le32_to_cpu(cfg.pllctrl2); 449 draminit0 = le32_to_cpu(cfg.draminit0); 450 draminit1 = le32_to_cpu(cfg.draminit1); 451 miscinit1 = le32_to_cpu(cfg.miscinit1); 452 dram_mode = le32_to_cpu(cfg.sgrammode); 453 tdfx_outl(par, PCIINIT0, le32_to_cpu(cfg.pciinit0)); 454 tdfx_outl(par, AGPINIT, le32_to_cpu(cfg.agpinit0)); 455 456 /* memory clock, and the graphics clock if the card wants one */ 457 tdfx_outl(par, PLLCTRL1, mempll); 458 if (gfxpll) 459 tdfx_outl(par, PLLCTRL2, gfxpll); 460 /* flush posted writes */ 461 tdfx_inl(par, PLLCTRL1); 462 /* PLL lock */ 463 udelay(100); 464 465 tdfx_outl(par, MISCINIT1, miscinit1); 466 tdfx_outl(par, DRAMINIT0, draminit0); 467 tdfx_outl(par, DRAMINIT1, draminit1); 468 469 /* SDRAM/SGRAM wake up: load the mode register */ 470 tdfx_outl(par, DRAMDATA, dram_mode); 471 tdfx_outl(par, DRAMCOMMAND, 0x10d); 472 473 tdfx_outl(par, LFBMEMORYCONFIG, 0x00001fff); 474 tdfx_outl(par, MISCINIT0, le32_to_cpu(cfg.miscinit0)); 475 476 return 0; 477 } 478 479 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg) 480 { 481 struct tdfx_par *par = info->par; 482 int i; 483 484 banshee_wait_idle(info); 485 486 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01); 487 488 /* Wake the VGA core if it hasn't already been woken up */ 489 tdfx_outl(par, VGAINIT0, reg->vgainit0); 490 vga_outb(par, 0x3c3, 0x01); 491 492 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */ 493 494 banshee_make_room(par, 3); 495 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF); 496 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001); 497 #if 0 498 tdfx_outl(par, PLLCTRL1, reg->mempll); 499 tdfx_outl(par, PLLCTRL2, reg->gfxpll); 500 #endif 501 tdfx_outl(par, PLLCTRL0, reg->vidpll); 502 503 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01); 504 505 for (i = 0; i < 5; i++) 506 seq_outb(par, i, reg->seq[i]); 507 508 for (i = 0; i < 25; i++) 509 crt_outb(par, i, reg->crt[i]); 510 511 for (i = 0; i < 9; i++) 512 gra_outb(par, i, reg->gra[i]); 513 514 for (i = 0; i < 21; i++) 515 att_outb(par, i, reg->att[i]); 516 517 crt_outb(par, 0x1a, reg->ext[0]); 518 crt_outb(par, 0x1b, reg->ext[1]); 519 520 vga_enable_palette(par); 521 vga_enable_video(par); 522 523 banshee_make_room(par, 9); 524 tdfx_outl(par, VGAINIT0, reg->vgainit0); 525 tdfx_outl(par, DACMODE, reg->dacmode); 526 tdfx_outl(par, VIDDESKSTRIDE, reg->stride); 527 tdfx_outl(par, HWCURPATADDR, reg->curspataddr); 528 529 tdfx_outl(par, VIDSCREENSIZE, reg->screensize); 530 tdfx_outl(par, VIDDESKSTART, reg->startaddr); 531 tdfx_outl(par, VIDPROCCFG, reg->vidcfg); 532 tdfx_outl(par, VGAINIT1, reg->vgainit1); 533 tdfx_outl(par, MISCINIT0, reg->miscinit0); 534 535 banshee_make_room(par, 8); 536 tdfx_outl(par, SRCBASE, reg->startaddr); 537 tdfx_outl(par, DSTBASE, reg->startaddr); 538 tdfx_outl(par, COMMANDEXTRA_2D, 0); 539 tdfx_outl(par, CLIP0MIN, 0); 540 tdfx_outl(par, CLIP0MAX, 0x0fff0fff); 541 tdfx_outl(par, CLIP1MIN, 0); 542 tdfx_outl(par, CLIP1MAX, 0x0fff0fff); 543 tdfx_outl(par, SRCXY, 0); 544 545 banshee_wait_idle(info); 546 } 547 548 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id) 549 { 550 u32 draminit0 = tdfx_inl(par, DRAMINIT0); 551 u32 draminit1 = tdfx_inl(par, DRAMINIT1); 552 u32 miscinit1; 553 int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4; 554 int chip_size; /* in MB */ 555 int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM; 556 557 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) { 558 /* Banshee/Voodoo3 */ 559 chip_size = 2; 560 if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE)) 561 chip_size = 1; 562 } else { 563 /* Voodoo4/5 */ 564 has_sgram = 0; 565 chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK; 566 chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT); 567 } 568 569 /* disable block writes for SDRAM */ 570 miscinit1 = tdfx_inl(par, MISCINIT1); 571 miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS; 572 miscinit1 |= MISCINIT1_CLUT_INV; 573 574 banshee_make_room(par, 1); 575 tdfx_outl(par, MISCINIT1, miscinit1); 576 return num_chips * chip_size * 1024l * 1024; 577 } 578 579 /* ------------------------------------------------------------------------- */ 580 581 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 582 { 583 struct tdfx_par *par = info->par; 584 u32 lpitch; 585 586 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && 587 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) { 588 DPRINTK("depth not supported: %u\n", var->bits_per_pixel); 589 return -EINVAL; 590 } 591 592 if (var->xres != var->xres_virtual) 593 var->xres_virtual = var->xres; 594 595 if (var->yres > var->yres_virtual) 596 var->yres_virtual = var->yres; 597 598 if (var->xoffset) { 599 DPRINTK("xoffset not supported\n"); 600 return -EINVAL; 601 } 602 var->yoffset = 0; 603 604 /* 605 * Banshee doesn't support interlace, but Voodoo4/5 and probably 606 * Voodoo3 do. 607 * no direct information about device id now? 608 * use max_pixclock for this... 609 */ 610 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) && 611 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) { 612 DPRINTK("interlace not supported\n"); 613 return -EINVAL; 614 } 615 616 if (info->monspecs.hfmax && info->monspecs.vfmax && 617 info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) { 618 DPRINTK("mode outside monitor's specs\n"); 619 return -EINVAL; 620 } 621 622 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */ 623 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3); 624 625 if (var->xres < 320 || var->xres > 2048) { 626 DPRINTK("width not supported: %u\n", var->xres); 627 return -EINVAL; 628 } 629 630 if (var->yres < 200 || var->yres > 2048) { 631 DPRINTK("height not supported: %u\n", var->yres); 632 return -EINVAL; 633 } 634 635 if (lpitch * var->yres_virtual > info->fix.smem_len) { 636 var->yres_virtual = info->fix.smem_len / lpitch; 637 if (var->yres_virtual < var->yres) { 638 DPRINTK("no memory for screen (%ux%ux%u)\n", 639 var->xres, var->yres_virtual, 640 var->bits_per_pixel); 641 return -EINVAL; 642 } 643 } 644 645 if (!var->pixclock) 646 return -EINVAL; 647 648 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) { 649 DPRINTK("pixclock too high (%ldKHz)\n", 650 PICOS2KHZ(var->pixclock)); 651 return -EINVAL; 652 } 653 654 var->transp.offset = 0; 655 var->transp.length = 0; 656 switch (var->bits_per_pixel) { 657 case 8: 658 var->red.length = 8; 659 var->red.offset = 0; 660 var->green = var->red; 661 var->blue = var->red; 662 break; 663 case 16: 664 var->red.offset = 11; 665 var->red.length = 5; 666 var->green.offset = 5; 667 var->green.length = 6; 668 var->blue.offset = 0; 669 var->blue.length = 5; 670 break; 671 case 32: 672 var->transp.offset = 24; 673 var->transp.length = 8; 674 fallthrough; 675 case 24: 676 var->red.offset = 16; 677 var->green.offset = 8; 678 var->blue.offset = 0; 679 var->red.length = var->green.length = var->blue.length = 8; 680 break; 681 } 682 var->width = -1; 683 var->height = -1; 684 685 var->accel_flags = FB_ACCELF_TEXT; 686 687 DPRINTK("Checking graphics mode at %dx%d depth %d\n", 688 var->xres, var->yres, var->bits_per_pixel); 689 return 0; 690 } 691 692 static int tdfxfb_set_par(struct fb_info *info) 693 { 694 struct tdfx_par *par = info->par; 695 u32 hdispend = info->var.xres; 696 u32 hsyncsta = hdispend + info->var.right_margin; 697 u32 hsyncend = hsyncsta + info->var.hsync_len; 698 u32 htotal = hsyncend + info->var.left_margin; 699 u32 hd, hs, he, ht, hbs, hbe; 700 u32 vd, vs, ve, vt, vbs, vbe; 701 struct banshee_reg reg; 702 int fout, freq; 703 u32 wd; 704 u32 cpp = (info->var.bits_per_pixel + 7) >> 3; 705 706 memset(®, 0, sizeof(reg)); 707 708 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | 709 VIDCFG_CURS_X11 | 710 ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | 711 (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0); 712 713 /* PLL settings */ 714 freq = PICOS2KHZ(info->var.pixclock); 715 716 reg.vidcfg &= ~VIDCFG_2X; 717 718 if (freq > par->max_pixclock / 2) { 719 freq = freq > par->max_pixclock ? par->max_pixclock : freq; 720 reg.dacmode |= DACMODE_2X; 721 reg.vidcfg |= VIDCFG_2X; 722 hdispend >>= 1; 723 hsyncsta >>= 1; 724 hsyncend >>= 1; 725 htotal >>= 1; 726 } 727 728 wd = (hdispend >> 3) - 1; 729 hd = wd; 730 hs = (hsyncsta >> 3) - 1; 731 he = (hsyncend >> 3) - 1; 732 ht = (htotal >> 3) - 1; 733 hbs = hd; 734 hbe = ht; 735 736 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) { 737 vd = (info->var.yres << 1) - 1; 738 vs = vd + (info->var.lower_margin << 1); 739 ve = vs + (info->var.vsync_len << 1); 740 vt = ve + (info->var.upper_margin << 1) - 1; 741 reg.screensize = info->var.xres | (info->var.yres << 13); 742 reg.vidcfg |= VIDCFG_HALF_MODE; 743 reg.crt[VGA_CRTC_MAX_SCAN] = 0x80; 744 } else { 745 vd = info->var.yres - 1; 746 vs = vd + info->var.lower_margin; 747 ve = vs + info->var.vsync_len; 748 vt = ve + info->var.upper_margin - 1; 749 reg.screensize = info->var.xres | (info->var.yres << 12); 750 reg.vidcfg &= ~VIDCFG_HALF_MODE; 751 } 752 vbs = vd; 753 vbe = vt; 754 755 /* this is all pretty standard VGA register stuffing */ 756 reg.misc[0x00] = 0x0f | 757 (info->var.xres < 400 ? 0xa0 : 758 info->var.xres < 480 ? 0x60 : 759 info->var.xres < 768 ? 0xe0 : 0x20); 760 761 reg.gra[VGA_GFX_MODE] = 0x40; 762 reg.gra[VGA_GFX_MISC] = 0x05; 763 reg.gra[VGA_GFX_COMPARE_MASK] = 0x0f; 764 reg.gra[VGA_GFX_BIT_MASK] = 0xff; 765 766 reg.att[VGA_ATC_PALETTE0] = 0x00; 767 reg.att[VGA_ATC_PALETTE1] = 0x01; 768 reg.att[VGA_ATC_PALETTE2] = 0x02; 769 reg.att[VGA_ATC_PALETTE3] = 0x03; 770 reg.att[VGA_ATC_PALETTE4] = 0x04; 771 reg.att[VGA_ATC_PALETTE5] = 0x05; 772 reg.att[VGA_ATC_PALETTE6] = 0x06; 773 reg.att[VGA_ATC_PALETTE7] = 0x07; 774 reg.att[VGA_ATC_PALETTE8] = 0x08; 775 reg.att[VGA_ATC_PALETTE9] = 0x09; 776 reg.att[VGA_ATC_PALETTEA] = 0x0a; 777 reg.att[VGA_ATC_PALETTEB] = 0x0b; 778 reg.att[VGA_ATC_PALETTEC] = 0x0c; 779 reg.att[VGA_ATC_PALETTED] = 0x0d; 780 reg.att[VGA_ATC_PALETTEE] = 0x0e; 781 reg.att[VGA_ATC_PALETTEF] = 0x0f; 782 reg.att[VGA_ATC_MODE] = 0x41; 783 reg.att[VGA_ATC_PLANE_ENABLE] = 0x0f; 784 785 reg.seq[VGA_SEQ_RESET] = 0x03; 786 reg.seq[VGA_SEQ_CLOCK_MODE] = 0x01; /* fixme: clkdiv2? */ 787 reg.seq[VGA_SEQ_PLANE_WRITE] = 0x0f; 788 reg.seq[VGA_SEQ_CHARACTER_MAP] = 0x00; 789 reg.seq[VGA_SEQ_MEMORY_MODE] = 0x0e; 790 791 reg.crt[VGA_CRTC_H_TOTAL] = ht - 4; 792 reg.crt[VGA_CRTC_H_DISP] = hd; 793 reg.crt[VGA_CRTC_H_BLANK_START] = hbs; 794 reg.crt[VGA_CRTC_H_BLANK_END] = 0x80 | (hbe & 0x1f); 795 reg.crt[VGA_CRTC_H_SYNC_START] = hs; 796 reg.crt[VGA_CRTC_H_SYNC_END] = ((hbe & 0x20) << 2) | (he & 0x1f); 797 reg.crt[VGA_CRTC_V_TOTAL] = vt; 798 reg.crt[VGA_CRTC_OVERFLOW] = ((vs & 0x200) >> 2) | 799 ((vd & 0x200) >> 3) | 800 ((vt & 0x200) >> 4) | 0x10 | 801 ((vbs & 0x100) >> 5) | 802 ((vs & 0x100) >> 6) | 803 ((vd & 0x100) >> 7) | 804 ((vt & 0x100) >> 8); 805 reg.crt[VGA_CRTC_MAX_SCAN] |= 0x40 | ((vbs & 0x200) >> 4); 806 reg.crt[VGA_CRTC_V_SYNC_START] = vs; 807 reg.crt[VGA_CRTC_V_SYNC_END] = (ve & 0x0f) | 0x20; 808 reg.crt[VGA_CRTC_V_DISP_END] = vd; 809 reg.crt[VGA_CRTC_OFFSET] = wd; 810 reg.crt[VGA_CRTC_V_BLANK_START] = vbs; 811 reg.crt[VGA_CRTC_V_BLANK_END] = vbe + 1; 812 reg.crt[VGA_CRTC_MODE] = 0xc3; 813 reg.crt[VGA_CRTC_LINE_COMPARE] = 0xff; 814 815 /* Banshee's nonvga stuff */ 816 reg.ext[0x00] = (((ht & 0x100) >> 8) | 817 ((hd & 0x100) >> 6) | 818 ((hbs & 0x100) >> 4) | 819 ((hbe & 0x40) >> 1) | 820 ((hs & 0x100) >> 2) | 821 ((he & 0x20) << 2)); 822 reg.ext[0x01] = (((vt & 0x400) >> 10) | 823 ((vd & 0x400) >> 8) | 824 ((vbs & 0x400) >> 6) | 825 ((vbe & 0x400) >> 4)); 826 827 reg.vgainit0 = VGAINIT0_8BIT_DAC | 828 VGAINIT0_EXT_ENABLE | 829 VGAINIT0_WAKEUP_3C3 | 830 VGAINIT0_ALT_READBACK | 831 VGAINIT0_EXTSHIFTOUT; 832 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff; 833 834 if (hwcursor) 835 reg.curspataddr = info->fix.smem_len; 836 837 reg.cursloc = 0; 838 839 reg.cursc0 = 0; 840 reg.cursc1 = 0xffffff; 841 842 reg.stride = info->var.xres * cpp; 843 reg.startaddr = info->var.yoffset * reg.stride 844 + info->var.xoffset * cpp; 845 846 reg.vidpll = do_calc_pll(freq, &fout); 847 #if 0 848 reg.mempll = do_calc_pll(..., &fout); 849 reg.gfxpll = do_calc_pll(..., &fout); 850 #endif 851 852 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 853 reg.vidcfg |= VIDCFG_INTERLACE; 854 reg.miscinit0 = tdfx_inl(par, MISCINIT0); 855 856 #if defined(__BIG_ENDIAN) 857 switch (info->var.bits_per_pixel) { 858 case 8: 859 case 24: 860 reg.miscinit0 &= ~(1 << 30); 861 reg.miscinit0 &= ~(1 << 31); 862 break; 863 case 16: 864 reg.miscinit0 |= (1 << 30); 865 reg.miscinit0 |= (1 << 31); 866 break; 867 case 32: 868 reg.miscinit0 |= (1 << 30); 869 reg.miscinit0 &= ~(1 << 31); 870 break; 871 } 872 #endif 873 do_write_regs(info, ®); 874 875 /* Now change fb_fix_screeninfo according to changes in par */ 876 info->fix.line_length = reg.stride; 877 info->fix.visual = (info->var.bits_per_pixel == 8) 878 ? FB_VISUAL_PSEUDOCOLOR 879 : FB_VISUAL_TRUECOLOR; 880 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", 881 info->var.xres, info->var.yres, info->var.bits_per_pixel); 882 return 0; 883 } 884 885 /* A handy macro shamelessly pinched from matroxfb */ 886 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) 887 888 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green, 889 unsigned blue, unsigned transp, 890 struct fb_info *info) 891 { 892 struct tdfx_par *par = info->par; 893 u32 rgbcol; 894 895 if (regno >= info->cmap.len || regno > 255) 896 return 1; 897 898 /* grayscale works only partially under directcolor */ 899 if (info->var.grayscale) { 900 /* grayscale = 0.30*R + 0.59*G + 0.11*B */ 901 blue = (red * 77 + green * 151 + blue * 28) >> 8; 902 green = blue; 903 red = blue; 904 } 905 906 switch (info->fix.visual) { 907 case FB_VISUAL_PSEUDOCOLOR: 908 rgbcol = (((u32)red & 0xff00) << 8) | 909 (((u32)green & 0xff00) << 0) | 910 (((u32)blue & 0xff00) >> 8); 911 do_setpalentry(par, regno, rgbcol); 912 break; 913 /* Truecolor has no hardware color palettes. */ 914 case FB_VISUAL_TRUECOLOR: 915 if (regno < 16) { 916 rgbcol = (CNVT_TOHW(red, info->var.red.length) << 917 info->var.red.offset) | 918 (CNVT_TOHW(green, info->var.green.length) << 919 info->var.green.offset) | 920 (CNVT_TOHW(blue, info->var.blue.length) << 921 info->var.blue.offset) | 922 (CNVT_TOHW(transp, info->var.transp.length) << 923 info->var.transp.offset); 924 par->palette[regno] = rgbcol; 925 } 926 927 break; 928 default: 929 DPRINTK("bad depth %u\n", info->var.bits_per_pixel); 930 break; 931 } 932 933 return 0; 934 } 935 936 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */ 937 static int tdfxfb_blank(int blank, struct fb_info *info) 938 { 939 struct tdfx_par *par = info->par; 940 int vgablank = 1; 941 u32 dacmode = tdfx_inl(par, DACMODE); 942 943 dacmode &= ~(BIT(1) | BIT(3)); 944 945 switch (blank) { 946 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */ 947 vgablank = 0; 948 break; 949 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */ 950 break; 951 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */ 952 dacmode |= BIT(3); 953 break; 954 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */ 955 dacmode |= BIT(1); 956 break; 957 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */ 958 dacmode |= BIT(1) | BIT(3); 959 break; 960 } 961 962 banshee_make_room(par, 1); 963 tdfx_outl(par, DACMODE, dacmode); 964 if (vgablank) 965 vga_disable_video(par); 966 else 967 vga_enable_video(par); 968 return 0; 969 } 970 971 /* 972 * Set the starting position of the visible screen to var->yoffset 973 */ 974 static int tdfxfb_pan_display(struct fb_var_screeninfo *var, 975 struct fb_info *info) 976 { 977 struct tdfx_par *par = info->par; 978 u32 addr = var->yoffset * info->fix.line_length; 979 980 if (nopan || var->xoffset) 981 return -EINVAL; 982 983 banshee_make_room(par, 1); 984 tdfx_outl(par, VIDDESKSTART, addr); 985 986 return 0; 987 } 988 989 #ifdef CONFIG_FB_3DFX_ACCEL 990 /* 991 * FillRect 2D command (solidfill or invert (via ROP_XOR)) 992 */ 993 static void tdfxfb_fillrect(struct fb_info *info, 994 const struct fb_fillrect *rect) 995 { 996 struct tdfx_par *par = info->par; 997 u32 bpp = info->var.bits_per_pixel; 998 u32 stride = info->fix.line_length; 999 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 1000 int tdfx_rop; 1001 u32 dx = rect->dx; 1002 u32 dy = rect->dy; 1003 u32 dstbase = 0; 1004 1005 if (rect->rop == ROP_COPY) 1006 tdfx_rop = TDFX_ROP_COPY; 1007 else 1008 tdfx_rop = TDFX_ROP_XOR; 1009 1010 /* assume always rect->height < 4096 */ 1011 if (dy + rect->height > 4095) { 1012 dstbase = stride * dy; 1013 dy = 0; 1014 } 1015 /* assume always rect->width < 4096 */ 1016 if (dx + rect->width > 4095) { 1017 dstbase += dx * bpp >> 3; 1018 dx = 0; 1019 } 1020 banshee_make_room(par, 6); 1021 tdfx_outl(par, DSTFORMAT, fmt); 1022 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) { 1023 tdfx_outl(par, COLORFORE, rect->color); 1024 } else { /* FB_VISUAL_TRUECOLOR */ 1025 tdfx_outl(par, COLORFORE, par->palette[rect->color]); 1026 } 1027 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24)); 1028 tdfx_outl(par, DSTBASE, dstbase); 1029 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16)); 1030 tdfx_outl(par, LAUNCH_2D, dx | (dy << 16)); 1031 } 1032 1033 /* 1034 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) 1035 */ 1036 static void tdfxfb_copyarea(struct fb_info *info, 1037 const struct fb_copyarea *area) 1038 { 1039 struct tdfx_par *par = info->par; 1040 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy; 1041 u32 bpp = info->var.bits_per_pixel; 1042 u32 stride = info->fix.line_length; 1043 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24); 1044 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 1045 u32 dstbase = 0; 1046 u32 srcbase = 0; 1047 1048 /* assume always area->height < 4096 */ 1049 if (sy + area->height > 4095) { 1050 srcbase = stride * sy; 1051 sy = 0; 1052 } 1053 /* assume always area->width < 4096 */ 1054 if (sx + area->width > 4095) { 1055 srcbase += sx * bpp >> 3; 1056 sx = 0; 1057 } 1058 /* assume always area->height < 4096 */ 1059 if (dy + area->height > 4095) { 1060 dstbase = stride * dy; 1061 dy = 0; 1062 } 1063 /* assume always area->width < 4096 */ 1064 if (dx + area->width > 4095) { 1065 dstbase += dx * bpp >> 3; 1066 dx = 0; 1067 } 1068 1069 if (area->sx <= area->dx) { 1070 /* -X */ 1071 blitcmd |= BIT(14); 1072 sx += area->width - 1; 1073 dx += area->width - 1; 1074 } 1075 if (area->sy <= area->dy) { 1076 /* -Y */ 1077 blitcmd |= BIT(15); 1078 sy += area->height - 1; 1079 dy += area->height - 1; 1080 } 1081 1082 banshee_make_room(par, 8); 1083 1084 tdfx_outl(par, SRCFORMAT, fmt); 1085 tdfx_outl(par, DSTFORMAT, fmt); 1086 tdfx_outl(par, COMMAND_2D, blitcmd); 1087 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16)); 1088 tdfx_outl(par, DSTXY, dx | (dy << 16)); 1089 tdfx_outl(par, SRCBASE, srcbase); 1090 tdfx_outl(par, DSTBASE, dstbase); 1091 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16)); 1092 } 1093 1094 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image) 1095 { 1096 struct tdfx_par *par = info->par; 1097 int size = image->height * ((image->width * image->depth + 7) >> 3); 1098 int fifo_free; 1099 int i, stride = info->fix.line_length; 1100 u32 bpp = info->var.bits_per_pixel; 1101 u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 1102 u8 *chardata = (u8 *) image->data; 1103 u32 srcfmt; 1104 u32 dx = image->dx; 1105 u32 dy = image->dy; 1106 u32 dstbase = 0; 1107 1108 if (image->depth != 1) { 1109 #ifdef BROKEN_CODE 1110 banshee_make_room(par, 6 + ((size + 3) >> 2)); 1111 srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) | 1112 0x400000; 1113 #else 1114 cfb_imageblit(info, image); 1115 #endif 1116 return; 1117 } 1118 banshee_make_room(par, 9); 1119 switch (info->fix.visual) { 1120 case FB_VISUAL_PSEUDOCOLOR: 1121 tdfx_outl(par, COLORFORE, image->fg_color); 1122 tdfx_outl(par, COLORBACK, image->bg_color); 1123 break; 1124 case FB_VISUAL_TRUECOLOR: 1125 default: 1126 tdfx_outl(par, COLORFORE, 1127 par->palette[image->fg_color]); 1128 tdfx_outl(par, COLORBACK, 1129 par->palette[image->bg_color]); 1130 } 1131 #ifdef __BIG_ENDIAN 1132 srcfmt = 0x400000 | BIT(20); 1133 #else 1134 srcfmt = 0x400000; 1135 #endif 1136 /* assume always image->height < 4096 */ 1137 if (dy + image->height > 4095) { 1138 dstbase = stride * dy; 1139 dy = 0; 1140 } 1141 /* assume always image->width < 4096 */ 1142 if (dx + image->width > 4095) { 1143 dstbase += dx * bpp >> 3; 1144 dx = 0; 1145 } 1146 1147 tdfx_outl(par, DSTBASE, dstbase); 1148 tdfx_outl(par, SRCXY, 0); 1149 tdfx_outl(par, DSTXY, dx | (dy << 16)); 1150 tdfx_outl(par, COMMAND_2D, 1151 COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24)); 1152 tdfx_outl(par, SRCFORMAT, srcfmt); 1153 tdfx_outl(par, DSTFORMAT, dstfmt); 1154 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16)); 1155 1156 /* A count of how many free FIFO entries we've requested. 1157 * When this goes negative, we need to request more. */ 1158 fifo_free = 0; 1159 1160 /* Send four bytes at a time of data */ 1161 for (i = (size >> 2); i > 0; i--) { 1162 if (--fifo_free < 0) { 1163 fifo_free = 31; 1164 banshee_make_room(par, fifo_free); 1165 } 1166 tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata); 1167 chardata += 4; 1168 } 1169 1170 /* Send the leftovers now */ 1171 banshee_make_room(par, 3); 1172 switch (size % 4) { 1173 case 0: 1174 break; 1175 case 1: 1176 tdfx_outl(par, LAUNCH_2D, *chardata); 1177 break; 1178 case 2: 1179 tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata); 1180 break; 1181 case 3: 1182 tdfx_outl(par, LAUNCH_2D, 1183 *(u16 *)chardata | (chardata[3] << 24)); 1184 break; 1185 } 1186 } 1187 #endif /* CONFIG_FB_3DFX_ACCEL */ 1188 1189 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1190 { 1191 struct tdfx_par *par = info->par; 1192 u32 vidcfg; 1193 1194 if (!hwcursor) 1195 return -EINVAL; /* just to force soft_cursor() call */ 1196 1197 /* Too large of a cursor or wrong bpp :-( */ 1198 if (cursor->image.width > 64 || 1199 cursor->image.height > 64 || 1200 cursor->image.depth > 1) 1201 return -EINVAL; 1202 1203 vidcfg = tdfx_inl(par, VIDPROCCFG); 1204 if (cursor->enable) 1205 tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE); 1206 else 1207 tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE); 1208 1209 /* 1210 * If the cursor is not be changed this means either we want the 1211 * current cursor state (if enable is set) or we want to query what 1212 * we can do with the cursor (if enable is not set) 1213 */ 1214 if (!cursor->set) 1215 return 0; 1216 1217 /* fix cursor color - XFree86 forgets to restore it properly */ 1218 if (cursor->set & FB_CUR_SETCMAP) { 1219 struct fb_cmap cmap = info->cmap; 1220 u32 bg_idx = cursor->image.bg_color; 1221 u32 fg_idx = cursor->image.fg_color; 1222 unsigned long bg_color, fg_color; 1223 1224 fg_color = (((u32)cmap.red[fg_idx] & 0xff00) << 8) | 1225 (((u32)cmap.green[fg_idx] & 0xff00) << 0) | 1226 (((u32)cmap.blue[fg_idx] & 0xff00) >> 8); 1227 bg_color = (((u32)cmap.red[bg_idx] & 0xff00) << 8) | 1228 (((u32)cmap.green[bg_idx] & 0xff00) << 0) | 1229 (((u32)cmap.blue[bg_idx] & 0xff00) >> 8); 1230 banshee_make_room(par, 2); 1231 tdfx_outl(par, HWCURC0, bg_color); 1232 tdfx_outl(par, HWCURC1, fg_color); 1233 } 1234 1235 if (cursor->set & FB_CUR_SETPOS) { 1236 int x = cursor->image.dx; 1237 int y = cursor->image.dy - info->var.yoffset; 1238 1239 x += 63; 1240 y += 63; 1241 banshee_make_room(par, 1); 1242 tdfx_outl(par, HWCURLOC, (y << 16) + x); 1243 } 1244 if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) { 1245 /* 1246 * Voodoo 3 and above cards use 2 monochrome cursor patterns. 1247 * The reason is so the card can fetch 8 words at a time 1248 * and are stored on chip for use for the next 8 scanlines. 1249 * This reduces the number of times for access to draw the 1250 * cursor for each screen refresh. 1251 * Each pattern is a bitmap of 64 bit wide and 64 bit high 1252 * (total of 8192 bits or 1024 bytes). The two patterns are 1253 * stored in such a way that pattern 0 always resides in the 1254 * lower half (least significant 64 bits) of a 128 bit word 1255 * and pattern 1 the upper half. If you examine the data of 1256 * the cursor image the graphics card uses then from the 1257 * beginning you see line one of pattern 0, line one of 1258 * pattern 1, line two of pattern 0, line two of pattern 1, 1259 * etc etc. The linear stride for the cursor is always 16 bytes 1260 * (128 bits) which is the maximum cursor width times two for 1261 * the two monochrome patterns. 1262 */ 1263 u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len; 1264 u8 *bitmap = (u8 *)cursor->image.data; 1265 u8 *mask = (u8 *)cursor->mask; 1266 int i; 1267 1268 fb_memset_io(cursorbase, 0, 1024); 1269 1270 for (i = 0; i < cursor->image.height; i++) { 1271 int h = 0; 1272 int j = (cursor->image.width + 7) >> 3; 1273 1274 for (; j > 0; j--) { 1275 u8 data = *mask ^ *bitmap; 1276 if (cursor->rop == ROP_COPY) 1277 data = *mask & *bitmap; 1278 /* Pattern 0. Copy the cursor mask to it */ 1279 fb_writeb(*mask, cursorbase + h); 1280 mask++; 1281 /* Pattern 1. Copy the cursor bitmap to it */ 1282 fb_writeb(data, cursorbase + h + 8); 1283 bitmap++; 1284 h++; 1285 } 1286 cursorbase += 16; 1287 } 1288 } 1289 return 0; 1290 } 1291 1292 static const struct fb_ops tdfxfb_ops = { 1293 .owner = THIS_MODULE, 1294 __FB_DEFAULT_IOMEM_OPS_RDWR, 1295 .fb_check_var = tdfxfb_check_var, 1296 .fb_set_par = tdfxfb_set_par, 1297 .fb_setcolreg = tdfxfb_setcolreg, 1298 .fb_blank = tdfxfb_blank, 1299 .fb_pan_display = tdfxfb_pan_display, 1300 .fb_sync = banshee_wait_idle, 1301 .fb_cursor = tdfxfb_cursor, 1302 #ifdef CONFIG_FB_3DFX_ACCEL 1303 .fb_fillrect = tdfxfb_fillrect, 1304 .fb_copyarea = tdfxfb_copyarea, 1305 .fb_imageblit = tdfxfb_imageblit, 1306 #else 1307 __FB_DEFAULT_IOMEM_OPS_DRAW, 1308 #endif 1309 __FB_DEFAULT_IOMEM_OPS_MMAP, 1310 }; 1311 1312 #ifdef CONFIG_FB_3DFX_I2C 1313 /* The voo GPIO registers don't have individual masks for each bit 1314 so we always have to read before writing. */ 1315 1316 static void tdfxfb_i2c_setscl(void *data, int val) 1317 { 1318 struct tdfxfb_i2c_chan *chan = data; 1319 struct tdfx_par *par = chan->par; 1320 unsigned int r; 1321 1322 r = tdfx_inl(par, VIDSERPARPORT); 1323 if (val) 1324 r |= I2C_SCL_OUT; 1325 else 1326 r &= ~I2C_SCL_OUT; 1327 tdfx_outl(par, VIDSERPARPORT, r); 1328 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1329 } 1330 1331 static void tdfxfb_i2c_setsda(void *data, int val) 1332 { 1333 struct tdfxfb_i2c_chan *chan = data; 1334 struct tdfx_par *par = chan->par; 1335 unsigned int r; 1336 1337 r = tdfx_inl(par, VIDSERPARPORT); 1338 if (val) 1339 r |= I2C_SDA_OUT; 1340 else 1341 r &= ~I2C_SDA_OUT; 1342 tdfx_outl(par, VIDSERPARPORT, r); 1343 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1344 } 1345 1346 /* The GPIO pins are open drain, so the pins always remain outputs. 1347 We rely on the i2c-algo-bit routines to set the pins high before 1348 reading the input from other chips. */ 1349 1350 static int tdfxfb_i2c_getscl(void *data) 1351 { 1352 struct tdfxfb_i2c_chan *chan = data; 1353 struct tdfx_par *par = chan->par; 1354 1355 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN)); 1356 } 1357 1358 static int tdfxfb_i2c_getsda(void *data) 1359 { 1360 struct tdfxfb_i2c_chan *chan = data; 1361 struct tdfx_par *par = chan->par; 1362 1363 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN)); 1364 } 1365 1366 static void tdfxfb_ddc_setscl(void *data, int val) 1367 { 1368 struct tdfxfb_i2c_chan *chan = data; 1369 struct tdfx_par *par = chan->par; 1370 unsigned int r; 1371 1372 r = tdfx_inl(par, VIDSERPARPORT); 1373 if (val) 1374 r |= DDC_SCL_OUT; 1375 else 1376 r &= ~DDC_SCL_OUT; 1377 tdfx_outl(par, VIDSERPARPORT, r); 1378 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1379 } 1380 1381 static void tdfxfb_ddc_setsda(void *data, int val) 1382 { 1383 struct tdfxfb_i2c_chan *chan = data; 1384 struct tdfx_par *par = chan->par; 1385 unsigned int r; 1386 1387 r = tdfx_inl(par, VIDSERPARPORT); 1388 if (val) 1389 r |= DDC_SDA_OUT; 1390 else 1391 r &= ~DDC_SDA_OUT; 1392 tdfx_outl(par, VIDSERPARPORT, r); 1393 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1394 } 1395 1396 static int tdfxfb_ddc_getscl(void *data) 1397 { 1398 struct tdfxfb_i2c_chan *chan = data; 1399 struct tdfx_par *par = chan->par; 1400 1401 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN)); 1402 } 1403 1404 static int tdfxfb_ddc_getsda(void *data) 1405 { 1406 struct tdfxfb_i2c_chan *chan = data; 1407 struct tdfx_par *par = chan->par; 1408 1409 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN)); 1410 } 1411 1412 static int tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, const char *name, 1413 struct device *dev) 1414 { 1415 int rc; 1416 1417 strscpy(chan->adapter.name, name, sizeof(chan->adapter.name)); 1418 chan->adapter.owner = THIS_MODULE; 1419 chan->adapter.algo_data = &chan->algo; 1420 chan->adapter.dev.parent = dev; 1421 chan->algo.setsda = tdfxfb_ddc_setsda; 1422 chan->algo.setscl = tdfxfb_ddc_setscl; 1423 chan->algo.getsda = tdfxfb_ddc_getsda; 1424 chan->algo.getscl = tdfxfb_ddc_getscl; 1425 chan->algo.udelay = 10; 1426 chan->algo.timeout = msecs_to_jiffies(500); 1427 chan->algo.data = chan; 1428 1429 i2c_set_adapdata(&chan->adapter, chan); 1430 1431 rc = i2c_bit_add_bus(&chan->adapter); 1432 if (rc == 0) 1433 DPRINTK("I2C bus %s registered.\n", name); 1434 else 1435 chan->par = NULL; 1436 1437 return rc; 1438 } 1439 1440 static int tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan, const char *name, 1441 struct device *dev) 1442 { 1443 int rc; 1444 1445 strscpy(chan->adapter.name, name, sizeof(chan->adapter.name)); 1446 chan->adapter.owner = THIS_MODULE; 1447 chan->adapter.algo_data = &chan->algo; 1448 chan->adapter.dev.parent = dev; 1449 chan->algo.setsda = tdfxfb_i2c_setsda; 1450 chan->algo.setscl = tdfxfb_i2c_setscl; 1451 chan->algo.getsda = tdfxfb_i2c_getsda; 1452 chan->algo.getscl = tdfxfb_i2c_getscl; 1453 chan->algo.udelay = 10; 1454 chan->algo.timeout = msecs_to_jiffies(500); 1455 chan->algo.data = chan; 1456 1457 i2c_set_adapdata(&chan->adapter, chan); 1458 1459 rc = i2c_bit_add_bus(&chan->adapter); 1460 if (rc == 0) 1461 DPRINTK("I2C bus %s registered.\n", name); 1462 else 1463 chan->par = NULL; 1464 1465 return rc; 1466 } 1467 1468 static void tdfxfb_create_i2c_busses(struct fb_info *info) 1469 { 1470 struct tdfx_par *par = info->par; 1471 1472 tdfx_outl(par, VIDINFORMAT, 0x8160); 1473 tdfx_outl(par, VIDSERPARPORT, 0xcffc0020); 1474 1475 par->chan[0].par = par; 1476 par->chan[1].par = par; 1477 1478 tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->device); 1479 tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->device); 1480 } 1481 1482 static void tdfxfb_delete_i2c_busses(struct tdfx_par *par) 1483 { 1484 if (par->chan[0].par) 1485 i2c_del_adapter(&par->chan[0].adapter); 1486 par->chan[0].par = NULL; 1487 1488 if (par->chan[1].par) 1489 i2c_del_adapter(&par->chan[1].adapter); 1490 par->chan[1].par = NULL; 1491 } 1492 1493 static int tdfxfb_probe_i2c_connector(struct tdfx_par *par, 1494 struct fb_monspecs *specs) 1495 { 1496 u8 *edid = NULL; 1497 1498 DPRINTK("Probe DDC Bus\n"); 1499 if (par->chan[0].par) 1500 edid = fb_ddc_read(&par->chan[0].adapter); 1501 1502 if (edid) { 1503 fb_edid_to_monspecs(edid, specs); 1504 kfree(edid); 1505 return 0; 1506 } 1507 return 1; 1508 } 1509 #endif /* CONFIG_FB_3DFX_I2C */ 1510 1511 /** 1512 * tdfxfb_probe - Device Initializiation 1513 * 1514 * @pdev: PCI Device to initialize 1515 * @id: PCI Device ID 1516 * 1517 * Initializes and allocates resources for PCI device @pdev. 1518 * 1519 */ 1520 static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1521 { 1522 struct tdfx_par *default_par; 1523 struct fb_info *info; 1524 int err, lpitch; 1525 struct fb_monspecs *specs; 1526 bool found; 1527 1528 err = aperture_remove_conflicting_pci_devices(pdev, "tdfxfb"); 1529 if (err) 1530 return err; 1531 1532 err = pcim_enable_device(pdev); 1533 if (err) { 1534 printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err); 1535 return err; 1536 } 1537 1538 info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev); 1539 1540 if (!info) 1541 return -ENOMEM; 1542 1543 default_par = info->par; 1544 info->fix = tdfx_fix; 1545 1546 /* Configure the default fb_fix_screeninfo first */ 1547 switch (pdev->device) { 1548 case PCI_DEVICE_ID_3DFX_BANSHEE: 1549 strcpy(info->fix.id, "3Dfx Banshee"); 1550 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK; 1551 break; 1552 case PCI_DEVICE_ID_3DFX_VOODOO3: 1553 strcpy(info->fix.id, "3Dfx Voodoo3"); 1554 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK; 1555 break; 1556 case PCI_DEVICE_ID_3DFX_VOODOO5: 1557 strcpy(info->fix.id, "3Dfx Voodoo5"); 1558 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK; 1559 break; 1560 } 1561 1562 info->fix.mmio_start = pci_resource_start(pdev, 0); 1563 info->fix.mmio_len = pci_resource_len(pdev, 0); 1564 if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len, 1565 "tdfx regbase")) { 1566 printk(KERN_ERR "tdfxfb: Can't reserve regbase\n"); 1567 goto out_err; 1568 } 1569 1570 default_par->regbase_virt = 1571 ioremap(info->fix.mmio_start, info->fix.mmio_len); 1572 if (!default_par->regbase_virt) { 1573 printk(KERN_ERR "fb: Can't remap %s register area.\n", 1574 info->fix.id); 1575 goto out_err_regbase; 1576 } 1577 1578 if (tdfxfb_hw_init(info, pdev)) 1579 goto out_err_regbase; 1580 1581 info->fix.smem_start = pci_resource_start(pdev, 1); 1582 info->fix.smem_len = do_lfb_size(default_par, pdev->device); 1583 if (!info->fix.smem_len) { 1584 printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id); 1585 goto out_err_regbase; 1586 } 1587 1588 if (!request_mem_region(info->fix.smem_start, 1589 pci_resource_len(pdev, 1), "tdfx smem")) { 1590 printk(KERN_ERR "tdfxfb: Can't reserve smem\n"); 1591 goto out_err_regbase; 1592 } 1593 1594 info->screen_base = ioremap_wc(info->fix.smem_start, 1595 info->fix.smem_len); 1596 if (!info->screen_base) { 1597 printk(KERN_ERR "fb: Can't remap %s framebuffer.\n", 1598 info->fix.id); 1599 goto out_err_screenbase; 1600 } 1601 1602 default_par->iobase = pci_resource_start(pdev, 2); 1603 1604 if (!request_region(pci_resource_start(pdev, 2), 1605 pci_resource_len(pdev, 2), "tdfx iobase")) { 1606 printk(KERN_ERR "tdfxfb: Can't reserve iobase\n"); 1607 goto out_err_screenbase; 1608 } 1609 1610 printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id, 1611 info->fix.smem_len >> 10); 1612 1613 if (!nomtrr) 1614 default_par->wc_cookie= arch_phys_wc_add(info->fix.smem_start, 1615 info->fix.smem_len); 1616 1617 info->fix.ypanstep = nopan ? 0 : 1; 1618 info->fix.ywrapstep = nowrap ? 0 : 1; 1619 1620 info->fbops = &tdfxfb_ops; 1621 info->pseudo_palette = default_par->palette; 1622 info->flags = FBINFO_HWACCEL_YPAN; 1623 #ifdef CONFIG_FB_3DFX_ACCEL 1624 info->flags |= FBINFO_HWACCEL_FILLRECT | 1625 FBINFO_HWACCEL_COPYAREA | 1626 FBINFO_HWACCEL_IMAGEBLIT | 1627 FBINFO_READS_FAST; 1628 #endif 1629 /* reserve 8192 bits for cursor */ 1630 /* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */ 1631 if (hwcursor) 1632 info->fix.smem_len = (info->fix.smem_len - 1024) & 1633 (PAGE_MASK << 1); 1634 specs = &info->monspecs; 1635 found = false; 1636 info->var.bits_per_pixel = 8; 1637 #ifdef CONFIG_FB_3DFX_I2C 1638 tdfxfb_create_i2c_busses(info); 1639 err = tdfxfb_probe_i2c_connector(default_par, specs); 1640 1641 if (!err) { 1642 if (specs->modedb == NULL) 1643 DPRINTK("Unable to get Mode Database\n"); 1644 else { 1645 const struct fb_videomode *m; 1646 1647 fb_videomode_to_modelist(specs->modedb, 1648 specs->modedb_len, 1649 &info->modelist); 1650 m = fb_find_best_display(specs, &info->modelist); 1651 if (m) { 1652 fb_videomode_to_var(&info->var, m); 1653 /* fill all other info->var's fields */ 1654 if (tdfxfb_check_var(&info->var, info) < 0) 1655 info->var = tdfx_var; 1656 else 1657 found = true; 1658 } 1659 } 1660 } 1661 #endif 1662 if (!mode_option && !found) 1663 mode_option = "640x480@60"; 1664 1665 if (mode_option) { 1666 err = fb_find_mode(&info->var, info, mode_option, 1667 specs->modedb, specs->modedb_len, 1668 NULL, info->var.bits_per_pixel); 1669 if (!err || err == 4) 1670 info->var = tdfx_var; 1671 } 1672 1673 if (found) { 1674 fb_destroy_modedb(specs->modedb); 1675 specs->modedb = NULL; 1676 } 1677 1678 /* maximize virtual vertical length */ 1679 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3); 1680 info->var.yres_virtual = info->fix.smem_len / lpitch; 1681 if (info->var.yres_virtual < info->var.yres) 1682 goto out_err_iobase; 1683 1684 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { 1685 printk(KERN_ERR "tdfxfb: Can't allocate color map\n"); 1686 goto out_err_iobase; 1687 } 1688 1689 /* 1690 * Program a video mode and clear the framebuffer now, this 1691 * ensures the display comes up even if fbcon doesn't bind 1692 * when the framebuffer is registered. 1693 */ 1694 tdfxfb_set_par(info); 1695 memset_io(info->screen_base, 0, info->fix.smem_len); 1696 1697 if (register_framebuffer(info) < 0) { 1698 printk(KERN_ERR "tdfxfb: can't register framebuffer\n"); 1699 fb_dealloc_cmap(&info->cmap); 1700 goto out_err_iobase; 1701 } 1702 /* 1703 * Our driver data 1704 */ 1705 pci_set_drvdata(pdev, info); 1706 return 0; 1707 1708 out_err_iobase: 1709 #ifdef CONFIG_FB_3DFX_I2C 1710 fb_destroy_modelist(&info->modelist); 1711 tdfxfb_delete_i2c_busses(default_par); 1712 #endif 1713 arch_phys_wc_del(default_par->wc_cookie); 1714 release_region(pci_resource_start(pdev, 2), 1715 pci_resource_len(pdev, 2)); 1716 out_err_screenbase: 1717 if (info->screen_base) 1718 iounmap(info->screen_base); 1719 release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1)); 1720 out_err_regbase: 1721 /* 1722 * Cleanup after anything that was remapped/allocated. 1723 */ 1724 if (default_par->regbase_virt) 1725 iounmap(default_par->regbase_virt); 1726 release_mem_region(info->fix.mmio_start, info->fix.mmio_len); 1727 out_err: 1728 framebuffer_release(info); 1729 return -ENXIO; 1730 } 1731 1732 #ifndef MODULE 1733 static void __init tdfxfb_setup(char *options) 1734 { 1735 char *this_opt; 1736 1737 if (!options || !*options) 1738 return; 1739 1740 while ((this_opt = strsep(&options, ",")) != NULL) { 1741 if (!*this_opt) 1742 continue; 1743 if (!strcmp(this_opt, "nopan")) { 1744 nopan = 1; 1745 } else if (!strcmp(this_opt, "nowrap")) { 1746 nowrap = 1; 1747 } else if (!strncmp(this_opt, "hwcursor=", 9)) { 1748 hwcursor = simple_strtoul(this_opt + 9, NULL, 0); 1749 } else if (!strncmp(this_opt, "nomtrr", 6)) { 1750 nomtrr = 1; 1751 } else { 1752 mode_option = this_opt; 1753 } 1754 } 1755 } 1756 #endif 1757 1758 /** 1759 * tdfxfb_remove - Device removal 1760 * 1761 * @pdev: PCI Device to cleanup 1762 * 1763 * Releases all resources allocated during the course of the driver's 1764 * lifetime for the PCI device @pdev. 1765 * 1766 */ 1767 static void tdfxfb_remove(struct pci_dev *pdev) 1768 { 1769 struct fb_info *info = pci_get_drvdata(pdev); 1770 struct tdfx_par *par = info->par; 1771 1772 unregister_framebuffer(info); 1773 #ifdef CONFIG_FB_3DFX_I2C 1774 tdfxfb_delete_i2c_busses(par); 1775 #endif 1776 arch_phys_wc_del(par->wc_cookie); 1777 iounmap(par->regbase_virt); 1778 iounmap(info->screen_base); 1779 1780 /* Clean up after reserved regions */ 1781 release_region(pci_resource_start(pdev, 2), 1782 pci_resource_len(pdev, 2)); 1783 release_mem_region(pci_resource_start(pdev, 1), 1784 pci_resource_len(pdev, 1)); 1785 release_mem_region(pci_resource_start(pdev, 0), 1786 pci_resource_len(pdev, 0)); 1787 fb_dealloc_cmap(&info->cmap); 1788 framebuffer_release(info); 1789 } 1790 1791 static int __init tdfxfb_init(void) 1792 { 1793 #ifndef MODULE 1794 char *option = NULL; 1795 #endif 1796 1797 if (fb_modesetting_disabled("tdfxfb")) 1798 return -ENODEV; 1799 1800 #ifndef MODULE 1801 if (fb_get_options("tdfxfb", &option)) 1802 return -ENODEV; 1803 1804 tdfxfb_setup(option); 1805 #endif 1806 return pci_register_driver(&tdfxfb_driver); 1807 } 1808 1809 static void __exit tdfxfb_exit(void) 1810 { 1811 pci_unregister_driver(&tdfxfb_driver); 1812 } 1813 1814 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>"); 1815 MODULE_DESCRIPTION("3Dfx framebuffer device driver"); 1816 MODULE_LICENSE("GPL"); 1817 1818 module_param(hwcursor, int, 0644); 1819 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " 1820 "(1=enable, 0=disable, default=1)"); 1821 module_param(mode_option, charp, 0); 1822 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); 1823 module_param(nomtrr, bool, 0); 1824 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)"); 1825 1826 module_init(tdfxfb_init); 1827 module_exit(tdfxfb_exit); 1828