1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * smscufx.c -- Framebuffer driver for SMSC UFX USB controller 4 * 5 * Copyright (C) 2011 Steve Glendinning <steve.glendinning@shawell.net> 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 * 10 * Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen, 11 * and others. 12 * 13 * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev 14 * available from http://git.plugable.com 15 * 16 * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven, 17 * usb-skeleton by GregKH. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/usb.h> 26 #include <linux/uaccess.h> 27 #include <linux/mm.h> 28 #include <linux/fb.h> 29 #include <linux/vmalloc.h> 30 #include <linux/slab.h> 31 #include <linux/delay.h> 32 #include "edid.h" 33 34 #define check_warn(status, fmt, args...) \ 35 ({ if (status < 0) pr_warn(fmt, ##args); }) 36 37 #define check_warn_return(status, fmt, args...) \ 38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } }) 39 40 #define check_warn_goto_error(status, fmt, args...) \ 41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } }) 42 43 #define all_bits_set(x, bits) (((x) & (bits)) == (bits)) 44 45 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 46 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 47 48 /* 49 * TODO: Propose standard fb.h ioctl for reporting damage, 50 * using _IOWR() and one of the existing area structs from fb.h 51 * Consider these ioctls deprecated, but they're still used by the 52 * DisplayLink X server as yet - need both to be modified in tandem 53 * when new ioctl(s) are ready. 54 */ 55 #define UFX_IOCTL_RETURN_EDID (0xAD) 56 #define UFX_IOCTL_REPORT_DAMAGE (0xAA) 57 58 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */ 59 #define BULK_SIZE (512) 60 #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE) 61 #define WRITES_IN_FLIGHT (4) 62 63 #define GET_URB_TIMEOUT (HZ) 64 #define FREE_URB_TIMEOUT (HZ*2) 65 66 #define BPP 2 67 68 #define UFX_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */ 69 #define UFX_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */ 70 71 struct dloarea { 72 int x, y; 73 int w, h; 74 }; 75 76 struct urb_node { 77 struct list_head entry; 78 struct ufx_data *dev; 79 struct delayed_work release_urb_work; 80 struct urb *urb; 81 }; 82 83 struct urb_list { 84 struct list_head list; 85 spinlock_t lock; 86 struct semaphore limit_sem; 87 int available; 88 int count; 89 size_t size; 90 }; 91 92 struct ufx_data { 93 struct usb_device *udev; 94 struct device *gdev; /* &udev->dev */ 95 struct fb_info *info; 96 struct urb_list urbs; 97 struct kref kref; 98 int fb_count; 99 bool virtualized; /* true when physical usb device not present */ 100 struct delayed_work free_framebuffer_work; 101 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ 102 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ 103 u8 *edid; /* null until we read edid from hw or get from sysfs */ 104 size_t edid_size; 105 u32 pseudo_palette[256]; 106 }; 107 108 static struct fb_fix_screeninfo ufx_fix = { 109 .id = "smscufx", 110 .type = FB_TYPE_PACKED_PIXELS, 111 .visual = FB_VISUAL_TRUECOLOR, 112 .xpanstep = 0, 113 .ypanstep = 0, 114 .ywrapstep = 0, 115 .accel = FB_ACCEL_NONE, 116 }; 117 118 static const u32 smscufx_info_flags = FBINFO_DEFAULT | FBINFO_READS_FAST | 119 FBINFO_VIRTFB | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT | 120 FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR; 121 122 static const struct usb_device_id id_table[] = { 123 {USB_DEVICE(0x0424, 0x9d00),}, 124 {USB_DEVICE(0x0424, 0x9d01),}, 125 {}, 126 }; 127 MODULE_DEVICE_TABLE(usb, id_table); 128 129 /* module options */ 130 static bool console; /* Optionally allow fbcon to consume first framebuffer */ 131 static bool fb_defio = true; /* Optionally enable fb_defio mmap support */ 132 133 /* ufx keeps a list of urbs for efficient bulk transfers */ 134 static void ufx_urb_completion(struct urb *urb); 135 static struct urb *ufx_get_urb(struct ufx_data *dev); 136 static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len); 137 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size); 138 static void ufx_free_urb_list(struct ufx_data *dev); 139 140 static DEFINE_MUTEX(disconnect_mutex); 141 142 /* reads a control register */ 143 static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data) 144 { 145 u32 *buf = kmalloc(4, GFP_KERNEL); 146 int ret; 147 148 BUG_ON(!dev); 149 150 if (!buf) 151 return -ENOMEM; 152 153 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), 154 USB_VENDOR_REQUEST_READ_REGISTER, 155 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 156 00, index, buf, 4, USB_CTRL_GET_TIMEOUT); 157 158 le32_to_cpus(buf); 159 *data = *buf; 160 kfree(buf); 161 162 if (unlikely(ret < 0)) 163 pr_warn("Failed to read register index 0x%08x\n", index); 164 165 return ret; 166 } 167 168 /* writes a control register */ 169 static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data) 170 { 171 u32 *buf = kmalloc(4, GFP_KERNEL); 172 int ret; 173 174 BUG_ON(!dev); 175 176 if (!buf) 177 return -ENOMEM; 178 179 *buf = data; 180 cpu_to_le32s(buf); 181 182 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), 183 USB_VENDOR_REQUEST_WRITE_REGISTER, 184 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 185 00, index, buf, 4, USB_CTRL_SET_TIMEOUT); 186 187 kfree(buf); 188 189 if (unlikely(ret < 0)) 190 pr_warn("Failed to write register index 0x%08x with value " 191 "0x%08x\n", index, data); 192 193 return ret; 194 } 195 196 static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index, 197 u32 bits_to_clear, u32 bits_to_set) 198 { 199 u32 data; 200 int status = ufx_reg_read(dev, index, &data); 201 check_warn_return(status, "ufx_reg_clear_and_set_bits error reading " 202 "0x%x", index); 203 204 data &= (~bits_to_clear); 205 data |= bits_to_set; 206 207 status = ufx_reg_write(dev, index, data); 208 check_warn_return(status, "ufx_reg_clear_and_set_bits error writing " 209 "0x%x", index); 210 211 return 0; 212 } 213 214 static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits) 215 { 216 return ufx_reg_clear_and_set_bits(dev, index, 0, bits); 217 } 218 219 static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits) 220 { 221 return ufx_reg_clear_and_set_bits(dev, index, bits, 0); 222 } 223 224 static int ufx_lite_reset(struct ufx_data *dev) 225 { 226 int status; 227 u32 value; 228 229 status = ufx_reg_write(dev, 0x3008, 0x00000001); 230 check_warn_return(status, "ufx_lite_reset error writing 0x3008"); 231 232 status = ufx_reg_read(dev, 0x3008, &value); 233 check_warn_return(status, "ufx_lite_reset error reading 0x3008"); 234 235 return (value == 0) ? 0 : -EIO; 236 } 237 238 /* If display is unblanked, then blank it */ 239 static int ufx_blank(struct ufx_data *dev, bool wait) 240 { 241 u32 dc_ctrl, dc_sts; 242 int i; 243 244 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 245 check_warn_return(status, "ufx_blank error reading 0x2004"); 246 247 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 248 check_warn_return(status, "ufx_blank error reading 0x2000"); 249 250 /* return success if display is already blanked */ 251 if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100)) 252 return 0; 253 254 /* request the DC to blank the display */ 255 dc_ctrl |= 0x00000100; 256 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 257 check_warn_return(status, "ufx_blank error writing 0x2000"); 258 259 /* return success immediately if we don't have to wait */ 260 if (!wait) 261 return 0; 262 263 for (i = 0; i < 250; i++) { 264 status = ufx_reg_read(dev, 0x2004, &dc_sts); 265 check_warn_return(status, "ufx_blank error reading 0x2004"); 266 267 if (dc_sts & 0x00000100) 268 return 0; 269 } 270 271 /* timed out waiting for display to blank */ 272 return -EIO; 273 } 274 275 /* If display is blanked, then unblank it */ 276 static int ufx_unblank(struct ufx_data *dev, bool wait) 277 { 278 u32 dc_ctrl, dc_sts; 279 int i; 280 281 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 282 check_warn_return(status, "ufx_unblank error reading 0x2004"); 283 284 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 285 check_warn_return(status, "ufx_unblank error reading 0x2000"); 286 287 /* return success if display is already unblanked */ 288 if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0)) 289 return 0; 290 291 /* request the DC to unblank the display */ 292 dc_ctrl &= ~0x00000100; 293 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 294 check_warn_return(status, "ufx_unblank error writing 0x2000"); 295 296 /* return success immediately if we don't have to wait */ 297 if (!wait) 298 return 0; 299 300 for (i = 0; i < 250; i++) { 301 status = ufx_reg_read(dev, 0x2004, &dc_sts); 302 check_warn_return(status, "ufx_unblank error reading 0x2004"); 303 304 if ((dc_sts & 0x00000100) == 0) 305 return 0; 306 } 307 308 /* timed out waiting for display to unblank */ 309 return -EIO; 310 } 311 312 /* If display is enabled, then disable it */ 313 static int ufx_disable(struct ufx_data *dev, bool wait) 314 { 315 u32 dc_ctrl, dc_sts; 316 int i; 317 318 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 319 check_warn_return(status, "ufx_disable error reading 0x2004"); 320 321 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 322 check_warn_return(status, "ufx_disable error reading 0x2000"); 323 324 /* return success if display is already disabled */ 325 if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0)) 326 return 0; 327 328 /* request the DC to disable the display */ 329 dc_ctrl &= ~(0x00000001); 330 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 331 check_warn_return(status, "ufx_disable error writing 0x2000"); 332 333 /* return success immediately if we don't have to wait */ 334 if (!wait) 335 return 0; 336 337 for (i = 0; i < 250; i++) { 338 status = ufx_reg_read(dev, 0x2004, &dc_sts); 339 check_warn_return(status, "ufx_disable error reading 0x2004"); 340 341 if ((dc_sts & 0x00000001) == 0) 342 return 0; 343 } 344 345 /* timed out waiting for display to disable */ 346 return -EIO; 347 } 348 349 /* If display is disabled, then enable it */ 350 static int ufx_enable(struct ufx_data *dev, bool wait) 351 { 352 u32 dc_ctrl, dc_sts; 353 int i; 354 355 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 356 check_warn_return(status, "ufx_enable error reading 0x2004"); 357 358 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 359 check_warn_return(status, "ufx_enable error reading 0x2000"); 360 361 /* return success if display is already enabled */ 362 if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001)) 363 return 0; 364 365 /* request the DC to enable the display */ 366 dc_ctrl |= 0x00000001; 367 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 368 check_warn_return(status, "ufx_enable error writing 0x2000"); 369 370 /* return success immediately if we don't have to wait */ 371 if (!wait) 372 return 0; 373 374 for (i = 0; i < 250; i++) { 375 status = ufx_reg_read(dev, 0x2004, &dc_sts); 376 check_warn_return(status, "ufx_enable error reading 0x2004"); 377 378 if (dc_sts & 0x00000001) 379 return 0; 380 } 381 382 /* timed out waiting for display to enable */ 383 return -EIO; 384 } 385 386 static int ufx_config_sys_clk(struct ufx_data *dev) 387 { 388 int status = ufx_reg_write(dev, 0x700C, 0x8000000F); 389 check_warn_return(status, "error writing 0x700C"); 390 391 status = ufx_reg_write(dev, 0x7014, 0x0010024F); 392 check_warn_return(status, "error writing 0x7014"); 393 394 status = ufx_reg_write(dev, 0x7010, 0x00000000); 395 check_warn_return(status, "error writing 0x7010"); 396 397 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A); 398 check_warn_return(status, "error clearing PLL1 bypass in 0x700C"); 399 msleep(1); 400 401 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000); 402 check_warn_return(status, "error clearing output gate in 0x700C"); 403 404 return 0; 405 } 406 407 static int ufx_config_ddr2(struct ufx_data *dev) 408 { 409 int status, i = 0; 410 u32 tmp; 411 412 status = ufx_reg_write(dev, 0x0004, 0x001F0F77); 413 check_warn_return(status, "error writing 0x0004"); 414 415 status = ufx_reg_write(dev, 0x0008, 0xFFF00000); 416 check_warn_return(status, "error writing 0x0008"); 417 418 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222); 419 check_warn_return(status, "error writing 0x000C"); 420 421 status = ufx_reg_write(dev, 0x0010, 0x00030814); 422 check_warn_return(status, "error writing 0x0010"); 423 424 status = ufx_reg_write(dev, 0x0014, 0x00500019); 425 check_warn_return(status, "error writing 0x0014"); 426 427 status = ufx_reg_write(dev, 0x0018, 0x020D0F15); 428 check_warn_return(status, "error writing 0x0018"); 429 430 status = ufx_reg_write(dev, 0x001C, 0x02532305); 431 check_warn_return(status, "error writing 0x001C"); 432 433 status = ufx_reg_write(dev, 0x0020, 0x0B030905); 434 check_warn_return(status, "error writing 0x0020"); 435 436 status = ufx_reg_write(dev, 0x0024, 0x00000827); 437 check_warn_return(status, "error writing 0x0024"); 438 439 status = ufx_reg_write(dev, 0x0028, 0x00000000); 440 check_warn_return(status, "error writing 0x0028"); 441 442 status = ufx_reg_write(dev, 0x002C, 0x00000042); 443 check_warn_return(status, "error writing 0x002C"); 444 445 status = ufx_reg_write(dev, 0x0030, 0x09520000); 446 check_warn_return(status, "error writing 0x0030"); 447 448 status = ufx_reg_write(dev, 0x0034, 0x02223314); 449 check_warn_return(status, "error writing 0x0034"); 450 451 status = ufx_reg_write(dev, 0x0038, 0x00430043); 452 check_warn_return(status, "error writing 0x0038"); 453 454 status = ufx_reg_write(dev, 0x003C, 0xF00F000F); 455 check_warn_return(status, "error writing 0x003C"); 456 457 status = ufx_reg_write(dev, 0x0040, 0xF380F00F); 458 check_warn_return(status, "error writing 0x0040"); 459 460 status = ufx_reg_write(dev, 0x0044, 0xF00F0496); 461 check_warn_return(status, "error writing 0x0044"); 462 463 status = ufx_reg_write(dev, 0x0048, 0x03080406); 464 check_warn_return(status, "error writing 0x0048"); 465 466 status = ufx_reg_write(dev, 0x004C, 0x00001000); 467 check_warn_return(status, "error writing 0x004C"); 468 469 status = ufx_reg_write(dev, 0x005C, 0x00000007); 470 check_warn_return(status, "error writing 0x005C"); 471 472 status = ufx_reg_write(dev, 0x0100, 0x54F00012); 473 check_warn_return(status, "error writing 0x0100"); 474 475 status = ufx_reg_write(dev, 0x0104, 0x00004012); 476 check_warn_return(status, "error writing 0x0104"); 477 478 status = ufx_reg_write(dev, 0x0118, 0x40404040); 479 check_warn_return(status, "error writing 0x0118"); 480 481 status = ufx_reg_write(dev, 0x0000, 0x00000001); 482 check_warn_return(status, "error writing 0x0000"); 483 484 while (i++ < 500) { 485 status = ufx_reg_read(dev, 0x0000, &tmp); 486 check_warn_return(status, "error reading 0x0000"); 487 488 if (all_bits_set(tmp, 0xC0000000)) 489 return 0; 490 } 491 492 pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp); 493 return -ETIMEDOUT; 494 } 495 496 struct pll_values { 497 u32 div_r0; 498 u32 div_f0; 499 u32 div_q0; 500 u32 range0; 501 u32 div_r1; 502 u32 div_f1; 503 u32 div_q1; 504 u32 range1; 505 }; 506 507 static u32 ufx_calc_range(u32 ref_freq) 508 { 509 if (ref_freq >= 88000000) 510 return 7; 511 512 if (ref_freq >= 54000000) 513 return 6; 514 515 if (ref_freq >= 34000000) 516 return 5; 517 518 if (ref_freq >= 21000000) 519 return 4; 520 521 if (ref_freq >= 13000000) 522 return 3; 523 524 if (ref_freq >= 8000000) 525 return 2; 526 527 return 1; 528 } 529 530 /* calculates PLL divider settings for a desired target frequency */ 531 static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll) 532 { 533 const u32 ref_clk = 25000000; 534 u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1; 535 u32 min_error = clk_pixel_pll; 536 537 for (div_r0 = 1; div_r0 <= 32; div_r0++) { 538 u32 ref_freq0 = ref_clk / div_r0; 539 if (ref_freq0 < 5000000) 540 break; 541 542 if (ref_freq0 > 200000000) 543 continue; 544 545 for (div_f0 = 1; div_f0 <= 256; div_f0++) { 546 u32 vco_freq0 = ref_freq0 * div_f0; 547 548 if (vco_freq0 < 350000000) 549 continue; 550 551 if (vco_freq0 > 700000000) 552 break; 553 554 for (div_q0 = 0; div_q0 < 7; div_q0++) { 555 u32 pllout_freq0 = vco_freq0 / (1 << div_q0); 556 557 if (pllout_freq0 < 5000000) 558 break; 559 560 if (pllout_freq0 > 200000000) 561 continue; 562 563 for (div_r1 = 1; div_r1 <= 32; div_r1++) { 564 u32 ref_freq1 = pllout_freq0 / div_r1; 565 566 if (ref_freq1 < 5000000) 567 break; 568 569 for (div_f1 = 1; div_f1 <= 256; div_f1++) { 570 u32 vco_freq1 = ref_freq1 * div_f1; 571 572 if (vco_freq1 < 350000000) 573 continue; 574 575 if (vco_freq1 > 700000000) 576 break; 577 578 for (div_q1 = 0; div_q1 < 7; div_q1++) { 579 u32 pllout_freq1 = vco_freq1 / (1 << div_q1); 580 int error = abs(pllout_freq1 - clk_pixel_pll); 581 582 if (pllout_freq1 < 5000000) 583 break; 584 585 if (pllout_freq1 > 700000000) 586 continue; 587 588 if (error < min_error) { 589 min_error = error; 590 591 /* final returned value is equal to calculated value - 1 592 * because a value of 0 = divide by 1 */ 593 asic_pll->div_r0 = div_r0 - 1; 594 asic_pll->div_f0 = div_f0 - 1; 595 asic_pll->div_q0 = div_q0; 596 asic_pll->div_r1 = div_r1 - 1; 597 asic_pll->div_f1 = div_f1 - 1; 598 asic_pll->div_q1 = div_q1; 599 600 asic_pll->range0 = ufx_calc_range(ref_freq0); 601 asic_pll->range1 = ufx_calc_range(ref_freq1); 602 603 if (min_error == 0) 604 return; 605 } 606 } 607 } 608 } 609 } 610 } 611 } 612 } 613 614 /* sets analog bit PLL configuration values */ 615 static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock) 616 { 617 struct pll_values asic_pll = {0}; 618 u32 value, clk_pixel, clk_pixel_pll; 619 int status; 620 621 /* convert pixclock (in ps) to frequency (in Hz) */ 622 clk_pixel = PICOS2KHZ(pixclock) * 1000; 623 pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel); 624 625 /* clk_pixel = 1/2 clk_pixel_pll */ 626 clk_pixel_pll = clk_pixel * 2; 627 628 ufx_calc_pll_values(clk_pixel_pll, &asic_pll); 629 630 /* Keep BYPASS and RESET signals asserted until configured */ 631 status = ufx_reg_write(dev, 0x7000, 0x8000000F); 632 check_warn_return(status, "error writing 0x7000"); 633 634 value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) | 635 (asic_pll.div_q1 << 16) | (asic_pll.range1 << 20)); 636 status = ufx_reg_write(dev, 0x7008, value); 637 check_warn_return(status, "error writing 0x7008"); 638 639 value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) | 640 (asic_pll.div_q0 << 16) | (asic_pll.range0 << 20)); 641 status = ufx_reg_write(dev, 0x7004, value); 642 check_warn_return(status, "error writing 0x7004"); 643 644 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005); 645 check_warn_return(status, 646 "error clearing PLL0 bypass bits in 0x7000"); 647 msleep(1); 648 649 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A); 650 check_warn_return(status, 651 "error clearing PLL1 bypass bits in 0x7000"); 652 msleep(1); 653 654 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000); 655 check_warn_return(status, "error clearing gate bits in 0x7000"); 656 657 return 0; 658 } 659 660 static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var) 661 { 662 u32 temp; 663 u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end; 664 u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end; 665 666 int status = ufx_reg_write(dev, 0x8028, 0); 667 check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad"); 668 669 status = ufx_reg_write(dev, 0x8024, 0); 670 check_warn_return(status, "ufx_set_vid_mode error disabling VDAC"); 671 672 /* shut everything down before changing timing */ 673 status = ufx_blank(dev, true); 674 check_warn_return(status, "ufx_set_vid_mode error blanking display"); 675 676 status = ufx_disable(dev, true); 677 check_warn_return(status, "ufx_set_vid_mode error disabling display"); 678 679 status = ufx_config_pix_clk(dev, var->pixclock); 680 check_warn_return(status, "ufx_set_vid_mode error configuring pixclock"); 681 682 status = ufx_reg_write(dev, 0x2000, 0x00000104); 683 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000"); 684 685 /* set horizontal timings */ 686 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin; 687 h_active = var->xres; 688 h_blank_start = var->xres + var->right_margin; 689 h_blank_end = var->xres + var->right_margin + var->hsync_len; 690 h_sync_start = var->xres + var->right_margin; 691 h_sync_end = var->xres + var->right_margin + var->hsync_len; 692 693 temp = ((h_total - 1) << 16) | (h_active - 1); 694 status = ufx_reg_write(dev, 0x2008, temp); 695 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008"); 696 697 temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1); 698 status = ufx_reg_write(dev, 0x200C, temp); 699 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C"); 700 701 temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1); 702 status = ufx_reg_write(dev, 0x2010, temp); 703 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010"); 704 705 /* set vertical timings */ 706 v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; 707 v_active = var->yres; 708 v_blank_start = var->yres + var->lower_margin; 709 v_blank_end = var->yres + var->lower_margin + var->vsync_len; 710 v_sync_start = var->yres + var->lower_margin; 711 v_sync_end = var->yres + var->lower_margin + var->vsync_len; 712 713 temp = ((v_total - 1) << 16) | (v_active - 1); 714 status = ufx_reg_write(dev, 0x2014, temp); 715 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014"); 716 717 temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1); 718 status = ufx_reg_write(dev, 0x2018, temp); 719 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018"); 720 721 temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1); 722 status = ufx_reg_write(dev, 0x201C, temp); 723 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C"); 724 725 status = ufx_reg_write(dev, 0x2020, 0x00000000); 726 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020"); 727 728 status = ufx_reg_write(dev, 0x2024, 0x00000000); 729 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024"); 730 731 /* Set the frame length register (#pix * 2 bytes/pixel) */ 732 temp = var->xres * var->yres * 2; 733 temp = (temp + 7) & (~0x7); 734 status = ufx_reg_write(dev, 0x2028, temp); 735 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028"); 736 737 /* enable desired output interface & disable others */ 738 status = ufx_reg_write(dev, 0x2040, 0); 739 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); 740 741 status = ufx_reg_write(dev, 0x2044, 0); 742 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044"); 743 744 status = ufx_reg_write(dev, 0x2048, 0); 745 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048"); 746 747 /* set the sync polarities & enable bit */ 748 temp = 0x00000001; 749 if (var->sync & FB_SYNC_HOR_HIGH_ACT) 750 temp |= 0x00000010; 751 752 if (var->sync & FB_SYNC_VERT_HIGH_ACT) 753 temp |= 0x00000008; 754 755 status = ufx_reg_write(dev, 0x2040, temp); 756 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); 757 758 /* start everything back up */ 759 status = ufx_enable(dev, true); 760 check_warn_return(status, "ufx_set_vid_mode error enabling display"); 761 762 /* Unblank the display */ 763 status = ufx_unblank(dev, true); 764 check_warn_return(status, "ufx_set_vid_mode error unblanking display"); 765 766 /* enable RGB pad */ 767 status = ufx_reg_write(dev, 0x8028, 0x00000003); 768 check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad"); 769 770 /* enable VDAC */ 771 status = ufx_reg_write(dev, 0x8024, 0x00000007); 772 check_warn_return(status, "ufx_set_vid_mode error enabling VDAC"); 773 774 return 0; 775 } 776 777 static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma) 778 { 779 unsigned long start = vma->vm_start; 780 unsigned long size = vma->vm_end - vma->vm_start; 781 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 782 unsigned long page, pos; 783 784 if (info->fbdefio) 785 return fb_deferred_io_mmap(info, vma); 786 787 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) 788 return -EINVAL; 789 if (size > info->fix.smem_len) 790 return -EINVAL; 791 if (offset > info->fix.smem_len - size) 792 return -EINVAL; 793 794 pos = (unsigned long)info->fix.smem_start + offset; 795 796 pr_debug("mmap() framebuffer addr:%lu size:%lu\n", 797 pos, size); 798 799 while (size > 0) { 800 page = vmalloc_to_pfn((void *)pos); 801 if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED)) 802 return -EAGAIN; 803 804 start += PAGE_SIZE; 805 pos += PAGE_SIZE; 806 if (size > PAGE_SIZE) 807 size -= PAGE_SIZE; 808 else 809 size = 0; 810 } 811 812 return 0; 813 } 814 815 static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y, 816 int width, int height) 817 { 818 size_t packed_line_len = ALIGN((width * 2), 4); 819 size_t packed_rect_len = packed_line_len * height; 820 int line; 821 822 BUG_ON(!dev); 823 BUG_ON(!dev->info); 824 825 /* command word */ 826 *((u32 *)&cmd[0]) = cpu_to_le32(0x01); 827 828 /* length word */ 829 *((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16); 830 831 cmd[4] = cpu_to_le16(x); 832 cmd[5] = cpu_to_le16(y); 833 cmd[6] = cpu_to_le16(width); 834 cmd[7] = cpu_to_le16(height); 835 836 /* frame base address */ 837 *((u32 *)&cmd[8]) = cpu_to_le32(0); 838 839 /* color mode and horizontal resolution */ 840 cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres); 841 842 /* vertical resolution */ 843 cmd[11] = cpu_to_le16(dev->info->var.yres); 844 845 /* packed data */ 846 for (line = 0; line < height; line++) { 847 const int line_offset = dev->info->fix.line_length * (y + line); 848 const int byte_offset = line_offset + (x * BPP); 849 memcpy(&cmd[(24 + (packed_line_len * line)) / 2], 850 (char *)dev->info->fix.smem_start + byte_offset, width * BPP); 851 } 852 } 853 854 static int ufx_handle_damage(struct ufx_data *dev, int x, int y, 855 int width, int height) 856 { 857 size_t packed_line_len = ALIGN((width * 2), 4); 858 int len, status, urb_lines, start_line = 0; 859 860 if ((width <= 0) || (height <= 0) || 861 (x + width > dev->info->var.xres) || 862 (y + height > dev->info->var.yres)) 863 return -EINVAL; 864 865 if (!atomic_read(&dev->usb_active)) 866 return 0; 867 868 while (start_line < height) { 869 struct urb *urb = ufx_get_urb(dev); 870 if (!urb) { 871 pr_warn("ufx_handle_damage unable to get urb"); 872 return 0; 873 } 874 875 /* assume we have enough space to transfer at least one line */ 876 BUG_ON(urb->transfer_buffer_length < (24 + (width * 2))); 877 878 /* calculate the maximum number of lines we could fit in */ 879 urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len; 880 881 /* but we might not need this many */ 882 urb_lines = min(urb_lines, (height - start_line)); 883 884 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length); 885 886 ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines); 887 len = 24 + (packed_line_len * urb_lines); 888 889 status = ufx_submit_urb(dev, urb, len); 890 check_warn_return(status, "Error submitting URB"); 891 892 start_line += urb_lines; 893 } 894 895 return 0; 896 } 897 898 /* Path triggered by usermode clients who write to filesystem 899 * e.g. cat filename > /dev/fb1 900 * Not used by X Windows or text-mode console. But useful for testing. 901 * Slow because of extra copy and we must assume all pixels dirty. */ 902 static ssize_t ufx_ops_write(struct fb_info *info, const char __user *buf, 903 size_t count, loff_t *ppos) 904 { 905 ssize_t result; 906 struct ufx_data *dev = info->par; 907 u32 offset = (u32) *ppos; 908 909 result = fb_sys_write(info, buf, count, ppos); 910 911 if (result > 0) { 912 int start = max((int)(offset / info->fix.line_length), 0); 913 int lines = min((u32)((result / info->fix.line_length) + 1), 914 (u32)info->var.yres); 915 916 ufx_handle_damage(dev, 0, start, info->var.xres, lines); 917 } 918 919 return result; 920 } 921 922 static void ufx_ops_copyarea(struct fb_info *info, 923 const struct fb_copyarea *area) 924 { 925 926 struct ufx_data *dev = info->par; 927 928 sys_copyarea(info, area); 929 930 ufx_handle_damage(dev, area->dx, area->dy, 931 area->width, area->height); 932 } 933 934 static void ufx_ops_imageblit(struct fb_info *info, 935 const struct fb_image *image) 936 { 937 struct ufx_data *dev = info->par; 938 939 sys_imageblit(info, image); 940 941 ufx_handle_damage(dev, image->dx, image->dy, 942 image->width, image->height); 943 } 944 945 static void ufx_ops_fillrect(struct fb_info *info, 946 const struct fb_fillrect *rect) 947 { 948 struct ufx_data *dev = info->par; 949 950 sys_fillrect(info, rect); 951 952 ufx_handle_damage(dev, rect->dx, rect->dy, rect->width, 953 rect->height); 954 } 955 956 /* NOTE: fb_defio.c is holding info->fbdefio.mutex 957 * Touching ANY framebuffer memory that triggers a page fault 958 * in fb_defio will cause a deadlock, when it also tries to 959 * grab the same mutex. */ 960 static void ufx_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist) 961 { 962 struct ufx_data *dev = info->par; 963 struct fb_deferred_io_pageref *pageref; 964 965 if (!fb_defio) 966 return; 967 968 if (!atomic_read(&dev->usb_active)) 969 return; 970 971 /* walk the written page list and render each to device */ 972 list_for_each_entry(pageref, pagereflist, list) { 973 /* create a rectangle of full screen width that encloses the 974 * entire dirty framebuffer page */ 975 const int x = 0; 976 const int width = dev->info->var.xres; 977 const int y = pageref->offset / (width * 2); 978 int height = (PAGE_SIZE / (width * 2)) + 1; 979 height = min(height, (int)(dev->info->var.yres - y)); 980 981 BUG_ON(y >= dev->info->var.yres); 982 BUG_ON((y + height) > dev->info->var.yres); 983 984 ufx_handle_damage(dev, x, y, width, height); 985 } 986 } 987 988 static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd, 989 unsigned long arg) 990 { 991 struct ufx_data *dev = info->par; 992 struct dloarea *area = NULL; 993 994 if (!atomic_read(&dev->usb_active)) 995 return 0; 996 997 /* TODO: Update X server to get this from sysfs instead */ 998 if (cmd == UFX_IOCTL_RETURN_EDID) { 999 u8 __user *edid = (u8 __user *)arg; 1000 if (copy_to_user(edid, dev->edid, dev->edid_size)) 1001 return -EFAULT; 1002 return 0; 1003 } 1004 1005 /* TODO: Help propose a standard fb.h ioctl to report mmap damage */ 1006 if (cmd == UFX_IOCTL_REPORT_DAMAGE) { 1007 /* If we have a damage-aware client, turn fb_defio "off" 1008 * To avoid perf imact of unnecessary page fault handling. 1009 * Done by resetting the delay for this fb_info to a very 1010 * long period. Pages will become writable and stay that way. 1011 * Reset to normal value when all clients have closed this fb. 1012 */ 1013 if (info->fbdefio) 1014 info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE; 1015 1016 area = (struct dloarea *)arg; 1017 1018 if (area->x < 0) 1019 area->x = 0; 1020 1021 if (area->x > info->var.xres) 1022 area->x = info->var.xres; 1023 1024 if (area->y < 0) 1025 area->y = 0; 1026 1027 if (area->y > info->var.yres) 1028 area->y = info->var.yres; 1029 1030 ufx_handle_damage(dev, area->x, area->y, area->w, area->h); 1031 } 1032 1033 return 0; 1034 } 1035 1036 /* taken from vesafb */ 1037 static int 1038 ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green, 1039 unsigned blue, unsigned transp, struct fb_info *info) 1040 { 1041 int err = 0; 1042 1043 if (regno >= info->cmap.len) 1044 return 1; 1045 1046 if (regno < 16) { 1047 if (info->var.red.offset == 10) { 1048 /* 1:5:5:5 */ 1049 ((u32 *) (info->pseudo_palette))[regno] = 1050 ((red & 0xf800) >> 1) | 1051 ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); 1052 } else { 1053 /* 0:5:6:5 */ 1054 ((u32 *) (info->pseudo_palette))[regno] = 1055 ((red & 0xf800)) | 1056 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); 1057 } 1058 } 1059 1060 return err; 1061 } 1062 1063 /* It's common for several clients to have framebuffer open simultaneously. 1064 * e.g. both fbcon and X. Makes things interesting. 1065 * Assumes caller is holding info->lock (for open and release at least) */ 1066 static int ufx_ops_open(struct fb_info *info, int user) 1067 { 1068 struct ufx_data *dev = info->par; 1069 1070 /* fbcon aggressively connects to first framebuffer it finds, 1071 * preventing other clients (X) from working properly. Usually 1072 * not what the user wants. Fail by default with option to enable. */ 1073 if (user == 0 && !console) 1074 return -EBUSY; 1075 1076 mutex_lock(&disconnect_mutex); 1077 1078 /* If the USB device is gone, we don't accept new opens */ 1079 if (dev->virtualized) { 1080 mutex_unlock(&disconnect_mutex); 1081 return -ENODEV; 1082 } 1083 1084 dev->fb_count++; 1085 1086 kref_get(&dev->kref); 1087 1088 if (fb_defio && (info->fbdefio == NULL)) { 1089 /* enable defio at last moment if not disabled by client */ 1090 1091 struct fb_deferred_io *fbdefio; 1092 1093 fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL); 1094 if (fbdefio) { 1095 fbdefio->delay = UFX_DEFIO_WRITE_DELAY; 1096 fbdefio->deferred_io = ufx_dpy_deferred_io; 1097 } 1098 1099 info->fbdefio = fbdefio; 1100 fb_deferred_io_init(info); 1101 } 1102 1103 pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d", 1104 info->node, user, info, dev->fb_count); 1105 1106 mutex_unlock(&disconnect_mutex); 1107 1108 return 0; 1109 } 1110 1111 /* 1112 * Called when all client interfaces to start transactions have been disabled, 1113 * and all references to our device instance (ufx_data) are released. 1114 * Every transaction must have a reference, so we know are fully spun down 1115 */ 1116 static void ufx_free(struct kref *kref) 1117 { 1118 struct ufx_data *dev = container_of(kref, struct ufx_data, kref); 1119 1120 /* this function will wait for all in-flight urbs to complete */ 1121 if (dev->urbs.count > 0) 1122 ufx_free_urb_list(dev); 1123 1124 pr_debug("freeing ufx_data %p", dev); 1125 1126 kfree(dev); 1127 } 1128 1129 static void ufx_release_urb_work(struct work_struct *work) 1130 { 1131 struct urb_node *unode = container_of(work, struct urb_node, 1132 release_urb_work.work); 1133 1134 up(&unode->dev->urbs.limit_sem); 1135 } 1136 1137 static void ufx_free_framebuffer_work(struct work_struct *work) 1138 { 1139 struct ufx_data *dev = container_of(work, struct ufx_data, 1140 free_framebuffer_work.work); 1141 struct fb_info *info = dev->info; 1142 int node = info->node; 1143 1144 unregister_framebuffer(info); 1145 1146 if (info->cmap.len != 0) 1147 fb_dealloc_cmap(&info->cmap); 1148 if (info->monspecs.modedb) 1149 fb_destroy_modedb(info->monspecs.modedb); 1150 vfree(info->screen_base); 1151 1152 fb_destroy_modelist(&info->modelist); 1153 1154 dev->info = NULL; 1155 1156 /* Assume info structure is freed after this point */ 1157 framebuffer_release(info); 1158 1159 pr_debug("fb_info for /dev/fb%d has been freed", node); 1160 1161 /* ref taken in probe() as part of registering framebfufer */ 1162 kref_put(&dev->kref, ufx_free); 1163 } 1164 1165 /* 1166 * Assumes caller is holding info->lock mutex (for open and release at least) 1167 */ 1168 static int ufx_ops_release(struct fb_info *info, int user) 1169 { 1170 struct ufx_data *dev = info->par; 1171 1172 dev->fb_count--; 1173 1174 /* We can't free fb_info here - fbmem will touch it when we return */ 1175 if (dev->virtualized && (dev->fb_count == 0)) 1176 schedule_delayed_work(&dev->free_framebuffer_work, HZ); 1177 1178 if ((dev->fb_count == 0) && (info->fbdefio)) { 1179 fb_deferred_io_cleanup(info); 1180 kfree(info->fbdefio); 1181 info->fbdefio = NULL; 1182 } 1183 1184 pr_debug("released /dev/fb%d user=%d count=%d", 1185 info->node, user, dev->fb_count); 1186 1187 kref_put(&dev->kref, ufx_free); 1188 1189 return 0; 1190 } 1191 1192 /* Check whether a video mode is supported by the chip 1193 * We start from monitor's modes, so don't need to filter that here */ 1194 static int ufx_is_valid_mode(struct fb_videomode *mode, 1195 struct fb_info *info) 1196 { 1197 if ((mode->xres * mode->yres) > (2048 * 1152)) { 1198 pr_debug("%dx%d too many pixels", 1199 mode->xres, mode->yres); 1200 return 0; 1201 } 1202 1203 if (mode->pixclock < 5000) { 1204 pr_debug("%dx%d %dps pixel clock too fast", 1205 mode->xres, mode->yres, mode->pixclock); 1206 return 0; 1207 } 1208 1209 pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres, 1210 mode->pixclock, (1000000 / mode->pixclock)); 1211 return 1; 1212 } 1213 1214 static void ufx_var_color_format(struct fb_var_screeninfo *var) 1215 { 1216 const struct fb_bitfield red = { 11, 5, 0 }; 1217 const struct fb_bitfield green = { 5, 6, 0 }; 1218 const struct fb_bitfield blue = { 0, 5, 0 }; 1219 1220 var->bits_per_pixel = 16; 1221 var->red = red; 1222 var->green = green; 1223 var->blue = blue; 1224 } 1225 1226 static int ufx_ops_check_var(struct fb_var_screeninfo *var, 1227 struct fb_info *info) 1228 { 1229 struct fb_videomode mode; 1230 1231 /* TODO: support dynamically changing framebuffer size */ 1232 if ((var->xres * var->yres * 2) > info->fix.smem_len) 1233 return -EINVAL; 1234 1235 /* set device-specific elements of var unrelated to mode */ 1236 ufx_var_color_format(var); 1237 1238 fb_var_to_videomode(&mode, var); 1239 1240 if (!ufx_is_valid_mode(&mode, info)) 1241 return -EINVAL; 1242 1243 return 0; 1244 } 1245 1246 static int ufx_ops_set_par(struct fb_info *info) 1247 { 1248 struct ufx_data *dev = info->par; 1249 int result; 1250 u16 *pix_framebuffer; 1251 int i; 1252 1253 pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres); 1254 result = ufx_set_vid_mode(dev, &info->var); 1255 1256 if ((result == 0) && (dev->fb_count == 0)) { 1257 /* paint greenscreen */ 1258 pix_framebuffer = (u16 *) info->screen_base; 1259 for (i = 0; i < info->fix.smem_len / 2; i++) 1260 pix_framebuffer[i] = 0x37e6; 1261 1262 ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres); 1263 } 1264 1265 /* re-enable defio if previously disabled by damage tracking */ 1266 if (info->fbdefio) 1267 info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY; 1268 1269 return result; 1270 } 1271 1272 /* In order to come back from full DPMS off, we need to set the mode again */ 1273 static int ufx_ops_blank(int blank_mode, struct fb_info *info) 1274 { 1275 struct ufx_data *dev = info->par; 1276 ufx_set_vid_mode(dev, &info->var); 1277 return 0; 1278 } 1279 1280 static const struct fb_ops ufx_ops = { 1281 .owner = THIS_MODULE, 1282 .fb_read = fb_sys_read, 1283 .fb_write = ufx_ops_write, 1284 .fb_setcolreg = ufx_ops_setcolreg, 1285 .fb_fillrect = ufx_ops_fillrect, 1286 .fb_copyarea = ufx_ops_copyarea, 1287 .fb_imageblit = ufx_ops_imageblit, 1288 .fb_mmap = ufx_ops_mmap, 1289 .fb_ioctl = ufx_ops_ioctl, 1290 .fb_open = ufx_ops_open, 1291 .fb_release = ufx_ops_release, 1292 .fb_blank = ufx_ops_blank, 1293 .fb_check_var = ufx_ops_check_var, 1294 .fb_set_par = ufx_ops_set_par, 1295 }; 1296 1297 /* Assumes &info->lock held by caller 1298 * Assumes no active clients have framebuffer open */ 1299 static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info) 1300 { 1301 int old_len = info->fix.smem_len; 1302 int new_len; 1303 unsigned char *old_fb = info->screen_base; 1304 unsigned char *new_fb; 1305 1306 pr_debug("Reallocating framebuffer. Addresses will change!"); 1307 1308 new_len = info->fix.line_length * info->var.yres; 1309 1310 if (PAGE_ALIGN(new_len) > old_len) { 1311 /* 1312 * Alloc system memory for virtual framebuffer 1313 */ 1314 new_fb = vmalloc(new_len); 1315 if (!new_fb) 1316 return -ENOMEM; 1317 1318 if (info->screen_base) { 1319 memcpy(new_fb, old_fb, old_len); 1320 vfree(info->screen_base); 1321 } 1322 1323 info->screen_base = new_fb; 1324 info->fix.smem_len = PAGE_ALIGN(new_len); 1325 info->fix.smem_start = (unsigned long) new_fb; 1326 info->flags = smscufx_info_flags; 1327 } 1328 return 0; 1329 } 1330 1331 /* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master, 1332 * restart enabled, but no start byte, enable controller */ 1333 static int ufx_i2c_init(struct ufx_data *dev) 1334 { 1335 u32 tmp; 1336 1337 /* disable the controller before it can be reprogrammed */ 1338 int status = ufx_reg_write(dev, 0x106C, 0x00); 1339 check_warn_return(status, "failed to disable I2C"); 1340 1341 /* Setup the clock count registers 1342 * (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */ 1343 status = ufx_reg_write(dev, 0x1018, 12); 1344 check_warn_return(status, "error writing 0x1018"); 1345 1346 /* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */ 1347 status = ufx_reg_write(dev, 0x1014, 6); 1348 check_warn_return(status, "error writing 0x1014"); 1349 1350 status = ufx_reg_read(dev, 0x1000, &tmp); 1351 check_warn_return(status, "error reading 0x1000"); 1352 1353 /* set speed to std mode */ 1354 tmp &= ~(0x06); 1355 tmp |= 0x02; 1356 1357 /* 7-bit (not 10-bit) addressing */ 1358 tmp &= ~(0x10); 1359 1360 /* enable restart conditions and master mode */ 1361 tmp |= 0x21; 1362 1363 status = ufx_reg_write(dev, 0x1000, tmp); 1364 check_warn_return(status, "error writing 0x1000"); 1365 1366 /* Set normal tx using target address 0 */ 1367 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000); 1368 check_warn_return(status, "error setting TX mode bits in 0x1004"); 1369 1370 /* Enable the controller */ 1371 status = ufx_reg_write(dev, 0x106C, 0x01); 1372 check_warn_return(status, "failed to enable I2C"); 1373 1374 return 0; 1375 } 1376 1377 /* sets the I2C port mux and target address */ 1378 static int ufx_i2c_configure(struct ufx_data *dev) 1379 { 1380 int status = ufx_reg_write(dev, 0x106C, 0x00); 1381 check_warn_return(status, "failed to disable I2C"); 1382 1383 status = ufx_reg_write(dev, 0x3010, 0x00000000); 1384 check_warn_return(status, "failed to write 0x3010"); 1385 1386 /* A0h is std for any EDID, right shifted by one */ 1387 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1)); 1388 check_warn_return(status, "failed to set TAR bits in 0x1004"); 1389 1390 status = ufx_reg_write(dev, 0x106C, 0x01); 1391 check_warn_return(status, "failed to enable I2C"); 1392 1393 return 0; 1394 } 1395 1396 /* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no 1397 * monitor is connected, there is no error except for timeout */ 1398 static int ufx_i2c_wait_busy(struct ufx_data *dev) 1399 { 1400 u32 tmp; 1401 int i, status; 1402 1403 for (i = 0; i < 15; i++) { 1404 status = ufx_reg_read(dev, 0x1100, &tmp); 1405 check_warn_return(status, "0x1100 read failed"); 1406 1407 /* if BUSY is clear, check for error */ 1408 if ((tmp & 0x80000000) == 0) { 1409 if (tmp & 0x20000000) { 1410 pr_warn("I2C read failed, 0x1100=0x%08x", tmp); 1411 return -EIO; 1412 } 1413 1414 return 0; 1415 } 1416 1417 /* perform the first 10 retries without delay */ 1418 if (i >= 10) 1419 msleep(10); 1420 } 1421 1422 pr_warn("I2C access timed out, resetting I2C hardware"); 1423 status = ufx_reg_write(dev, 0x1100, 0x40000000); 1424 check_warn_return(status, "0x1100 write failed"); 1425 1426 return -ETIMEDOUT; 1427 } 1428 1429 /* reads a 128-byte EDID block from the currently selected port and TAR */ 1430 static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len) 1431 { 1432 int i, j, status; 1433 u32 *edid_u32 = (u32 *)edid; 1434 1435 BUG_ON(edid_len != EDID_LENGTH); 1436 1437 status = ufx_i2c_configure(dev); 1438 if (status < 0) { 1439 pr_err("ufx_i2c_configure failed"); 1440 return status; 1441 } 1442 1443 memset(edid, 0xff, EDID_LENGTH); 1444 1445 /* Read the 128-byte EDID as 2 bursts of 64 bytes */ 1446 for (i = 0; i < 2; i++) { 1447 u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8); 1448 status = ufx_reg_write(dev, 0x1100, temp); 1449 check_warn_return(status, "Failed to write 0x1100"); 1450 1451 temp |= 0x80000000; 1452 status = ufx_reg_write(dev, 0x1100, temp); 1453 check_warn_return(status, "Failed to write 0x1100"); 1454 1455 status = ufx_i2c_wait_busy(dev); 1456 check_warn_return(status, "Timeout waiting for I2C BUSY to clear"); 1457 1458 for (j = 0; j < 16; j++) { 1459 u32 data_reg_addr = 0x1110 + (j * 4); 1460 status = ufx_reg_read(dev, data_reg_addr, edid_u32++); 1461 check_warn_return(status, "Error reading i2c data"); 1462 } 1463 } 1464 1465 /* all FF's in the first 16 bytes indicates nothing is connected */ 1466 for (i = 0; i < 16; i++) { 1467 if (edid[i] != 0xFF) { 1468 pr_debug("edid data read successfully"); 1469 return EDID_LENGTH; 1470 } 1471 } 1472 1473 pr_warn("edid data contains all 0xff"); 1474 return -ETIMEDOUT; 1475 } 1476 1477 /* 1) use sw default 1478 * 2) Parse into various fb_info structs 1479 * 3) Allocate virtual framebuffer memory to back highest res mode 1480 * 1481 * Parses EDID into three places used by various parts of fbdev: 1482 * fb_var_screeninfo contains the timing of the monitor's preferred mode 1483 * fb_info.monspecs is full parsed EDID info, including monspecs.modedb 1484 * fb_info.modelist is a linked list of all monitor & VESA modes which work 1485 * 1486 * If EDID is not readable/valid, then modelist is all VESA modes, 1487 * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode 1488 * Returns 0 if successful */ 1489 static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info, 1490 char *default_edid, size_t default_edid_size) 1491 { 1492 const struct fb_videomode *default_vmode = NULL; 1493 u8 *edid; 1494 int i, result = 0, tries = 3; 1495 1496 if (info->dev) /* only use mutex if info has been registered */ 1497 mutex_lock(&info->lock); 1498 1499 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 1500 if (!edid) { 1501 result = -ENOMEM; 1502 goto error; 1503 } 1504 1505 fb_destroy_modelist(&info->modelist); 1506 memset(&info->monspecs, 0, sizeof(info->monspecs)); 1507 1508 /* Try to (re)read EDID from hardware first 1509 * EDID data may return, but not parse as valid 1510 * Try again a few times, in case of e.g. analog cable noise */ 1511 while (tries--) { 1512 i = ufx_read_edid(dev, edid, EDID_LENGTH); 1513 1514 if (i >= EDID_LENGTH) 1515 fb_edid_to_monspecs(edid, &info->monspecs); 1516 1517 if (info->monspecs.modedb_len > 0) { 1518 dev->edid = edid; 1519 dev->edid_size = i; 1520 break; 1521 } 1522 } 1523 1524 /* If that fails, use a previously returned EDID if available */ 1525 if (info->monspecs.modedb_len == 0) { 1526 pr_err("Unable to get valid EDID from device/display\n"); 1527 1528 if (dev->edid) { 1529 fb_edid_to_monspecs(dev->edid, &info->monspecs); 1530 if (info->monspecs.modedb_len > 0) 1531 pr_err("Using previously queried EDID\n"); 1532 } 1533 } 1534 1535 /* If that fails, use the default EDID we were handed */ 1536 if (info->monspecs.modedb_len == 0) { 1537 if (default_edid_size >= EDID_LENGTH) { 1538 fb_edid_to_monspecs(default_edid, &info->monspecs); 1539 if (info->monspecs.modedb_len > 0) { 1540 memcpy(edid, default_edid, default_edid_size); 1541 dev->edid = edid; 1542 dev->edid_size = default_edid_size; 1543 pr_err("Using default/backup EDID\n"); 1544 } 1545 } 1546 } 1547 1548 /* If we've got modes, let's pick a best default mode */ 1549 if (info->monspecs.modedb_len > 0) { 1550 1551 for (i = 0; i < info->monspecs.modedb_len; i++) { 1552 if (ufx_is_valid_mode(&info->monspecs.modedb[i], info)) 1553 fb_add_videomode(&info->monspecs.modedb[i], 1554 &info->modelist); 1555 else /* if we've removed top/best mode */ 1556 info->monspecs.misc &= ~FB_MISC_1ST_DETAIL; 1557 } 1558 1559 default_vmode = fb_find_best_display(&info->monspecs, 1560 &info->modelist); 1561 } 1562 1563 /* If everything else has failed, fall back to safe default mode */ 1564 if (default_vmode == NULL) { 1565 1566 struct fb_videomode fb_vmode = {0}; 1567 1568 /* Add the standard VESA modes to our modelist 1569 * Since we don't have EDID, there may be modes that 1570 * overspec monitor and/or are incorrect aspect ratio, etc. 1571 * But at least the user has a chance to choose 1572 */ 1573 for (i = 0; i < VESA_MODEDB_SIZE; i++) { 1574 if (ufx_is_valid_mode((struct fb_videomode *) 1575 &vesa_modes[i], info)) 1576 fb_add_videomode(&vesa_modes[i], 1577 &info->modelist); 1578 } 1579 1580 /* default to resolution safe for projectors 1581 * (since they are most common case without EDID) 1582 */ 1583 fb_vmode.xres = 800; 1584 fb_vmode.yres = 600; 1585 fb_vmode.refresh = 60; 1586 default_vmode = fb_find_nearest_mode(&fb_vmode, 1587 &info->modelist); 1588 } 1589 1590 /* If we have good mode and no active clients */ 1591 if ((default_vmode != NULL) && (dev->fb_count == 0)) { 1592 1593 fb_videomode_to_var(&info->var, default_vmode); 1594 ufx_var_color_format(&info->var); 1595 1596 /* with mode size info, we can now alloc our framebuffer */ 1597 memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix)); 1598 info->fix.line_length = info->var.xres * 1599 (info->var.bits_per_pixel / 8); 1600 1601 result = ufx_realloc_framebuffer(dev, info); 1602 1603 } else 1604 result = -EINVAL; 1605 1606 error: 1607 if (edid && (dev->edid != edid)) 1608 kfree(edid); 1609 1610 if (info->dev) 1611 mutex_unlock(&info->lock); 1612 1613 return result; 1614 } 1615 1616 static int ufx_usb_probe(struct usb_interface *interface, 1617 const struct usb_device_id *id) 1618 { 1619 struct usb_device *usbdev; 1620 struct ufx_data *dev; 1621 struct fb_info *info; 1622 int retval; 1623 u32 id_rev, fpga_rev; 1624 1625 /* usb initialization */ 1626 usbdev = interface_to_usbdev(interface); 1627 BUG_ON(!usbdev); 1628 1629 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1630 if (dev == NULL) { 1631 dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n"); 1632 return -ENOMEM; 1633 } 1634 1635 /* we need to wait for both usb and fbdev to spin down on disconnect */ 1636 kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */ 1637 kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */ 1638 1639 dev->udev = usbdev; 1640 dev->gdev = &usbdev->dev; /* our generic struct device * */ 1641 usb_set_intfdata(interface, dev); 1642 1643 dev_dbg(dev->gdev, "%s %s - serial #%s\n", 1644 usbdev->manufacturer, usbdev->product, usbdev->serial); 1645 dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n", 1646 le16_to_cpu(usbdev->descriptor.idVendor), 1647 le16_to_cpu(usbdev->descriptor.idProduct), 1648 le16_to_cpu(usbdev->descriptor.bcdDevice), dev); 1649 dev_dbg(dev->gdev, "console enable=%d\n", console); 1650 dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio); 1651 1652 if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) { 1653 dev_err(dev->gdev, "ufx_alloc_urb_list failed\n"); 1654 goto e_nomem; 1655 } 1656 1657 /* We don't register a new USB class. Our client interface is fbdev */ 1658 1659 /* allocates framebuffer driver structure, not framebuffer memory */ 1660 info = framebuffer_alloc(0, &usbdev->dev); 1661 if (!info) 1662 goto e_nomem; 1663 1664 dev->info = info; 1665 info->par = dev; 1666 info->pseudo_palette = dev->pseudo_palette; 1667 info->fbops = &ufx_ops; 1668 INIT_LIST_HEAD(&info->modelist); 1669 1670 retval = fb_alloc_cmap(&info->cmap, 256, 0); 1671 if (retval < 0) { 1672 dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval); 1673 goto destroy_modedb; 1674 } 1675 1676 INIT_DELAYED_WORK(&dev->free_framebuffer_work, 1677 ufx_free_framebuffer_work); 1678 1679 retval = ufx_reg_read(dev, 0x3000, &id_rev); 1680 check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval); 1681 dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev); 1682 1683 retval = ufx_reg_read(dev, 0x3004, &fpga_rev); 1684 check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval); 1685 dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev); 1686 1687 dev_dbg(dev->gdev, "resetting device"); 1688 retval = ufx_lite_reset(dev); 1689 check_warn_goto_error(retval, "error %d resetting device", retval); 1690 1691 dev_dbg(dev->gdev, "configuring system clock"); 1692 retval = ufx_config_sys_clk(dev); 1693 check_warn_goto_error(retval, "error %d configuring system clock", retval); 1694 1695 dev_dbg(dev->gdev, "configuring DDR2 controller"); 1696 retval = ufx_config_ddr2(dev); 1697 check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval); 1698 1699 dev_dbg(dev->gdev, "configuring I2C controller"); 1700 retval = ufx_i2c_init(dev); 1701 check_warn_goto_error(retval, "error %d initialising I2C controller", retval); 1702 1703 dev_dbg(dev->gdev, "selecting display mode"); 1704 retval = ufx_setup_modes(dev, info, NULL, 0); 1705 check_warn_goto_error(retval, "unable to find common mode for display and adapter"); 1706 1707 retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001); 1708 check_warn_goto_error(retval, "error %d enabling graphics engine", retval); 1709 1710 /* ready to begin using device */ 1711 atomic_set(&dev->usb_active, 1); 1712 1713 dev_dbg(dev->gdev, "checking var"); 1714 retval = ufx_ops_check_var(&info->var, info); 1715 check_warn_goto_error(retval, "error %d ufx_ops_check_var", retval); 1716 1717 dev_dbg(dev->gdev, "setting par"); 1718 retval = ufx_ops_set_par(info); 1719 check_warn_goto_error(retval, "error %d ufx_ops_set_par", retval); 1720 1721 dev_dbg(dev->gdev, "registering framebuffer"); 1722 retval = register_framebuffer(info); 1723 check_warn_goto_error(retval, "error %d register_framebuffer", retval); 1724 1725 dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution." 1726 " Using %dK framebuffer memory\n", info->node, 1727 info->var.xres, info->var.yres, info->fix.smem_len >> 10); 1728 1729 return 0; 1730 1731 error: 1732 fb_dealloc_cmap(&info->cmap); 1733 destroy_modedb: 1734 fb_destroy_modedb(info->monspecs.modedb); 1735 vfree(info->screen_base); 1736 fb_destroy_modelist(&info->modelist); 1737 framebuffer_release(info); 1738 put_ref: 1739 kref_put(&dev->kref, ufx_free); /* ref for framebuffer */ 1740 kref_put(&dev->kref, ufx_free); /* last ref from kref_init */ 1741 return retval; 1742 1743 e_nomem: 1744 retval = -ENOMEM; 1745 goto put_ref; 1746 } 1747 1748 static void ufx_usb_disconnect(struct usb_interface *interface) 1749 { 1750 struct ufx_data *dev; 1751 1752 mutex_lock(&disconnect_mutex); 1753 1754 dev = usb_get_intfdata(interface); 1755 1756 pr_debug("USB disconnect starting\n"); 1757 1758 /* we virtualize until all fb clients release. Then we free */ 1759 dev->virtualized = true; 1760 1761 /* When non-active we'll update virtual framebuffer, but no new urbs */ 1762 atomic_set(&dev->usb_active, 0); 1763 1764 usb_set_intfdata(interface, NULL); 1765 1766 /* if clients still have us open, will be freed on last close */ 1767 if (dev->fb_count == 0) 1768 schedule_delayed_work(&dev->free_framebuffer_work, 0); 1769 1770 /* release reference taken by kref_init in probe() */ 1771 kref_put(&dev->kref, ufx_free); 1772 1773 /* consider ufx_data freed */ 1774 1775 mutex_unlock(&disconnect_mutex); 1776 } 1777 1778 static struct usb_driver ufx_driver = { 1779 .name = "smscufx", 1780 .probe = ufx_usb_probe, 1781 .disconnect = ufx_usb_disconnect, 1782 .id_table = id_table, 1783 }; 1784 1785 module_usb_driver(ufx_driver); 1786 1787 static void ufx_urb_completion(struct urb *urb) 1788 { 1789 struct urb_node *unode = urb->context; 1790 struct ufx_data *dev = unode->dev; 1791 unsigned long flags; 1792 1793 /* sync/async unlink faults aren't errors */ 1794 if (urb->status) { 1795 if (!(urb->status == -ENOENT || 1796 urb->status == -ECONNRESET || 1797 urb->status == -ESHUTDOWN)) { 1798 pr_err("%s - nonzero write bulk status received: %d\n", 1799 __func__, urb->status); 1800 atomic_set(&dev->lost_pixels, 1); 1801 } 1802 } 1803 1804 urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */ 1805 1806 spin_lock_irqsave(&dev->urbs.lock, flags); 1807 list_add_tail(&unode->entry, &dev->urbs.list); 1808 dev->urbs.available++; 1809 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1810 1811 /* When using fb_defio, we deadlock if up() is called 1812 * while another is waiting. So queue to another process */ 1813 if (fb_defio) 1814 schedule_delayed_work(&unode->release_urb_work, 0); 1815 else 1816 up(&dev->urbs.limit_sem); 1817 } 1818 1819 static void ufx_free_urb_list(struct ufx_data *dev) 1820 { 1821 int count = dev->urbs.count; 1822 struct list_head *node; 1823 struct urb_node *unode; 1824 struct urb *urb; 1825 int ret; 1826 unsigned long flags; 1827 1828 pr_debug("Waiting for completes and freeing all render urbs\n"); 1829 1830 /* keep waiting and freeing, until we've got 'em all */ 1831 while (count--) { 1832 /* Getting interrupted means a leak, but ok at shutdown*/ 1833 ret = down_interruptible(&dev->urbs.limit_sem); 1834 if (ret) 1835 break; 1836 1837 spin_lock_irqsave(&dev->urbs.lock, flags); 1838 1839 node = dev->urbs.list.next; /* have reserved one with sem */ 1840 list_del_init(node); 1841 1842 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1843 1844 unode = list_entry(node, struct urb_node, entry); 1845 urb = unode->urb; 1846 1847 /* Free each separately allocated piece */ 1848 usb_free_coherent(urb->dev, dev->urbs.size, 1849 urb->transfer_buffer, urb->transfer_dma); 1850 usb_free_urb(urb); 1851 kfree(node); 1852 } 1853 } 1854 1855 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size) 1856 { 1857 int i = 0; 1858 struct urb *urb; 1859 struct urb_node *unode; 1860 char *buf; 1861 1862 spin_lock_init(&dev->urbs.lock); 1863 1864 dev->urbs.size = size; 1865 INIT_LIST_HEAD(&dev->urbs.list); 1866 1867 while (i < count) { 1868 unode = kzalloc(sizeof(*unode), GFP_KERNEL); 1869 if (!unode) 1870 break; 1871 unode->dev = dev; 1872 1873 INIT_DELAYED_WORK(&unode->release_urb_work, 1874 ufx_release_urb_work); 1875 1876 urb = usb_alloc_urb(0, GFP_KERNEL); 1877 if (!urb) { 1878 kfree(unode); 1879 break; 1880 } 1881 unode->urb = urb; 1882 1883 buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL, 1884 &urb->transfer_dma); 1885 if (!buf) { 1886 kfree(unode); 1887 usb_free_urb(urb); 1888 break; 1889 } 1890 1891 /* urb->transfer_buffer_length set to actual before submit */ 1892 usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1), 1893 buf, size, ufx_urb_completion, unode); 1894 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; 1895 1896 list_add_tail(&unode->entry, &dev->urbs.list); 1897 1898 i++; 1899 } 1900 1901 sema_init(&dev->urbs.limit_sem, i); 1902 dev->urbs.count = i; 1903 dev->urbs.available = i; 1904 1905 pr_debug("allocated %d %d byte urbs\n", i, (int) size); 1906 1907 return i; 1908 } 1909 1910 static struct urb *ufx_get_urb(struct ufx_data *dev) 1911 { 1912 int ret = 0; 1913 struct list_head *entry; 1914 struct urb_node *unode; 1915 struct urb *urb = NULL; 1916 unsigned long flags; 1917 1918 /* Wait for an in-flight buffer to complete and get re-queued */ 1919 ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT); 1920 if (ret) { 1921 atomic_set(&dev->lost_pixels, 1); 1922 pr_warn("wait for urb interrupted: %x available: %d\n", 1923 ret, dev->urbs.available); 1924 goto error; 1925 } 1926 1927 spin_lock_irqsave(&dev->urbs.lock, flags); 1928 1929 BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */ 1930 entry = dev->urbs.list.next; 1931 list_del_init(entry); 1932 dev->urbs.available--; 1933 1934 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1935 1936 unode = list_entry(entry, struct urb_node, entry); 1937 urb = unode->urb; 1938 1939 error: 1940 return urb; 1941 } 1942 1943 static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len) 1944 { 1945 int ret; 1946 1947 BUG_ON(len > dev->urbs.size); 1948 1949 urb->transfer_buffer_length = len; /* set to actual payload len */ 1950 ret = usb_submit_urb(urb, GFP_KERNEL); 1951 if (ret) { 1952 ufx_urb_completion(urb); /* because no one else will */ 1953 atomic_set(&dev->lost_pixels, 1); 1954 pr_err("usb_submit_urb error %x\n", ret); 1955 } 1956 return ret; 1957 } 1958 1959 module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP); 1960 MODULE_PARM_DESC(console, "Allow fbcon to be used on this display"); 1961 1962 module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP); 1963 MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support"); 1964 1965 MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); 1966 MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver"); 1967 MODULE_LICENSE("GPL"); 1968