1 /* 2 * Silicon Motion SM712 frame buffer device 3 * 4 * Copyright (C) 2006 Silicon Motion Technology Corp. 5 * Authors: Ge Wang, gewang@siliconmotion.com 6 * Boyod boyod.yang@siliconmotion.com.cn 7 * 8 * Copyright (C) 2009 Lemote, Inc. 9 * Author: Wu Zhangjin, wuzhangjin@gmail.com 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file COPYING in the main directory of this archive for 13 * more details. 14 */ 15 16 #define FB_ACCEL_SMI_LYNX 88 17 18 #define SCREEN_X_RES 1024 19 #define SCREEN_Y_RES 600 20 #define SCREEN_BPP 16 21 22 /*Assume SM712 graphics chip has 4MB VRAM */ 23 #define SM712_VIDEOMEMORYSIZE 0x00400000 24 /*Assume SM722 graphics chip has 8MB VRAM */ 25 #define SM722_VIDEOMEMORYSIZE 0x00800000 26 27 #define dac_reg (0x3c8) 28 #define dac_val (0x3c9) 29 30 extern void __iomem *smtc_regbaseaddress; 31 #define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg) 32 33 #define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg) 34 35 #define SIZE_SR00_SR04 (0x04 - 0x00 + 1) 36 #define SIZE_SR10_SR24 (0x24 - 0x10 + 1) 37 #define SIZE_SR30_SR75 (0x75 - 0x30 + 1) 38 #define SIZE_SR80_SR93 (0x93 - 0x80 + 1) 39 #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1) 40 #define SIZE_GR00_GR08 (0x08 - 0x00 + 1) 41 #define SIZE_AR00_AR14 (0x14 - 0x00 + 1) 42 #define SIZE_CR00_CR18 (0x18 - 0x00 + 1) 43 #define SIZE_CR30_CR4D (0x4D - 0x30 + 1) 44 #define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1) 45 46 static inline void smtc_crtcw(int reg, int val) 47 { 48 smtc_mmiowb(reg, 0x3d4); 49 smtc_mmiowb(val, 0x3d5); 50 } 51 52 static inline void smtc_grphw(int reg, int val) 53 { 54 smtc_mmiowb(reg, 0x3ce); 55 smtc_mmiowb(val, 0x3cf); 56 } 57 58 static inline void smtc_attrw(int reg, int val) 59 { 60 smtc_mmiorb(0x3da); 61 smtc_mmiowb(reg, 0x3c0); 62 smtc_mmiorb(0x3c1); 63 smtc_mmiowb(val, 0x3c0); 64 } 65 66 static inline void smtc_seqw(int reg, int val) 67 { 68 smtc_mmiowb(reg, 0x3c4); 69 smtc_mmiowb(val, 0x3c5); 70 } 71 72 static inline unsigned int smtc_seqr(int reg) 73 { 74 smtc_mmiowb(reg, 0x3c4); 75 return smtc_mmiorb(0x3c5); 76 } 77 78 /* The next structure holds all information relevant for a specific video mode. 79 */ 80 81 struct modeinit { 82 int mmsizex; 83 int mmsizey; 84 int bpp; 85 int hz; 86 unsigned char init_misc; 87 unsigned char init_sr00_sr04[SIZE_SR00_SR04]; 88 unsigned char init_sr10_sr24[SIZE_SR10_SR24]; 89 unsigned char init_sr30_sr75[SIZE_SR30_SR75]; 90 unsigned char init_sr80_sr93[SIZE_SR80_SR93]; 91 unsigned char init_sra0_sraf[SIZE_SRA0_SRAF]; 92 unsigned char init_gr00_gr08[SIZE_GR00_GR08]; 93 unsigned char init_ar00_ar14[SIZE_AR00_AR14]; 94 unsigned char init_cr00_cr18[SIZE_CR00_CR18]; 95 unsigned char init_cr30_cr4d[SIZE_CR30_CR4D]; 96 unsigned char init_cr90_cra7[SIZE_CR90_CRA7]; 97 }; 98 99 #ifdef __BIG_ENDIAN 100 #define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \ 101 ((g & 0xe000) >> 13) | \ 102 ((g & 0x1c00) << 3) | \ 103 ((b & 0xf800) >> 3)) 104 #define big_addr 0x800000 105 #define mmio_addr 0x00800000 106 #define seqw17() smtc_seqw(0x17, 0x30) 107 #define big_pixel_depth(p, d) {if (p == 24) {p = 32; d = 32; } } 108 #define big_swap(p) ((p & 0xff00ff00 >> 8) | (p & 0x00ff00ff << 8)) 109 #else 110 #define pal_rgb(r, g, b, val) val 111 #define big_addr 0 112 #define mmio_addr 0x00c00000 113 #define seqw17() do { } while (0) 114 #define big_pixel_depth(p, d) do { } while (0) 115 #define big_swap(p) p 116 #endif 117