1 /* 2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver 3 * 4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> 5 * 6 * Copyright 1999-2000 Jeff Garzik 7 * 8 * Contributors: 9 * 10 * Ani Joshi: Lots of debugging and cleanup work, really helped 11 * get the driver going 12 * 13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization 14 * 15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr 16 * 17 * Paul Richards: Bug fixes, updates 18 * 19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven 20 * Includes riva_hw.c from nVidia, see copyright below. 21 * KGI code provided the basis for state storage, init, and mode switching. 22 * 23 * This file is subject to the terms and conditions of the GNU General Public 24 * License. See the file COPYING in the main directory of this archive 25 * for more details. 26 * 27 * Known bugs and issues: 28 * restoring text mode fails 29 * doublescan modes are broken 30 */ 31 32 #include <linux/aperture.h> 33 #include <linux/module.h> 34 #include <linux/kernel.h> 35 #include <linux/errno.h> 36 #include <linux/string.h> 37 #include <linux/mm.h> 38 #include <linux/slab.h> 39 #include <linux/delay.h> 40 #include <linux/fb.h> 41 #include <linux/init.h> 42 #include <linux/pci.h> 43 #include <linux/backlight.h> 44 #include <linux/bitrev.h> 45 #ifdef CONFIG_PMAC_BACKLIGHT 46 #include <asm/machdep.h> 47 #include <asm/backlight.h> 48 #endif 49 50 #include "rivafb.h" 51 #include "nvreg.h" 52 53 /* version number of this driver */ 54 #define RIVAFB_VERSION "0.9.5b" 55 56 /* ------------------------------------------------------------------------- * 57 * 58 * various helpful macros and constants 59 * 60 * ------------------------------------------------------------------------- */ 61 #ifdef CONFIG_FB_RIVA_DEBUG 62 #define NVTRACE printk 63 #else 64 #define NVTRACE if(0) printk 65 #endif 66 67 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) 68 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) 69 70 #ifdef CONFIG_FB_RIVA_DEBUG 71 #define assert(expr) \ 72 if(!(expr)) { \ 73 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 74 #expr,__FILE__,__func__,__LINE__); \ 75 BUG(); \ 76 } 77 #else 78 #define assert(expr) 79 #endif 80 81 #define PFX "rivafb: " 82 83 /* macro that allows you to set overflow bits */ 84 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) 85 #define SetBit(n) (1<<(n)) 86 #define Set8Bits(value) ((value)&0xff) 87 88 /* HW cursor parameters */ 89 #define MAX_CURS 32 90 91 /* ------------------------------------------------------------------------- * 92 * 93 * prototypes 94 * 95 * ------------------------------------------------------------------------- */ 96 97 static int rivafb_blank(int blank, struct fb_info *info); 98 99 /* ------------------------------------------------------------------------- * 100 * 101 * card identification 102 * 103 * ------------------------------------------------------------------------- */ 104 105 static const struct pci_device_id rivafb_pci_tbl[] = { 106 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128) }, 107 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT) }, 108 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2) }, 109 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2) }, 110 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2) }, 111 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2) }, 112 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2) }, 113 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR) }, 114 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR) }, 115 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO) }, 116 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX) }, 117 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2) }, 118 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO) }, 119 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR) }, 120 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS) }, 121 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2) }, 122 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA) }, 123 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO) }, 124 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460) }, 125 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440) }, 126 // NF2/IGP version, GeForce 4 MX, NV18 127 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x01f0) }, 128 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420) }, 129 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO) }, 130 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO) }, 131 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32) }, 132 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL) }, 133 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64) }, 134 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200) }, 135 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL) }, 136 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL) }, 137 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2) }, 138 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3) }, 139 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1) }, 140 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2) }, 141 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC) }, 142 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600) }, 143 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400) }, 144 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200) }, 145 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL) }, 146 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL) }, 147 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL) }, 148 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200) }, 149 { } /* terminate list */ 150 }; 151 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); 152 153 /* ------------------------------------------------------------------------- * 154 * 155 * global variables 156 * 157 * ------------------------------------------------------------------------- */ 158 159 /* command line data, set in rivafb_setup() */ 160 static int flatpanel = -1; /* Autodetect later */ 161 static int forceCRTC = -1; 162 static bool noaccel = 0; 163 static bool nomtrr = 0; 164 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); 165 166 static char *mode_option = NULL; 167 static bool strictmode = 0; 168 169 static struct fb_fix_screeninfo rivafb_fix = { 170 .type = FB_TYPE_PACKED_PIXELS, 171 .xpanstep = 1, 172 .ypanstep = 1, 173 }; 174 175 static struct fb_var_screeninfo rivafb_default_var = { 176 .xres = 640, 177 .yres = 480, 178 .xres_virtual = 640, 179 .yres_virtual = 480, 180 .bits_per_pixel = 8, 181 .red = {0, 8, 0}, 182 .green = {0, 8, 0}, 183 .blue = {0, 8, 0}, 184 .transp = {0, 0, 0}, 185 .activate = FB_ACTIVATE_NOW, 186 .height = -1, 187 .width = -1, 188 .pixclock = 39721, 189 .left_margin = 40, 190 .right_margin = 24, 191 .upper_margin = 32, 192 .lower_margin = 11, 193 .hsync_len = 96, 194 .vsync_len = 2, 195 .vmode = FB_VMODE_NONINTERLACED 196 }; 197 198 /* from GGI */ 199 static const struct riva_regs reg_template = { 200 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ 201 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 202 0x41, 0x01, 0x0F, 0x00, 0x00}, 203 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ 204 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ 206 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 207 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 208 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 209 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ 210 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 211 0x00, /* 0x40 */ 212 }, 213 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ 214 0xFF}, 215 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ 216 0xEB /* MISC */ 217 }; 218 219 /* 220 * Backlight control 221 */ 222 #ifdef CONFIG_FB_RIVA_BACKLIGHT 223 /* We do not have any information about which values are allowed, thus 224 * we used safe values. 225 */ 226 #define MIN_LEVEL 0x158 227 #define MAX_LEVEL 0x534 228 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) 229 230 static int riva_bl_get_level_brightness(struct riva_par *par, 231 int level) 232 { 233 struct fb_info *info = pci_get_drvdata(par->pdev); 234 int nlevel; 235 236 /* Get and convert the value */ 237 /* No locking on bl_curve since accessing a single value */ 238 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; 239 240 if (nlevel < 0) 241 nlevel = 0; 242 else if (nlevel < MIN_LEVEL) 243 nlevel = MIN_LEVEL; 244 else if (nlevel > MAX_LEVEL) 245 nlevel = MAX_LEVEL; 246 247 return nlevel; 248 } 249 250 static int riva_bl_update_status(struct backlight_device *bd) 251 { 252 struct riva_par *par = bl_get_data(bd); 253 U032 tmp_pcrt, tmp_pmc; 254 int level = backlight_get_brightness(bd); 255 256 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; 257 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC; 258 if(level > 0) { 259 tmp_pcrt |= 0x1; 260 tmp_pmc |= (1 << 31); /* backlight bit */ 261 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ 262 } 263 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt); 264 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); 265 266 return 0; 267 } 268 269 static const struct backlight_ops riva_bl_ops = { 270 .update_status = riva_bl_update_status, 271 }; 272 273 static void riva_bl_init(struct riva_par *par) 274 { 275 struct backlight_properties props; 276 struct fb_info *info = pci_get_drvdata(par->pdev); 277 struct backlight_device *bd; 278 char name[12]; 279 280 if (!par->FlatPanel) 281 return; 282 283 #ifdef CONFIG_PMAC_BACKLIGHT 284 if (!machine_is(powermac) || 285 !pmac_has_backlight_type("mnca")) 286 return; 287 #endif 288 289 snprintf(name, sizeof(name), "rivabl%d", info->node); 290 291 memset(&props, 0, sizeof(struct backlight_properties)); 292 props.type = BACKLIGHT_RAW; 293 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 294 bd = backlight_device_register(name, info->device, par, &riva_bl_ops, 295 &props); 296 if (IS_ERR(bd)) { 297 info->bl_dev = NULL; 298 printk(KERN_WARNING "riva: Backlight registration failed\n"); 299 goto error; 300 } 301 302 info->bl_dev = bd; 303 fb_bl_default_curve(info, 0, 304 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL, 305 FB_BACKLIGHT_MAX); 306 307 bd->props.brightness = bd->props.max_brightness; 308 bd->props.power = BACKLIGHT_POWER_ON; 309 backlight_update_status(bd); 310 311 printk("riva: Backlight initialized (%s)\n", name); 312 313 return; 314 315 error: 316 return; 317 } 318 319 static void riva_bl_exit(struct fb_info *info) 320 { 321 struct backlight_device *bd = info->bl_dev; 322 323 backlight_device_unregister(bd); 324 printk("riva: Backlight unloaded\n"); 325 } 326 #else 327 static inline void riva_bl_init(struct riva_par *par) {} 328 static inline void riva_bl_exit(struct fb_info *info) {} 329 #endif /* CONFIG_FB_RIVA_BACKLIGHT */ 330 331 /* ------------------------------------------------------------------------- * 332 * 333 * MMIO access macros 334 * 335 * ------------------------------------------------------------------------- */ 336 337 static inline void CRTCout(struct riva_par *par, unsigned char index, 338 unsigned char val) 339 { 340 VGA_WR08(par->riva.PCIO, 0x3d4, index); 341 VGA_WR08(par->riva.PCIO, 0x3d5, val); 342 } 343 344 static inline unsigned char CRTCin(struct riva_par *par, 345 unsigned char index) 346 { 347 VGA_WR08(par->riva.PCIO, 0x3d4, index); 348 return (VGA_RD08(par->riva.PCIO, 0x3d5)); 349 } 350 351 static inline void GRAout(struct riva_par *par, unsigned char index, 352 unsigned char val) 353 { 354 VGA_WR08(par->riva.PVIO, 0x3ce, index); 355 VGA_WR08(par->riva.PVIO, 0x3cf, val); 356 } 357 358 static inline unsigned char GRAin(struct riva_par *par, 359 unsigned char index) 360 { 361 VGA_WR08(par->riva.PVIO, 0x3ce, index); 362 return (VGA_RD08(par->riva.PVIO, 0x3cf)); 363 } 364 365 static inline void SEQout(struct riva_par *par, unsigned char index, 366 unsigned char val) 367 { 368 VGA_WR08(par->riva.PVIO, 0x3c4, index); 369 VGA_WR08(par->riva.PVIO, 0x3c5, val); 370 } 371 372 static inline unsigned char SEQin(struct riva_par *par, 373 unsigned char index) 374 { 375 VGA_WR08(par->riva.PVIO, 0x3c4, index); 376 return (VGA_RD08(par->riva.PVIO, 0x3c5)); 377 } 378 379 static inline void ATTRout(struct riva_par *par, unsigned char index, 380 unsigned char val) 381 { 382 VGA_WR08(par->riva.PCIO, 0x3c0, index); 383 VGA_WR08(par->riva.PCIO, 0x3c0, val); 384 } 385 386 static inline unsigned char ATTRin(struct riva_par *par, 387 unsigned char index) 388 { 389 VGA_WR08(par->riva.PCIO, 0x3c0, index); 390 return (VGA_RD08(par->riva.PCIO, 0x3c1)); 391 } 392 393 static inline void MISCout(struct riva_par *par, unsigned char val) 394 { 395 VGA_WR08(par->riva.PVIO, 0x3c2, val); 396 } 397 398 static inline unsigned char MISCin(struct riva_par *par) 399 { 400 return (VGA_RD08(par->riva.PVIO, 0x3cc)); 401 } 402 403 static inline void reverse_order(u32 *l) 404 { 405 u8 *a = (u8 *)l; 406 a[0] = bitrev8(a[0]); 407 a[1] = bitrev8(a[1]); 408 a[2] = bitrev8(a[2]); 409 a[3] = bitrev8(a[3]); 410 } 411 412 /* ------------------------------------------------------------------------- * 413 * 414 * cursor stuff 415 * 416 * ------------------------------------------------------------------------- */ 417 418 /** 419 * rivafb_load_cursor_image - load cursor image to hardware 420 * @data8: address to monochrome bitmap (1 = foreground color, 0 = background) 421 * @par: pointer to private data 422 * @w: width of cursor image in pixels 423 * @h: height of cursor image in scanlines 424 * @bg: background color (ARGB1555) - alpha bit determines opacity 425 * @fg: foreground color (ARGB1555) 426 * 427 * DESCRIPTiON: 428 * Loads cursor image based on a monochrome source and mask bitmap. The 429 * image bits determines the color of the pixel, 0 for background, 1 for 430 * foreground. Only the affected region (as determined by @w and @h 431 * parameters) will be updated. 432 * 433 * CALLED FROM: 434 * rivafb_cursor() 435 */ 436 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, 437 u16 bg, u16 fg, u32 w, u32 h) 438 { 439 int i, j, k = 0; 440 u32 b, tmp; 441 u32 *data = (u32 *)data8; 442 bg = le16_to_cpu(bg); 443 fg = le16_to_cpu(fg); 444 445 w = (w + 1) & ~1; 446 447 for (i = 0; i < h; i++) { 448 b = *data++; 449 reverse_order(&b); 450 451 for (j = 0; j < w/2; j++) { 452 tmp = 0; 453 #if defined (__BIG_ENDIAN) 454 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 455 b <<= 1; 456 tmp |= (b & (1 << 31)) ? fg : bg; 457 b <<= 1; 458 #else 459 tmp = (b & 1) ? fg : bg; 460 b >>= 1; 461 tmp |= (b & 1) ? fg << 16 : bg << 16; 462 b >>= 1; 463 #endif 464 writel(tmp, &par->riva.CURSOR[k++]); 465 } 466 k += (MAX_CURS - w)/2; 467 } 468 } 469 470 /* ------------------------------------------------------------------------- * 471 * 472 * general utility functions 473 * 474 * ------------------------------------------------------------------------- */ 475 476 /** 477 * riva_wclut - set CLUT entry 478 * @chip: pointer to RIVA_HW_INST object 479 * @regnum: register number 480 * @red: red component 481 * @green: green component 482 * @blue: blue component 483 * 484 * DESCRIPTION: 485 * Sets color register @regnum. 486 * 487 * CALLED FROM: 488 * rivafb_setcolreg() 489 */ 490 static void riva_wclut(RIVA_HW_INST *chip, 491 unsigned char regnum, unsigned char red, 492 unsigned char green, unsigned char blue) 493 { 494 VGA_WR08(chip->PDIO, 0x3c8, regnum); 495 VGA_WR08(chip->PDIO, 0x3c9, red); 496 VGA_WR08(chip->PDIO, 0x3c9, green); 497 VGA_WR08(chip->PDIO, 0x3c9, blue); 498 } 499 500 /** 501 * riva_rclut - read fromCLUT register 502 * @chip: pointer to RIVA_HW_INST object 503 * @regnum: register number 504 * @red: red component 505 * @green: green component 506 * @blue: blue component 507 * 508 * DESCRIPTION: 509 * Reads red, green, and blue from color register @regnum. 510 * 511 * CALLED FROM: 512 * rivafb_setcolreg() 513 */ 514 static void riva_rclut(RIVA_HW_INST *chip, 515 unsigned char regnum, unsigned char *red, 516 unsigned char *green, unsigned char *blue) 517 { 518 519 VGA_WR08(chip->PDIO, 0x3c7, regnum); 520 *red = VGA_RD08(chip->PDIO, 0x3c9); 521 *green = VGA_RD08(chip->PDIO, 0x3c9); 522 *blue = VGA_RD08(chip->PDIO, 0x3c9); 523 } 524 525 /** 526 * riva_save_state - saves current chip state 527 * @par: pointer to riva_par object containing info for current riva board 528 * @regs: pointer to riva_regs object 529 * 530 * DESCRIPTION: 531 * Saves current chip state to @regs. 532 * 533 * CALLED FROM: 534 * rivafb_probe() 535 */ 536 /* from GGI */ 537 static void riva_save_state(struct riva_par *par, struct riva_regs *regs) 538 { 539 int i; 540 541 NVTRACE_ENTER(); 542 par->riva.LockUnlock(&par->riva, 0); 543 544 par->riva.UnloadStateExt(&par->riva, ®s->ext); 545 546 regs->misc_output = MISCin(par); 547 548 for (i = 0; i < NUM_CRT_REGS; i++) 549 regs->crtc[i] = CRTCin(par, i); 550 551 for (i = 0; i < NUM_ATC_REGS; i++) 552 regs->attr[i] = ATTRin(par, i); 553 554 for (i = 0; i < NUM_GRC_REGS; i++) 555 regs->gra[i] = GRAin(par, i); 556 557 for (i = 0; i < NUM_SEQ_REGS; i++) 558 regs->seq[i] = SEQin(par, i); 559 NVTRACE_LEAVE(); 560 } 561 562 /** 563 * riva_load_state - loads current chip state 564 * @par: pointer to riva_par object containing info for current riva board 565 * @regs: pointer to riva_regs object 566 * 567 * DESCRIPTION: 568 * Loads chip state from @regs. 569 * 570 * CALLED FROM: 571 * riva_load_video_mode() 572 * rivafb_probe() 573 * rivafb_remove() 574 */ 575 /* from GGI */ 576 static void riva_load_state(struct riva_par *par, struct riva_regs *regs) 577 { 578 RIVA_HW_STATE *state = ®s->ext; 579 int i; 580 581 NVTRACE_ENTER(); 582 CRTCout(par, 0x11, 0x00); 583 584 par->riva.LockUnlock(&par->riva, 0); 585 586 par->riva.LoadStateExt(&par->riva, state); 587 588 MISCout(par, regs->misc_output); 589 590 for (i = 0; i < NUM_CRT_REGS; i++) { 591 switch (i) { 592 case 0x19: 593 case 0x20 ... 0x40: 594 break; 595 default: 596 CRTCout(par, i, regs->crtc[i]); 597 } 598 } 599 600 for (i = 0; i < NUM_ATC_REGS; i++) 601 ATTRout(par, i, regs->attr[i]); 602 603 for (i = 0; i < NUM_GRC_REGS; i++) 604 GRAout(par, i, regs->gra[i]); 605 606 for (i = 0; i < NUM_SEQ_REGS; i++) 607 SEQout(par, i, regs->seq[i]); 608 NVTRACE_LEAVE(); 609 } 610 611 /** 612 * riva_load_video_mode - calculate timings 613 * @info: pointer to fb_info object containing info for current riva board 614 * 615 * DESCRIPTION: 616 * Calculate some timings and then send em off to riva_load_state(). 617 * 618 * CALLED FROM: 619 * rivafb_set_par() 620 */ 621 static int riva_load_video_mode(struct fb_info *info) 622 { 623 int bpp, width, hDisplaySize, hDisplay, hStart, 624 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; 625 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; 626 int rc; 627 struct riva_par *par = info->par; 628 struct riva_regs newmode; 629 630 NVTRACE_ENTER(); 631 /* time to calculate */ 632 rivafb_blank(FB_BLANK_NORMAL, info); 633 634 bpp = info->var.bits_per_pixel; 635 if (bpp == 16 && info->var.green.length == 5) 636 bpp = 15; 637 width = info->var.xres_virtual; 638 hDisplaySize = info->var.xres; 639 hDisplay = (hDisplaySize / 8) - 1; 640 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; 641 hEnd = (hDisplaySize + info->var.right_margin + 642 info->var.hsync_len) / 8 - 1; 643 hTotal = (hDisplaySize + info->var.right_margin + 644 info->var.hsync_len + info->var.left_margin) / 8 - 5; 645 hBlankStart = hDisplay; 646 hBlankEnd = hTotal + 4; 647 648 height = info->var.yres_virtual; 649 vDisplay = info->var.yres - 1; 650 vStart = info->var.yres + info->var.lower_margin - 1; 651 vEnd = info->var.yres + info->var.lower_margin + 652 info->var.vsync_len - 1; 653 vTotal = info->var.yres + info->var.lower_margin + 654 info->var.vsync_len + info->var.upper_margin + 2; 655 vBlankStart = vDisplay; 656 vBlankEnd = vTotal + 1; 657 dotClock = 1000000000 / info->var.pixclock; 658 659 memcpy(&newmode, ®_template, sizeof(struct riva_regs)); 660 661 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 662 vTotal |= 1; 663 664 if (par->FlatPanel) { 665 vStart = vTotal - 3; 666 vEnd = vTotal - 2; 667 vBlankStart = vStart; 668 hStart = hTotal - 3; 669 hEnd = hTotal - 2; 670 hBlankEnd = hTotal + 4; 671 } 672 673 newmode.crtc[0x0] = Set8Bits (hTotal); 674 newmode.crtc[0x1] = Set8Bits (hDisplay); 675 newmode.crtc[0x2] = Set8Bits (hBlankStart); 676 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); 677 newmode.crtc[0x4] = Set8Bits (hStart); 678 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) 679 | SetBitField (hEnd, 4: 0, 4:0); 680 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); 681 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) 682 | SetBitField (vDisplay, 8: 8, 1:1) 683 | SetBitField (vStart, 8: 8, 2:2) 684 | SetBitField (vBlankStart, 8: 8, 3:3) 685 | SetBit (4) 686 | SetBitField (vTotal, 9: 9, 5:5) 687 | SetBitField (vDisplay, 9: 9, 6:6) 688 | SetBitField (vStart, 9: 9, 7:7); 689 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) 690 | SetBit (6); 691 newmode.crtc[0x10] = Set8Bits (vStart); 692 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) 693 | SetBit (5); 694 newmode.crtc[0x12] = Set8Bits (vDisplay); 695 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); 696 newmode.crtc[0x15] = Set8Bits (vBlankStart); 697 newmode.crtc[0x16] = Set8Bits (vBlankEnd); 698 699 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) 700 | SetBitField(vBlankStart,10:10,3:3) 701 | SetBitField(vStart,10:10,2:2) 702 | SetBitField(vDisplay,10:10,1:1) 703 | SetBitField(vTotal,10:10,0:0); 704 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) 705 | SetBitField(hDisplay,8:8,1:1) 706 | SetBitField(hBlankStart,8:8,2:2) 707 | SetBitField(hStart,8:8,3:3); 708 newmode.ext.extra = SetBitField(vTotal,11:11,0:0) 709 | SetBitField(vDisplay,11:11,2:2) 710 | SetBitField(vStart,11:11,4:4) 711 | SetBitField(vBlankStart,11:11,6:6); 712 713 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { 714 int tmp = (hTotal >> 1) & ~1; 715 newmode.ext.interlace = Set8Bits(tmp); 716 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); 717 } else 718 newmode.ext.interlace = 0xff; /* interlace off */ 719 720 if (par->riva.Architecture >= NV_ARCH_10) 721 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); 722 723 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 724 newmode.misc_output &= ~0x40; 725 else 726 newmode.misc_output |= 0x40; 727 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 728 newmode.misc_output &= ~0x80; 729 else 730 newmode.misc_output |= 0x80; 731 732 rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width, 733 hDisplaySize, height, dotClock); 734 if (rc) 735 goto out; 736 737 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & 738 0xfff000ff; 739 if (par->FlatPanel == 1) { 740 newmode.ext.pixel |= (1 << 7); 741 newmode.ext.scale |= (1 << 8); 742 } 743 if (par->SecondCRTC) { 744 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & 745 ~0x00001000; 746 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | 747 0x00001000; 748 newmode.ext.crtcOwner = 3; 749 newmode.ext.pllsel |= 0x20000800; 750 newmode.ext.vpll2 = newmode.ext.vpll; 751 } else if (par->riva.twoHeads) { 752 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | 753 0x00001000; 754 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & 755 ~0x00001000; 756 newmode.ext.crtcOwner = 0; 757 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); 758 } 759 if (par->FlatPanel == 1) { 760 newmode.ext.pixel |= (1 << 7); 761 newmode.ext.scale |= (1 << 8); 762 } 763 newmode.ext.cursorConfig = 0x02000100; 764 par->current_state = newmode; 765 riva_load_state(par, &par->current_state); 766 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ 767 768 out: 769 rivafb_blank(FB_BLANK_UNBLANK, info); 770 NVTRACE_LEAVE(); 771 772 return rc; 773 } 774 775 static void riva_update_var(struct fb_var_screeninfo *var, 776 const struct fb_videomode *modedb) 777 { 778 NVTRACE_ENTER(); 779 var->xres = var->xres_virtual = modedb->xres; 780 var->yres = modedb->yres; 781 if (var->yres_virtual < var->yres) 782 var->yres_virtual = var->yres; 783 var->xoffset = var->yoffset = 0; 784 var->pixclock = modedb->pixclock; 785 var->left_margin = modedb->left_margin; 786 var->right_margin = modedb->right_margin; 787 var->upper_margin = modedb->upper_margin; 788 var->lower_margin = modedb->lower_margin; 789 var->hsync_len = modedb->hsync_len; 790 var->vsync_len = modedb->vsync_len; 791 var->sync = modedb->sync; 792 var->vmode = modedb->vmode; 793 NVTRACE_LEAVE(); 794 } 795 796 /** 797 * rivafb_do_maximize - 798 * @info: pointer to fb_info object containing info for current riva board 799 * @var: standard kernel fb changeable data 800 * @nom: nom 801 * @den: den 802 * 803 * DESCRIPTION: 804 * . 805 * 806 * RETURNS: 807 * -EINVAL on failure, 0 on success 808 * 809 * 810 * CALLED FROM: 811 * rivafb_check_var() 812 */ 813 static int rivafb_do_maximize(struct fb_info *info, 814 struct fb_var_screeninfo *var, 815 int nom, int den) 816 { 817 static struct { 818 int xres, yres; 819 } modes[] = { 820 {1600, 1280}, 821 {1280, 1024}, 822 {1024, 768}, 823 {800, 600}, 824 {640, 480}, 825 {-1, -1} 826 }; 827 int i; 828 829 NVTRACE_ENTER(); 830 /* use highest possible virtual resolution */ 831 if (var->xres_virtual == -1 && var->yres_virtual == -1) { 832 printk(KERN_WARNING PFX 833 "using maximum available virtual resolution\n"); 834 for (i = 0; modes[i].xres != -1; i++) { 835 if (modes[i].xres * nom / den * modes[i].yres < 836 info->fix.smem_len) 837 break; 838 } 839 if (modes[i].xres == -1) { 840 printk(KERN_ERR PFX 841 "could not find a virtual resolution that fits into video memory!!\n"); 842 NVTRACE("EXIT - EINVAL error\n"); 843 return -EINVAL; 844 } 845 var->xres_virtual = modes[i].xres; 846 var->yres_virtual = modes[i].yres; 847 848 printk(KERN_INFO PFX 849 "virtual resolution set to maximum of %dx%d\n", 850 var->xres_virtual, var->yres_virtual); 851 } else if (var->xres_virtual == -1) { 852 var->xres_virtual = (info->fix.smem_len * den / 853 (nom * var->yres_virtual)) & ~15; 854 printk(KERN_WARNING PFX 855 "setting virtual X resolution to %d\n", var->xres_virtual); 856 } else if (var->yres_virtual == -1) { 857 var->xres_virtual = (var->xres_virtual + 15) & ~15; 858 var->yres_virtual = info->fix.smem_len * den / 859 (nom * var->xres_virtual); 860 printk(KERN_WARNING PFX 861 "setting virtual Y resolution to %d\n", var->yres_virtual); 862 } else { 863 var->xres_virtual = (var->xres_virtual + 15) & ~15; 864 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { 865 printk(KERN_ERR PFX 866 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", 867 var->xres, var->yres, var->bits_per_pixel); 868 NVTRACE("EXIT - EINVAL error\n"); 869 return -EINVAL; 870 } 871 } 872 873 if (var->xres_virtual * nom / den >= 8192) { 874 printk(KERN_WARNING PFX 875 "virtual X resolution (%d) is too high, lowering to %d\n", 876 var->xres_virtual, 8192 * den / nom - 16); 877 var->xres_virtual = 8192 * den / nom - 16; 878 } 879 880 if (var->xres_virtual < var->xres) { 881 printk(KERN_ERR PFX 882 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); 883 return -EINVAL; 884 } 885 886 if (var->yres_virtual < var->yres) { 887 printk(KERN_ERR PFX 888 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); 889 return -EINVAL; 890 } 891 if (var->yres_virtual > 0x7fff/nom) 892 var->yres_virtual = 0x7fff/nom; 893 if (var->xres_virtual > 0x7fff/nom) 894 var->xres_virtual = 0x7fff/nom; 895 NVTRACE_LEAVE(); 896 return 0; 897 } 898 899 static void 900 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) 901 { 902 RIVA_FIFO_FREE(par->riva, Patt, 4); 903 NV_WR32(&par->riva.Patt->Color0, 0, clr0); 904 NV_WR32(&par->riva.Patt->Color1, 0, clr1); 905 NV_WR32(par->riva.Patt->Monochrome, 0, pat0); 906 NV_WR32(par->riva.Patt->Monochrome, 4, pat1); 907 } 908 909 /* acceleration routines */ 910 static inline void wait_for_idle(struct riva_par *par) 911 { 912 while (par->riva.Busy(&par->riva)); 913 } 914 915 /* 916 * Set ROP. Translate X rop into ROP3. Internal routine. 917 */ 918 static void 919 riva_set_rop_solid(struct riva_par *par, int rop) 920 { 921 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 922 RIVA_FIFO_FREE(par->riva, Rop, 1); 923 NV_WR32(&par->riva.Rop->Rop3, 0, rop); 924 925 } 926 927 static void riva_setup_accel(struct fb_info *info) 928 { 929 struct riva_par *par = info->par; 930 931 RIVA_FIFO_FREE(par->riva, Clip, 2); 932 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); 933 NV_WR32(&par->riva.Clip->WidthHeight, 0, 934 (info->var.xres_virtual & 0xffff) | 935 (info->var.yres_virtual << 16)); 936 riva_set_rop_solid(par, 0xcc); 937 wait_for_idle(par); 938 } 939 940 /** 941 * riva_get_cmap_len - query current color map length 942 * @var: standard kernel fb changeable data 943 * 944 * DESCRIPTION: 945 * Get current color map length. 946 * 947 * RETURNS: 948 * Length of color map 949 * 950 * CALLED FROM: 951 * rivafb_setcolreg() 952 */ 953 static int riva_get_cmap_len(const struct fb_var_screeninfo *var) 954 { 955 int rc = 256; /* reasonable default */ 956 957 switch (var->green.length) { 958 case 8: 959 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ 960 break; 961 case 5: 962 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ 963 break; 964 case 6: 965 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ 966 break; 967 default: 968 /* should not occur */ 969 break; 970 } 971 return rc; 972 } 973 974 /* ------------------------------------------------------------------------- * 975 * 976 * framebuffer operations 977 * 978 * ------------------------------------------------------------------------- */ 979 980 static int rivafb_open(struct fb_info *info, int user) 981 { 982 struct riva_par *par = info->par; 983 984 NVTRACE_ENTER(); 985 mutex_lock(&par->open_lock); 986 if (!par->ref_count) { 987 #ifdef CONFIG_X86 988 memset(&par->state, 0, sizeof(struct vgastate)); 989 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; 990 /* save the DAC for Riva128 */ 991 if (par->riva.Architecture == NV_ARCH_03) 992 par->state.flags |= VGA_SAVE_CMAP; 993 save_vga(&par->state); 994 #endif 995 /* vgaHWunlock() + riva unlock (0x7F) */ 996 CRTCout(par, 0x11, 0xFF); 997 par->riva.LockUnlock(&par->riva, 0); 998 999 riva_save_state(par, &par->initial_state); 1000 } 1001 par->ref_count++; 1002 mutex_unlock(&par->open_lock); 1003 NVTRACE_LEAVE(); 1004 return 0; 1005 } 1006 1007 static int rivafb_release(struct fb_info *info, int user) 1008 { 1009 struct riva_par *par = info->par; 1010 1011 NVTRACE_ENTER(); 1012 mutex_lock(&par->open_lock); 1013 if (!par->ref_count) { 1014 mutex_unlock(&par->open_lock); 1015 return -EINVAL; 1016 } 1017 if (par->ref_count == 1) { 1018 par->riva.LockUnlock(&par->riva, 0); 1019 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); 1020 riva_load_state(par, &par->initial_state); 1021 #ifdef CONFIG_X86 1022 restore_vga(&par->state); 1023 #endif 1024 par->riva.LockUnlock(&par->riva, 1); 1025 } 1026 par->ref_count--; 1027 mutex_unlock(&par->open_lock); 1028 NVTRACE_LEAVE(); 1029 return 0; 1030 } 1031 1032 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 1033 { 1034 const struct fb_videomode *mode; 1035 struct riva_par *par = info->par; 1036 int nom, den; /* translating from pixels->bytes */ 1037 int mode_valid = 0; 1038 1039 NVTRACE_ENTER(); 1040 if (!var->pixclock) 1041 return -EINVAL; 1042 1043 switch (var->bits_per_pixel) { 1044 case 1 ... 8: 1045 var->red.offset = var->green.offset = var->blue.offset = 0; 1046 var->red.length = var->green.length = var->blue.length = 8; 1047 var->bits_per_pixel = 8; 1048 nom = den = 1; 1049 break; 1050 case 9 ... 15: 1051 var->green.length = 5; 1052 fallthrough; 1053 case 16: 1054 var->bits_per_pixel = 16; 1055 /* The Riva128 supports RGB555 only */ 1056 if (par->riva.Architecture == NV_ARCH_03) 1057 var->green.length = 5; 1058 if (var->green.length == 5) { 1059 /* 0rrrrrgg gggbbbbb */ 1060 var->red.offset = 10; 1061 var->green.offset = 5; 1062 var->blue.offset = 0; 1063 var->red.length = 5; 1064 var->green.length = 5; 1065 var->blue.length = 5; 1066 } else { 1067 /* rrrrrggg gggbbbbb */ 1068 var->red.offset = 11; 1069 var->green.offset = 5; 1070 var->blue.offset = 0; 1071 var->red.length = 5; 1072 var->green.length = 6; 1073 var->blue.length = 5; 1074 } 1075 nom = 2; 1076 den = 1; 1077 break; 1078 case 17 ... 32: 1079 var->red.length = var->green.length = var->blue.length = 8; 1080 var->bits_per_pixel = 32; 1081 var->red.offset = 16; 1082 var->green.offset = 8; 1083 var->blue.offset = 0; 1084 nom = 4; 1085 den = 1; 1086 break; 1087 default: 1088 printk(KERN_ERR PFX 1089 "mode %dx%dx%d rejected...color depth not supported.\n", 1090 var->xres, var->yres, var->bits_per_pixel); 1091 NVTRACE("EXIT, returning -EINVAL\n"); 1092 return -EINVAL; 1093 } 1094 1095 if (!strictmode) { 1096 if (!info->monspecs.vfmax || !info->monspecs.hfmax || 1097 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 1098 mode_valid = 1; 1099 } 1100 1101 /* calculate modeline if supported by monitor */ 1102 if (!mode_valid && info->monspecs.gtf) { 1103 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 1104 mode_valid = 1; 1105 } 1106 1107 if (!mode_valid) { 1108 mode = fb_find_best_mode(var, &info->modelist); 1109 if (mode) { 1110 riva_update_var(var, mode); 1111 mode_valid = 1; 1112 } 1113 } 1114 1115 if (!mode_valid && info->monspecs.modedb_len) 1116 return -EINVAL; 1117 1118 if (var->xres_virtual < var->xres) 1119 var->xres_virtual = var->xres; 1120 if (var->yres_virtual <= var->yres) 1121 var->yres_virtual = -1; 1122 if (rivafb_do_maximize(info, var, nom, den) < 0) 1123 return -EINVAL; 1124 1125 /* truncate xoffset and yoffset to maximum if too high */ 1126 if (var->xoffset > var->xres_virtual - var->xres) 1127 var->xoffset = var->xres_virtual - var->xres - 1; 1128 1129 if (var->yoffset > var->yres_virtual - var->yres) 1130 var->yoffset = var->yres_virtual - var->yres - 1; 1131 1132 var->red.msb_right = 1133 var->green.msb_right = 1134 var->blue.msb_right = 1135 var->transp.offset = var->transp.length = var->transp.msb_right = 0; 1136 NVTRACE_LEAVE(); 1137 return 0; 1138 } 1139 1140 static int rivafb_set_par(struct fb_info *info) 1141 { 1142 struct riva_par *par = info->par; 1143 int rc = 0; 1144 1145 NVTRACE_ENTER(); 1146 /* vgaHWunlock() + riva unlock (0x7F) */ 1147 CRTCout(par, 0x11, 0xFF); 1148 par->riva.LockUnlock(&par->riva, 0); 1149 rc = riva_load_video_mode(info); 1150 if (rc) 1151 goto out; 1152 if(!(info->flags & FBINFO_HWACCEL_DISABLED)) 1153 riva_setup_accel(info); 1154 1155 par->cursor_reset = 1; 1156 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); 1157 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1158 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1159 1160 if (info->flags & FBINFO_HWACCEL_DISABLED) 1161 info->pixmap.scan_align = 1; 1162 else 1163 info->pixmap.scan_align = 4; 1164 1165 out: 1166 NVTRACE_LEAVE(); 1167 return rc; 1168 } 1169 1170 /** 1171 * rivafb_pan_display 1172 * @var: standard kernel fb changeable data 1173 * @info: pointer to fb_info object containing info for current riva board 1174 * 1175 * DESCRIPTION: 1176 * Pan (or wrap, depending on the `vmode' field) the display using the 1177 * `xoffset' and `yoffset' fields of the `var' structure. 1178 * If the values don't fit, return -EINVAL. 1179 * 1180 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag 1181 */ 1182 static int rivafb_pan_display(struct fb_var_screeninfo *var, 1183 struct fb_info *info) 1184 { 1185 struct riva_par *par = info->par; 1186 unsigned int base; 1187 1188 NVTRACE_ENTER(); 1189 base = var->yoffset * info->fix.line_length + var->xoffset; 1190 par->riva.SetStartAddress(&par->riva, base); 1191 NVTRACE_LEAVE(); 1192 return 0; 1193 } 1194 1195 static int rivafb_blank(int blank, struct fb_info *info) 1196 { 1197 struct riva_par *par= info->par; 1198 unsigned char tmp, vesa; 1199 1200 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ 1201 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ 1202 1203 NVTRACE_ENTER(); 1204 1205 if (blank) 1206 tmp |= 0x20; 1207 1208 switch (blank) { 1209 case FB_BLANK_UNBLANK: 1210 case FB_BLANK_NORMAL: 1211 break; 1212 case FB_BLANK_VSYNC_SUSPEND: 1213 vesa |= 0x80; 1214 break; 1215 case FB_BLANK_HSYNC_SUSPEND: 1216 vesa |= 0x40; 1217 break; 1218 case FB_BLANK_POWERDOWN: 1219 vesa |= 0xc0; 1220 break; 1221 } 1222 1223 SEQout(par, 0x01, tmp); 1224 CRTCout(par, 0x1a, vesa); 1225 1226 NVTRACE_LEAVE(); 1227 1228 return 0; 1229 } 1230 1231 /** 1232 * rivafb_setcolreg 1233 * @regno: register index 1234 * @red: red component 1235 * @green: green component 1236 * @blue: blue component 1237 * @transp: transparency 1238 * @info: pointer to fb_info object containing info for current riva board 1239 * 1240 * DESCRIPTION: 1241 * Set a single color register. The values supplied have a 16 bit 1242 * magnitude. 1243 * 1244 * RETURNS: 1245 * Return != 0 for invalid regno. 1246 * 1247 * CALLED FROM: 1248 * fbcmap.c:fb_set_cmap() 1249 */ 1250 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, 1251 unsigned blue, unsigned transp, 1252 struct fb_info *info) 1253 { 1254 struct riva_par *par = info->par; 1255 RIVA_HW_INST *chip = &par->riva; 1256 int i; 1257 1258 if (regno >= riva_get_cmap_len(&info->var)) 1259 return -EINVAL; 1260 1261 if (info->var.grayscale) { 1262 /* gray = 0.30*R + 0.59*G + 0.11*B */ 1263 red = green = blue = 1264 (red * 77 + green * 151 + blue * 28) >> 8; 1265 } 1266 1267 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1268 ((u32 *) info->pseudo_palette)[regno] = 1269 (regno << info->var.red.offset) | 1270 (regno << info->var.green.offset) | 1271 (regno << info->var.blue.offset); 1272 /* 1273 * The Riva128 2D engine requires color information in 1274 * TrueColor format even if framebuffer is in DirectColor 1275 */ 1276 if (par->riva.Architecture == NV_ARCH_03) { 1277 switch (info->var.bits_per_pixel) { 1278 case 16: 1279 par->palette[regno] = ((red & 0xf800) >> 1) | 1280 ((green & 0xf800) >> 6) | 1281 ((blue & 0xf800) >> 11); 1282 break; 1283 case 32: 1284 par->palette[regno] = ((red & 0xff00) << 8) | 1285 ((green & 0xff00)) | 1286 ((blue & 0xff00) >> 8); 1287 break; 1288 } 1289 } 1290 } 1291 1292 switch (info->var.bits_per_pixel) { 1293 case 8: 1294 /* "transparent" stuff is completely ignored. */ 1295 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1296 break; 1297 case 16: 1298 if (info->var.green.length == 5) { 1299 for (i = 0; i < 8; i++) { 1300 riva_wclut(chip, regno*8+i, red >> 8, 1301 green >> 8, blue >> 8); 1302 } 1303 } else { 1304 u8 r, g, b; 1305 1306 if (regno < 32) { 1307 for (i = 0; i < 8; i++) { 1308 riva_wclut(chip, regno*8+i, 1309 red >> 8, green >> 8, 1310 blue >> 8); 1311 } 1312 } 1313 riva_rclut(chip, regno*4, &r, &g, &b); 1314 for (i = 0; i < 4; i++) 1315 riva_wclut(chip, regno*4+i, r, 1316 green >> 8, b); 1317 } 1318 break; 1319 case 32: 1320 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1321 break; 1322 default: 1323 /* do nothing */ 1324 break; 1325 } 1326 return 0; 1327 } 1328 1329 /** 1330 * rivafb_fillrect - hardware accelerated color fill function 1331 * @info: pointer to fb_info structure 1332 * @rect: pointer to fb_fillrect structure 1333 * 1334 * DESCRIPTION: 1335 * This function fills up a region of framebuffer memory with a solid 1336 * color with a choice of two different ROP's, copy or invert. 1337 * 1338 * CALLED FROM: 1339 * framebuffer hook 1340 */ 1341 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 1342 { 1343 struct riva_par *par = info->par; 1344 u_int color, rop = 0; 1345 1346 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1347 cfb_fillrect(info, rect); 1348 return; 1349 } 1350 1351 if (info->var.bits_per_pixel == 8) 1352 color = rect->color; 1353 else { 1354 if (par->riva.Architecture != NV_ARCH_03) 1355 color = ((u32 *)info->pseudo_palette)[rect->color]; 1356 else 1357 color = par->palette[rect->color]; 1358 } 1359 1360 switch (rect->rop) { 1361 case ROP_XOR: 1362 rop = 0x66; 1363 break; 1364 case ROP_COPY: 1365 default: 1366 rop = 0xCC; 1367 break; 1368 } 1369 1370 riva_set_rop_solid(par, rop); 1371 1372 RIVA_FIFO_FREE(par->riva, Bitmap, 1); 1373 NV_WR32(&par->riva.Bitmap->Color1A, 0, color); 1374 1375 RIVA_FIFO_FREE(par->riva, Bitmap, 2); 1376 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, 1377 (rect->dx << 16) | rect->dy); 1378 mb(); 1379 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, 1380 (rect->width << 16) | rect->height); 1381 mb(); 1382 riva_set_rop_solid(par, 0xcc); 1383 1384 } 1385 1386 /** 1387 * rivafb_copyarea - hardware accelerated blit function 1388 * @info: pointer to fb_info structure 1389 * @region: pointer to fb_copyarea structure 1390 * 1391 * DESCRIPTION: 1392 * This copies an area of pixels from one location to another 1393 * 1394 * CALLED FROM: 1395 * framebuffer hook 1396 */ 1397 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 1398 { 1399 struct riva_par *par = info->par; 1400 1401 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1402 cfb_copyarea(info, region); 1403 return; 1404 } 1405 1406 RIVA_FIFO_FREE(par->riva, Blt, 3); 1407 NV_WR32(&par->riva.Blt->TopLeftSrc, 0, 1408 (region->sy << 16) | region->sx); 1409 NV_WR32(&par->riva.Blt->TopLeftDst, 0, 1410 (region->dy << 16) | region->dx); 1411 mb(); 1412 NV_WR32(&par->riva.Blt->WidthHeight, 0, 1413 (region->height << 16) | region->width); 1414 mb(); 1415 } 1416 1417 static inline void convert_bgcolor_16(u32 *col) 1418 { 1419 *col = ((*col & 0x0000F800) << 8) 1420 | ((*col & 0x00007E0) << 5) 1421 | ((*col & 0x0000001F) << 3) 1422 | 0xFF000000; 1423 mb(); 1424 } 1425 1426 /** 1427 * rivafb_imageblit: hardware accelerated color expand function 1428 * @info: pointer to fb_info structure 1429 * @image: pointer to fb_image structure 1430 * 1431 * DESCRIPTION: 1432 * If the source is a monochrome bitmap, the function fills up a a region 1433 * of framebuffer memory with pixels whose color is determined by the bit 1434 * setting of the bitmap, 1 - foreground, 0 - background. 1435 * 1436 * If the source is not a monochrome bitmap, color expansion is not done. 1437 * In this case, it is channeled to a software function. 1438 * 1439 * CALLED FROM: 1440 * framebuffer hook 1441 */ 1442 static void rivafb_imageblit(struct fb_info *info, 1443 const struct fb_image *image) 1444 { 1445 struct riva_par *par = info->par; 1446 u32 fgx = 0, bgx = 0, width, tmp; 1447 u8 *cdat = (u8 *) image->data; 1448 volatile u32 __iomem *d; 1449 int i, size; 1450 1451 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { 1452 cfb_imageblit(info, image); 1453 return; 1454 } 1455 1456 switch (info->var.bits_per_pixel) { 1457 case 8: 1458 fgx = image->fg_color; 1459 bgx = image->bg_color; 1460 break; 1461 case 16: 1462 case 32: 1463 if (par->riva.Architecture != NV_ARCH_03) { 1464 fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; 1465 bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; 1466 } else { 1467 fgx = par->palette[image->fg_color]; 1468 bgx = par->palette[image->bg_color]; 1469 } 1470 if (info->var.green.length == 6) 1471 convert_bgcolor_16(&bgx); 1472 break; 1473 } 1474 1475 RIVA_FIFO_FREE(par->riva, Bitmap, 7); 1476 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, 1477 (image->dy << 16) | (image->dx & 0xFFFF)); 1478 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, 1479 (((image->dy + image->height) << 16) | 1480 ((image->dx + image->width) & 0xffff))); 1481 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); 1482 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); 1483 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, 1484 (image->height << 16) | ((image->width + 31) & ~31)); 1485 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, 1486 (image->height << 16) | ((image->width + 31) & ~31)); 1487 NV_WR32(&par->riva.Bitmap->PointE, 0, 1488 (image->dy << 16) | (image->dx & 0xFFFF)); 1489 1490 d = &par->riva.Bitmap->MonochromeData01E; 1491 1492 width = (image->width + 31)/32; 1493 size = width * image->height; 1494 while (size >= 16) { 1495 RIVA_FIFO_FREE(par->riva, Bitmap, 16); 1496 for (i = 0; i < 16; i++) { 1497 tmp = *((u32 *)cdat); 1498 cdat = (u8 *)((u32 *)cdat + 1); 1499 reverse_order(&tmp); 1500 NV_WR32(d, i*4, tmp); 1501 } 1502 size -= 16; 1503 } 1504 if (size) { 1505 RIVA_FIFO_FREE(par->riva, Bitmap, size); 1506 for (i = 0; i < size; i++) { 1507 tmp = *((u32 *) cdat); 1508 cdat = (u8 *)((u32 *)cdat + 1); 1509 reverse_order(&tmp); 1510 NV_WR32(d, i*4, tmp); 1511 } 1512 } 1513 } 1514 1515 /** 1516 * rivafb_cursor - hardware cursor function 1517 * @info: pointer to info structure 1518 * @cursor: pointer to fbcursor structure 1519 * 1520 * DESCRIPTION: 1521 * A cursor function that supports displaying a cursor image via hardware. 1522 * Within the kernel, copy and invert rops are supported. If exported 1523 * to user space, only the copy rop will be supported. 1524 * 1525 * CALLED FROM 1526 * framebuffer hook 1527 */ 1528 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1529 { 1530 struct riva_par *par = info->par; 1531 u8 data[MAX_CURS * MAX_CURS/8]; 1532 int i, set = cursor->set; 1533 u16 fg, bg; 1534 1535 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 1536 return -ENXIO; 1537 1538 par->riva.ShowHideCursor(&par->riva, 0); 1539 1540 if (par->cursor_reset) { 1541 set = FB_CUR_SETALL; 1542 par->cursor_reset = 0; 1543 } 1544 1545 if (set & FB_CUR_SETSIZE) 1546 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); 1547 1548 if (set & FB_CUR_SETPOS) { 1549 u32 xx, yy, temp; 1550 1551 yy = cursor->image.dy - info->var.yoffset; 1552 xx = cursor->image.dx - info->var.xoffset; 1553 temp = xx & 0xFFFF; 1554 temp |= yy << 16; 1555 1556 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); 1557 } 1558 1559 1560 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 1561 u32 bg_idx = cursor->image.bg_color; 1562 u32 fg_idx = cursor->image.fg_color; 1563 u32 s_pitch = (cursor->image.width+7) >> 3; 1564 u32 d_pitch = MAX_CURS/8; 1565 u8 *dat = (u8 *) cursor->image.data; 1566 u8 *msk = (u8 *) cursor->mask; 1567 u8 *src; 1568 1569 src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC); 1570 1571 if (src) { 1572 switch (cursor->rop) { 1573 case ROP_XOR: 1574 for (i = 0; i < s_pitch * cursor->image.height; i++) 1575 src[i] = dat[i] ^ msk[i]; 1576 break; 1577 case ROP_COPY: 1578 default: 1579 for (i = 0; i < s_pitch * cursor->image.height; i++) 1580 src[i] = dat[i] & msk[i]; 1581 break; 1582 } 1583 1584 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 1585 cursor->image.height); 1586 1587 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 1588 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 1589 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1590 1 << 15; 1591 1592 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 1593 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 1594 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1595 1 << 15; 1596 1597 par->riva.LockUnlock(&par->riva, 0); 1598 1599 rivafb_load_cursor_image(par, data, bg, fg, 1600 cursor->image.width, 1601 cursor->image.height); 1602 kfree(src); 1603 } 1604 } 1605 1606 if (cursor->enable) 1607 par->riva.ShowHideCursor(&par->riva, 1); 1608 1609 return 0; 1610 } 1611 1612 static int rivafb_sync(struct fb_info *info) 1613 { 1614 struct riva_par *par = info->par; 1615 1616 wait_for_idle(par); 1617 return 0; 1618 } 1619 1620 /* ------------------------------------------------------------------------- * 1621 * 1622 * initialization helper functions 1623 * 1624 * ------------------------------------------------------------------------- */ 1625 1626 /* kernel interface */ 1627 static const struct fb_ops riva_fb_ops = { 1628 .owner = THIS_MODULE, 1629 .fb_open = rivafb_open, 1630 .fb_release = rivafb_release, 1631 __FB_DEFAULT_IOMEM_OPS_RDWR, 1632 .fb_check_var = rivafb_check_var, 1633 .fb_set_par = rivafb_set_par, 1634 .fb_setcolreg = rivafb_setcolreg, 1635 .fb_pan_display = rivafb_pan_display, 1636 .fb_blank = rivafb_blank, 1637 .fb_fillrect = rivafb_fillrect, 1638 .fb_copyarea = rivafb_copyarea, 1639 .fb_imageblit = rivafb_imageblit, 1640 .fb_cursor = rivafb_cursor, 1641 .fb_sync = rivafb_sync, 1642 __FB_DEFAULT_IOMEM_OPS_MMAP, 1643 }; 1644 1645 static int riva_set_fbinfo(struct fb_info *info) 1646 { 1647 unsigned int cmap_len; 1648 struct riva_par *par = info->par; 1649 1650 NVTRACE_ENTER(); 1651 info->flags = FBINFO_HWACCEL_XPAN 1652 | FBINFO_HWACCEL_YPAN 1653 | FBINFO_HWACCEL_COPYAREA 1654 | FBINFO_HWACCEL_FILLRECT 1655 | FBINFO_HWACCEL_IMAGEBLIT; 1656 1657 /* Accel seems to not work properly on NV30 yet...*/ 1658 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { 1659 printk(KERN_DEBUG PFX "disabling acceleration\n"); 1660 info->flags |= FBINFO_HWACCEL_DISABLED; 1661 } 1662 1663 info->var = rivafb_default_var; 1664 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1665 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1666 1667 info->pseudo_palette = par->pseudo_palette; 1668 1669 cmap_len = riva_get_cmap_len(&info->var); 1670 fb_alloc_cmap(&info->cmap, cmap_len, 0); 1671 1672 info->pixmap.size = 8 * 1024; 1673 info->pixmap.buf_align = 4; 1674 info->pixmap.access_align = 32; 1675 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1676 info->var.yres_virtual = -1; 1677 NVTRACE_LEAVE(); 1678 return (rivafb_check_var(&info->var, info)); 1679 } 1680 1681 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) 1682 { 1683 struct riva_par *par = info->par; 1684 struct device_node *dp; 1685 const unsigned char *pedid = NULL; 1686 const unsigned char *disptype = NULL; 1687 static char *propnames[] = { 1688 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; 1689 int i; 1690 1691 NVTRACE_ENTER(); 1692 dp = pci_device_to_OF_node(pd); 1693 for (; dp != NULL; dp = dp->child) { 1694 disptype = of_get_property(dp, "display-type", NULL); 1695 if (disptype == NULL) 1696 continue; 1697 if (strncmp(disptype, "LCD", 3) != 0) 1698 continue; 1699 for (i = 0; propnames[i] != NULL; ++i) { 1700 pedid = of_get_property(dp, propnames[i], NULL); 1701 if (pedid != NULL) { 1702 par->EDID = (unsigned char *)pedid; 1703 NVTRACE("LCD found.\n"); 1704 return 1; 1705 } 1706 } 1707 } 1708 NVTRACE_LEAVE(); 1709 return 0; 1710 } 1711 1712 #if defined(CONFIG_FB_RIVA_I2C) 1713 static int riva_get_EDID_i2c(struct fb_info *info) 1714 { 1715 struct riva_par *par = info->par; 1716 struct fb_var_screeninfo var; 1717 int i; 1718 1719 NVTRACE_ENTER(); 1720 par->riva.LockUnlock(&par->riva, 0); 1721 riva_create_i2c_busses(par); 1722 for (i = 0; i < 3; i++) { 1723 if (!par->chan[i].par) 1724 continue; 1725 riva_probe_i2c_connector(par, i, &par->EDID); 1726 if (par->EDID && !fb_parse_edid(par->EDID, &var)) { 1727 printk(PFX "Found EDID Block from BUS %i\n", i); 1728 break; 1729 } 1730 } 1731 1732 NVTRACE_LEAVE(); 1733 return (par->EDID) ? 1 : 0; 1734 } 1735 #endif /* CONFIG_FB_RIVA_I2C */ 1736 1737 static void riva_update_default_var(struct fb_var_screeninfo *var, 1738 struct fb_info *info) 1739 { 1740 struct fb_monspecs *specs = &info->monspecs; 1741 struct fb_videomode modedb; 1742 1743 NVTRACE_ENTER(); 1744 /* respect mode options */ 1745 if (mode_option) { 1746 fb_find_mode(var, info, mode_option, 1747 specs->modedb, specs->modedb_len, 1748 NULL, 8); 1749 } else if (specs->modedb != NULL) { 1750 /* get first mode in database as fallback */ 1751 modedb = specs->modedb[0]; 1752 /* get preferred timing */ 1753 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { 1754 int i; 1755 1756 for (i = 0; i < specs->modedb_len; i++) { 1757 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { 1758 modedb = specs->modedb[i]; 1759 break; 1760 } 1761 } 1762 } 1763 var->bits_per_pixel = 8; 1764 riva_update_var(var, &modedb); 1765 } 1766 NVTRACE_LEAVE(); 1767 } 1768 1769 1770 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) 1771 { 1772 NVTRACE_ENTER(); 1773 if (riva_get_EDID_OF(info, pdev)) { 1774 NVTRACE_LEAVE(); 1775 return; 1776 } 1777 if (IS_ENABLED(CONFIG_OF)) 1778 printk(PFX "could not retrieve EDID from OF\n"); 1779 #if defined(CONFIG_FB_RIVA_I2C) 1780 if (!riva_get_EDID_i2c(info)) 1781 printk(PFX "could not retrieve EDID from DDC/I2C\n"); 1782 #endif 1783 NVTRACE_LEAVE(); 1784 } 1785 1786 1787 static void riva_get_edidinfo(struct fb_info *info) 1788 { 1789 struct fb_var_screeninfo *var = &rivafb_default_var; 1790 struct riva_par *par = info->par; 1791 1792 fb_edid_to_monspecs(par->EDID, &info->monspecs); 1793 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, 1794 &info->modelist); 1795 riva_update_default_var(var, info); 1796 1797 /* if user specified flatpanel, we respect that */ 1798 if (info->monspecs.input & FB_DISP_DDI) 1799 par->FlatPanel = 1; 1800 } 1801 1802 /* ------------------------------------------------------------------------- * 1803 * 1804 * PCI bus 1805 * 1806 * ------------------------------------------------------------------------- */ 1807 1808 static u32 riva_get_arch(struct pci_dev *pd) 1809 { 1810 u32 arch = 0; 1811 1812 switch (pd->device & 0x0ff0) { 1813 case 0x0100: /* GeForce 256 */ 1814 case 0x0110: /* GeForce2 MX */ 1815 case 0x0150: /* GeForce2 */ 1816 case 0x0170: /* GeForce4 MX */ 1817 case 0x0180: /* GeForce4 MX (8x AGP) */ 1818 case 0x01A0: /* nForce */ 1819 case 0x01F0: /* nForce2 */ 1820 arch = NV_ARCH_10; 1821 break; 1822 case 0x0200: /* GeForce3 */ 1823 case 0x0250: /* GeForce4 Ti */ 1824 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1825 arch = NV_ARCH_20; 1826 break; 1827 case 0x0300: /* GeForceFX 5800 */ 1828 case 0x0310: /* GeForceFX 5600 */ 1829 case 0x0320: /* GeForceFX 5200 */ 1830 case 0x0330: /* GeForceFX 5900 */ 1831 case 0x0340: /* GeForceFX 5700 */ 1832 arch = NV_ARCH_30; 1833 break; 1834 case 0x0020: /* TNT, TNT2 */ 1835 arch = NV_ARCH_04; 1836 break; 1837 case 0x0010: /* Riva128 */ 1838 arch = NV_ARCH_03; 1839 break; 1840 default: /* unknown architecture */ 1841 break; 1842 } 1843 return arch; 1844 } 1845 1846 static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) 1847 { 1848 struct riva_par *default_par; 1849 struct fb_info *info; 1850 int ret; 1851 1852 NVTRACE_ENTER(); 1853 assert(pd != NULL); 1854 1855 ret = aperture_remove_conflicting_pci_devices(pd, "rivafb"); 1856 if (ret) 1857 return ret; 1858 1859 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); 1860 if (!info) { 1861 ret = -ENOMEM; 1862 goto err_ret; 1863 } 1864 default_par = info->par; 1865 default_par->pdev = pd; 1866 1867 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1868 if (info->pixmap.addr == NULL) { 1869 ret = -ENOMEM; 1870 goto err_framebuffer_release; 1871 } 1872 1873 ret = pci_enable_device(pd); 1874 if (ret < 0) { 1875 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1876 goto err_free_pixmap; 1877 } 1878 1879 ret = pci_request_regions(pd, "rivafb"); 1880 if (ret < 0) { 1881 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1882 goto err_disable_device; 1883 } 1884 1885 mutex_init(&default_par->open_lock); 1886 default_par->riva.Architecture = riva_get_arch(pd); 1887 1888 default_par->Chipset = (pd->vendor << 16) | pd->device; 1889 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); 1890 1891 if(default_par->riva.Architecture == 0) { 1892 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1893 ret=-ENODEV; 1894 goto err_release_region; 1895 } 1896 if(default_par->riva.Architecture == NV_ARCH_10 || 1897 default_par->riva.Architecture == NV_ARCH_20 || 1898 default_par->riva.Architecture == NV_ARCH_30) { 1899 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1900 } else { 1901 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); 1902 } 1903 1904 default_par->FlatPanel = flatpanel; 1905 if (flatpanel == 1) 1906 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1907 default_par->forceCRTC = forceCRTC; 1908 1909 rivafb_fix.mmio_len = pci_resource_len(pd, 0); 1910 rivafb_fix.smem_len = pci_resource_len(pd, 1); 1911 1912 { 1913 /* enable IO and mem if not already done */ 1914 unsigned short cmd; 1915 1916 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1917 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1918 pci_write_config_word(pd, PCI_COMMAND, cmd); 1919 } 1920 1921 rivafb_fix.mmio_start = pci_resource_start(pd, 0); 1922 rivafb_fix.smem_start = pci_resource_start(pd, 1); 1923 1924 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, 1925 rivafb_fix.mmio_len); 1926 if (!default_par->ctrl_base) { 1927 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1928 ret = -EIO; 1929 goto err_release_region; 1930 } 1931 1932 switch (default_par->riva.Architecture) { 1933 case NV_ARCH_03: 1934 /* Riva128's PRAMIN is in the "framebuffer" space 1935 * Since these cards were never made with more than 8 megabytes 1936 * we can safely allocate this separately. 1937 */ 1938 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); 1939 if (!default_par->riva.PRAMIN) { 1940 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); 1941 ret = -EIO; 1942 goto err_iounmap_ctrl_base; 1943 } 1944 break; 1945 case NV_ARCH_04: 1946 case NV_ARCH_10: 1947 case NV_ARCH_20: 1948 case NV_ARCH_30: 1949 default_par->riva.PCRTC0 = 1950 (u32 __iomem *)(default_par->ctrl_base + 0x00600000); 1951 default_par->riva.PRAMIN = 1952 (u32 __iomem *)(default_par->ctrl_base + 0x00710000); 1953 break; 1954 } 1955 riva_common_setup(default_par); 1956 1957 if (default_par->riva.Architecture == NV_ARCH_03) { 1958 default_par->riva.PCRTC = default_par->riva.PCRTC0 1959 = default_par->riva.PGRAPH; 1960 } 1961 1962 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; 1963 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; 1964 info->screen_base = ioremap_wc(rivafb_fix.smem_start, 1965 rivafb_fix.smem_len); 1966 if (!info->screen_base) { 1967 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 1968 ret = -EIO; 1969 goto err_iounmap_pramin; 1970 } 1971 1972 if (!nomtrr) 1973 default_par->wc_cookie = 1974 arch_phys_wc_add(rivafb_fix.smem_start, 1975 rivafb_fix.smem_len); 1976 1977 info->fbops = &riva_fb_ops; 1978 info->fix = rivafb_fix; 1979 riva_get_EDID(info, pd); 1980 riva_get_edidinfo(info); 1981 1982 ret=riva_set_fbinfo(info); 1983 if (ret < 0) { 1984 printk(KERN_ERR PFX "error setting initial video mode\n"); 1985 goto err_iounmap_screen_base; 1986 } 1987 1988 fb_destroy_modedb(info->monspecs.modedb); 1989 info->monspecs.modedb = NULL; 1990 1991 pci_set_drvdata(pd, info); 1992 1993 ret = register_framebuffer(info); 1994 if (ret < 0) { 1995 printk(KERN_ERR PFX 1996 "error registering riva framebuffer\n"); 1997 goto err_iounmap_screen_base; 1998 } 1999 2000 if (backlight) 2001 riva_bl_init(info->par); 2002 2003 printk(KERN_INFO PFX 2004 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", 2005 info->fix.id, 2006 RIVAFB_VERSION, 2007 info->fix.smem_len / (1024 * 1024), 2008 info->fix.smem_start); 2009 2010 NVTRACE_LEAVE(); 2011 return 0; 2012 2013 err_iounmap_screen_base: 2014 #ifdef CONFIG_FB_RIVA_I2C 2015 riva_delete_i2c_busses(info->par); 2016 #endif 2017 iounmap(info->screen_base); 2018 err_iounmap_pramin: 2019 if (default_par->riva.Architecture == NV_ARCH_03) 2020 iounmap(default_par->riva.PRAMIN); 2021 err_iounmap_ctrl_base: 2022 iounmap(default_par->ctrl_base); 2023 err_release_region: 2024 pci_release_regions(pd); 2025 err_disable_device: 2026 err_free_pixmap: 2027 kfree(info->pixmap.addr); 2028 err_framebuffer_release: 2029 framebuffer_release(info); 2030 err_ret: 2031 return ret; 2032 } 2033 2034 static void rivafb_remove(struct pci_dev *pd) 2035 { 2036 struct fb_info *info = pci_get_drvdata(pd); 2037 struct riva_par *par = info->par; 2038 2039 NVTRACE_ENTER(); 2040 2041 #ifdef CONFIG_FB_RIVA_I2C 2042 riva_delete_i2c_busses(par); 2043 kfree(par->EDID); 2044 #endif 2045 2046 riva_bl_exit(info); 2047 unregister_framebuffer(info); 2048 2049 arch_phys_wc_del(par->wc_cookie); 2050 iounmap(par->ctrl_base); 2051 iounmap(info->screen_base); 2052 if (par->riva.Architecture == NV_ARCH_03) 2053 iounmap(par->riva.PRAMIN); 2054 pci_release_regions(pd); 2055 kfree(info->pixmap.addr); 2056 framebuffer_release(info); 2057 NVTRACE_LEAVE(); 2058 } 2059 2060 /* ------------------------------------------------------------------------- * 2061 * 2062 * initialization 2063 * 2064 * ------------------------------------------------------------------------- */ 2065 2066 #ifndef MODULE 2067 static int rivafb_setup(char *options) 2068 { 2069 char *this_opt; 2070 2071 NVTRACE_ENTER(); 2072 if (!options || !*options) 2073 return 0; 2074 2075 while ((this_opt = strsep(&options, ",")) != NULL) { 2076 if (!strncmp(this_opt, "forceCRTC", 9)) { 2077 char *p; 2078 2079 p = this_opt + 9; 2080 if (!*p || !*(++p)) continue; 2081 forceCRTC = *p - '0'; 2082 if (forceCRTC < 0 || forceCRTC > 1) 2083 forceCRTC = -1; 2084 } else if (!strncmp(this_opt, "flatpanel", 9)) { 2085 flatpanel = 1; 2086 } else if (!strncmp(this_opt, "backlight:", 10)) { 2087 backlight = simple_strtoul(this_opt+10, NULL, 0); 2088 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2089 nomtrr = 1; 2090 } else if (!strncmp(this_opt, "strictmode", 10)) { 2091 strictmode = 1; 2092 } else if (!strncmp(this_opt, "noaccel", 7)) { 2093 noaccel = 1; 2094 } else 2095 mode_option = this_opt; 2096 } 2097 NVTRACE_LEAVE(); 2098 return 0; 2099 } 2100 #endif /* !MODULE */ 2101 2102 static struct pci_driver rivafb_driver = { 2103 .name = "rivafb", 2104 .id_table = rivafb_pci_tbl, 2105 .probe = rivafb_probe, 2106 .remove = rivafb_remove, 2107 }; 2108 2109 2110 2111 /* ------------------------------------------------------------------------- * 2112 * 2113 * modularization 2114 * 2115 * ------------------------------------------------------------------------- */ 2116 2117 static int rivafb_init(void) 2118 { 2119 #ifndef MODULE 2120 char *option = NULL; 2121 #endif 2122 2123 if (fb_modesetting_disabled("rivafb")) 2124 return -ENODEV; 2125 2126 #ifndef MODULE 2127 if (fb_get_options("rivafb", &option)) 2128 return -ENODEV; 2129 rivafb_setup(option); 2130 #endif 2131 return pci_register_driver(&rivafb_driver); 2132 } 2133 2134 2135 module_init(rivafb_init); 2136 2137 static void __exit rivafb_exit(void) 2138 { 2139 pci_unregister_driver(&rivafb_driver); 2140 } 2141 2142 module_exit(rivafb_exit); 2143 2144 module_param(noaccel, bool, 0); 2145 MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2146 module_param(flatpanel, int, 0); 2147 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); 2148 module_param(forceCRTC, int, 0); 2149 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); 2150 module_param(nomtrr, bool, 0); 2151 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); 2152 module_param(strictmode, bool, 0); 2153 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); 2154 2155 MODULE_AUTHOR("Ani Joshi, maintainer"); 2156 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); 2157 MODULE_LICENSE("GPL"); 2158