1 /* 2 * linux/drivers/video/pxafb.c 3 * 4 * Copyright (C) 1999 Eric A. Thomas. 5 * Copyright (C) 2004 Jean-Frederic Clere. 6 * Copyright (C) 2004 Ian Campbell. 7 * Copyright (C) 2004 Jeff Lackey. 8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas 9 * which in turn is 10 * Based on acornfb.c Copyright (C) Russell King. 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file COPYING in the main directory of this archive for 14 * more details. 15 * 16 * Intel PXA250/210 LCD Controller Frame Buffer Driver 17 * 18 * Please direct your questions and comments on this driver to the following 19 * email address: 20 * 21 * linux-arm-kernel@lists.arm.linux.org.uk 22 * 23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c: 24 * 25 * Copyright (C) 2004, Intel Corporation 26 * 27 * 2003/08/27: <yu.tang@intel.com> 28 * 2004/03/10: <stanley.cai@intel.com> 29 * 2004/10/28: <yan.yin@intel.com> 30 * 31 * Copyright (C) 2006-2008 Marvell International Ltd. 32 * All Rights Reserved 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/kernel.h> 38 #include <linux/sched.h> 39 #include <linux/errno.h> 40 #include <linux/string.h> 41 #include <linux/interrupt.h> 42 #include <linux/slab.h> 43 #include <linux/mm.h> 44 #include <linux/fb.h> 45 #include <linux/delay.h> 46 #include <linux/init.h> 47 #include <linux/ioport.h> 48 #include <linux/cpufreq.h> 49 #include <linux/platform_device.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/clk.h> 52 #include <linux/err.h> 53 #include <linux/completion.h> 54 #include <linux/mutex.h> 55 #include <linux/kthread.h> 56 #include <linux/freezer.h> 57 #include <linux/console.h> 58 #include <linux/of_graph.h> 59 #include <linux/regulator/consumer.h> 60 #include <linux/soc/pxa/cpu.h> 61 #include <video/of_display_timing.h> 62 #include <video/videomode.h> 63 64 #include <asm/io.h> 65 #include <asm/irq.h> 66 #include <asm/div64.h> 67 #include <linux/platform_data/video-pxafb.h> 68 69 /* 70 * Complain if VAR is out of range. 71 */ 72 #define DEBUG_VAR 1 73 74 #include "pxafb.h" 75 #include "pxa3xx-regs.h" 76 77 /* Bits which should not be set in machine configuration structures */ 78 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\ 79 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\ 80 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) 81 82 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ 83 LCCR3_PCD | LCCR3_BPP(0xf)) 84 85 static int pxafb_activate_var(struct fb_var_screeninfo *var, 86 struct pxafb_info *); 87 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); 88 static void setup_base_frame(struct pxafb_info *fbi, 89 struct fb_var_screeninfo *var, int branch); 90 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, 91 unsigned long offset, size_t size); 92 93 static unsigned long video_mem_size = 0; 94 95 static inline unsigned long 96 lcd_readl(struct pxafb_info *fbi, unsigned int off) 97 { 98 return __raw_readl(fbi->mmio_base + off); 99 } 100 101 static inline void 102 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val) 103 { 104 __raw_writel(val, fbi->mmio_base + off); 105 } 106 107 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) 108 { 109 unsigned long flags; 110 111 local_irq_save(flags); 112 /* 113 * We need to handle two requests being made at the same time. 114 * There are two important cases: 115 * 1. When we are changing VT (C_REENABLE) while unblanking 116 * (C_ENABLE) We must perform the unblanking, which will 117 * do our REENABLE for us. 118 * 2. When we are blanking, but immediately unblank before 119 * we have blanked. We do the "REENABLE" thing here as 120 * well, just to be sure. 121 */ 122 if (fbi->task_state == C_ENABLE && state == C_REENABLE) 123 state = (u_int) -1; 124 if (fbi->task_state == C_DISABLE && state == C_ENABLE) 125 state = C_REENABLE; 126 127 if (state != (u_int)-1) { 128 fbi->task_state = state; 129 schedule_work(&fbi->task); 130 } 131 local_irq_restore(flags); 132 } 133 134 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 135 { 136 chan &= 0xffff; 137 chan >>= 16 - bf->length; 138 return chan << bf->offset; 139 } 140 141 static int 142 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, 143 u_int trans, struct fb_info *info) 144 { 145 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 146 u_int val; 147 148 if (regno >= fbi->palette_size) 149 return 1; 150 151 if (fbi->fb.var.grayscale) { 152 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff); 153 return 0; 154 } 155 156 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) { 157 case LCCR4_PAL_FOR_0: 158 val = ((red >> 0) & 0xf800); 159 val |= ((green >> 5) & 0x07e0); 160 val |= ((blue >> 11) & 0x001f); 161 fbi->palette_cpu[regno] = val; 162 break; 163 case LCCR4_PAL_FOR_1: 164 val = ((red << 8) & 0x00f80000); 165 val |= ((green >> 0) & 0x0000fc00); 166 val |= ((blue >> 8) & 0x000000f8); 167 ((u32 *)(fbi->palette_cpu))[regno] = val; 168 break; 169 case LCCR4_PAL_FOR_2: 170 val = ((red << 8) & 0x00fc0000); 171 val |= ((green >> 0) & 0x0000fc00); 172 val |= ((blue >> 8) & 0x000000fc); 173 ((u32 *)(fbi->palette_cpu))[regno] = val; 174 break; 175 case LCCR4_PAL_FOR_3: 176 val = ((red << 8) & 0x00ff0000); 177 val |= ((green >> 0) & 0x0000ff00); 178 val |= ((blue >> 8) & 0x000000ff); 179 ((u32 *)(fbi->palette_cpu))[regno] = val; 180 break; 181 } 182 183 return 0; 184 } 185 186 static int 187 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 188 u_int trans, struct fb_info *info) 189 { 190 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 191 unsigned int val; 192 int ret = 1; 193 194 /* 195 * If inverse mode was selected, invert all the colours 196 * rather than the register number. The register number 197 * is what you poke into the framebuffer to produce the 198 * colour you requested. 199 */ 200 if (fbi->cmap_inverse) { 201 red = 0xffff - red; 202 green = 0xffff - green; 203 blue = 0xffff - blue; 204 } 205 206 /* 207 * If greyscale is true, then we convert the RGB value 208 * to greyscale no matter what visual we are using. 209 */ 210 if (fbi->fb.var.grayscale) 211 red = green = blue = (19595 * red + 38470 * green + 212 7471 * blue) >> 16; 213 214 switch (fbi->fb.fix.visual) { 215 case FB_VISUAL_TRUECOLOR: 216 /* 217 * 16-bit True Colour. We encode the RGB value 218 * according to the RGB bitfield information. 219 */ 220 if (regno < 16) { 221 u32 *pal = fbi->fb.pseudo_palette; 222 223 val = chan_to_field(red, &fbi->fb.var.red); 224 val |= chan_to_field(green, &fbi->fb.var.green); 225 val |= chan_to_field(blue, &fbi->fb.var.blue); 226 227 pal[regno] = val; 228 ret = 0; 229 } 230 break; 231 232 case FB_VISUAL_STATIC_PSEUDOCOLOR: 233 case FB_VISUAL_PSEUDOCOLOR: 234 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); 235 break; 236 } 237 238 return ret; 239 } 240 241 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */ 242 static inline int var_to_depth(struct fb_var_screeninfo *var) 243 { 244 return var->red.length + var->green.length + 245 var->blue.length + var->transp.length; 246 } 247 248 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */ 249 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var) 250 { 251 int bpp = -EINVAL; 252 253 switch (var->bits_per_pixel) { 254 case 1: bpp = 0; break; 255 case 2: bpp = 1; break; 256 case 4: bpp = 2; break; 257 case 8: bpp = 3; break; 258 case 16: bpp = 4; break; 259 case 24: 260 switch (var_to_depth(var)) { 261 case 18: bpp = 6; break; /* 18-bits/pixel packed */ 262 case 19: bpp = 8; break; /* 19-bits/pixel packed */ 263 case 24: bpp = 9; break; 264 } 265 break; 266 case 32: 267 switch (var_to_depth(var)) { 268 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */ 269 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */ 270 case 25: bpp = 10; break; 271 } 272 break; 273 } 274 return bpp; 275 } 276 277 /* 278 * pxafb_var_to_lccr3(): 279 * Convert a bits per pixel value to the correct bit pattern for LCCR3 280 * 281 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an 282 * implication of the acutal use of transparency bit, which we handle it 283 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel 284 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP. 285 * 286 * Transparency for palette pixel formats is not supported at the moment. 287 */ 288 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var) 289 { 290 int bpp = pxafb_var_to_bpp(var); 291 uint32_t lccr3; 292 293 if (bpp < 0) 294 return 0; 295 296 lccr3 = LCCR3_BPP(bpp); 297 298 switch (var_to_depth(var)) { 299 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break; 300 case 18: lccr3 |= LCCR3_PDFOR_3; break; 301 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3; 302 break; 303 case 19: 304 case 25: lccr3 |= LCCR3_PDFOR_0; break; 305 } 306 return lccr3; 307 } 308 309 #define SET_PIXFMT(v, r, g, b, t) \ 310 ({ \ 311 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \ 312 (v)->transp.length = (t) ? (t) : 0; \ 313 (v)->blue.length = (b); (v)->blue.offset = 0; \ 314 (v)->green.length = (g); (v)->green.offset = (b); \ 315 (v)->red.length = (r); (v)->red.offset = (b) + (g); \ 316 }) 317 318 /* set the RGBT bitfields of fb_var_screeninf according to 319 * var->bits_per_pixel and given depth 320 */ 321 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth) 322 { 323 if (depth == 0) 324 depth = var->bits_per_pixel; 325 326 if (var->bits_per_pixel < 16) { 327 /* indexed pixel formats */ 328 var->red.offset = 0; var->red.length = 8; 329 var->green.offset = 0; var->green.length = 8; 330 var->blue.offset = 0; var->blue.length = 8; 331 var->transp.offset = 0; var->transp.length = 8; 332 } 333 334 switch (depth) { 335 case 16: var->transp.length ? 336 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */ 337 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */ 338 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */ 339 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */ 340 case 24: var->transp.length ? 341 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */ 342 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */ 343 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */ 344 } 345 } 346 347 #ifdef CONFIG_CPU_FREQ 348 /* 349 * pxafb_display_dma_period() 350 * Calculate the minimum period (in picoseconds) between two DMA 351 * requests for the LCD controller. If we hit this, it means we're 352 * doing nothing but LCD DMA. 353 */ 354 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) 355 { 356 /* 357 * Period = pixclock * bits_per_byte * bytes_per_transfer 358 * / memory_bits_per_pixel; 359 */ 360 return var->pixclock * 8 * 16 / var->bits_per_pixel; 361 } 362 #endif 363 364 /* 365 * Select the smallest mode that allows the desired resolution to be 366 * displayed. If desired parameters can be rounded up. 367 */ 368 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, 369 struct fb_var_screeninfo *var) 370 { 371 struct pxafb_mode_info *mode = NULL; 372 struct pxafb_mode_info *modelist = mach->modes; 373 unsigned int best_x = 0xffffffff, best_y = 0xffffffff; 374 unsigned int i; 375 376 for (i = 0; i < mach->num_modes; i++) { 377 if (modelist[i].xres >= var->xres && 378 modelist[i].yres >= var->yres && 379 modelist[i].xres < best_x && 380 modelist[i].yres < best_y && 381 modelist[i].bpp >= var->bits_per_pixel) { 382 best_x = modelist[i].xres; 383 best_y = modelist[i].yres; 384 mode = &modelist[i]; 385 } 386 } 387 388 return mode; 389 } 390 391 static void pxafb_setmode(struct fb_var_screeninfo *var, 392 struct pxafb_mode_info *mode) 393 { 394 var->xres = mode->xres; 395 var->yres = mode->yres; 396 var->bits_per_pixel = mode->bpp; 397 var->pixclock = mode->pixclock; 398 var->hsync_len = mode->hsync_len; 399 var->left_margin = mode->left_margin; 400 var->right_margin = mode->right_margin; 401 var->vsync_len = mode->vsync_len; 402 var->upper_margin = mode->upper_margin; 403 var->lower_margin = mode->lower_margin; 404 var->sync = mode->sync; 405 var->grayscale = mode->cmap_greyscale; 406 var->transp.length = mode->transparency; 407 408 /* set the initial RGBA bitfields */ 409 pxafb_set_pixfmt(var, mode->depth); 410 } 411 412 static int pxafb_adjust_timing(struct pxafb_info *fbi, 413 struct fb_var_screeninfo *var) 414 { 415 int line_length; 416 417 var->xres = max_t(int, var->xres, MIN_XRES); 418 var->yres = max_t(int, var->yres, MIN_YRES); 419 420 if (!(fbi->lccr0 & LCCR0_LCDT)) { 421 clamp_val(var->hsync_len, 1, 64); 422 clamp_val(var->vsync_len, 1, 64); 423 clamp_val(var->left_margin, 1, 255); 424 clamp_val(var->right_margin, 1, 255); 425 clamp_val(var->upper_margin, 1, 255); 426 clamp_val(var->lower_margin, 1, 255); 427 } 428 429 /* make sure each line is aligned on word boundary */ 430 line_length = var->xres * var->bits_per_pixel / 8; 431 line_length = ALIGN(line_length, 4); 432 var->xres = line_length * 8 / var->bits_per_pixel; 433 434 /* we don't support xpan, force xres_virtual to be equal to xres */ 435 var->xres_virtual = var->xres; 436 437 if (var->accel_flags & FB_ACCELF_TEXT) 438 var->yres_virtual = fbi->fb.fix.smem_len / line_length; 439 else 440 var->yres_virtual = max(var->yres_virtual, var->yres); 441 442 /* check for limits */ 443 if (var->xres > MAX_XRES || var->yres > MAX_YRES) 444 return -EINVAL; 445 446 if (var->yres > var->yres_virtual) 447 return -EINVAL; 448 449 return 0; 450 } 451 452 /* 453 * pxafb_check_var(): 454 * Get the video params out of 'var'. If a value doesn't fit, round it up, 455 * if it's too big, return -EINVAL. 456 * 457 * Round up in the following order: bits_per_pixel, xres, 458 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 459 * bitfields, horizontal timing, vertical timing. 460 */ 461 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 462 { 463 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 464 struct pxafb_mach_info *inf = fbi->inf; 465 int err; 466 467 if (inf->fixed_modes) { 468 struct pxafb_mode_info *mode; 469 470 mode = pxafb_getmode(inf, var); 471 if (!mode) 472 return -EINVAL; 473 pxafb_setmode(var, mode); 474 } 475 476 /* do a test conversion to BPP fields to check the color formats */ 477 err = pxafb_var_to_bpp(var); 478 if (err < 0) 479 return err; 480 481 pxafb_set_pixfmt(var, var_to_depth(var)); 482 483 err = pxafb_adjust_timing(fbi, var); 484 if (err) 485 return err; 486 487 #ifdef CONFIG_CPU_FREQ 488 pr_debug("pxafb: dma period = %d ps\n", 489 pxafb_display_dma_period(var)); 490 #endif 491 492 return 0; 493 } 494 495 /* 496 * pxafb_set_par(): 497 * Set the user defined part of the display for the specified console 498 */ 499 static int pxafb_set_par(struct fb_info *info) 500 { 501 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 502 struct fb_var_screeninfo *var = &info->var; 503 504 if (var->bits_per_pixel >= 16) 505 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; 506 else if (!fbi->cmap_static) 507 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 508 else { 509 /* 510 * Some people have weird ideas about wanting static 511 * pseudocolor maps. I suspect their user space 512 * applications are broken. 513 */ 514 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 515 } 516 517 fbi->fb.fix.line_length = var->xres_virtual * 518 var->bits_per_pixel / 8; 519 if (var->bits_per_pixel >= 16) 520 fbi->palette_size = 0; 521 else 522 fbi->palette_size = var->bits_per_pixel == 1 ? 523 4 : 1 << var->bits_per_pixel; 524 525 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; 526 527 if (fbi->fb.var.bits_per_pixel >= 16) 528 fb_dealloc_cmap(&fbi->fb.cmap); 529 else 530 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); 531 532 pxafb_activate_var(var, fbi); 533 534 return 0; 535 } 536 537 static int pxafb_pan_display(struct fb_var_screeninfo *var, 538 struct fb_info *info) 539 { 540 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 541 struct fb_var_screeninfo newvar; 542 int dma = DMA_MAX + DMA_BASE; 543 544 if (fbi->state != C_ENABLE) 545 return 0; 546 547 /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what 548 * was passed in and copy the rest from the old screeninfo. 549 */ 550 memcpy(&newvar, &fbi->fb.var, sizeof(newvar)); 551 newvar.xoffset = var->xoffset; 552 newvar.yoffset = var->yoffset; 553 newvar.vmode &= ~FB_VMODE_YWRAP; 554 newvar.vmode |= var->vmode & FB_VMODE_YWRAP; 555 556 setup_base_frame(fbi, &newvar, 1); 557 558 if (fbi->lccr0 & LCCR0_SDS) 559 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1); 560 561 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1); 562 return 0; 563 } 564 565 /* 566 * pxafb_blank(): 567 * Blank the display by setting all palette values to zero. Note, the 568 * 16 bpp mode does not really use the palette, so this will not 569 * blank the display in all modes. 570 */ 571 static int pxafb_blank(int blank, struct fb_info *info) 572 { 573 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 574 int i; 575 576 switch (blank) { 577 case FB_BLANK_POWERDOWN: 578 case FB_BLANK_VSYNC_SUSPEND: 579 case FB_BLANK_HSYNC_SUSPEND: 580 case FB_BLANK_NORMAL: 581 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 582 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 583 for (i = 0; i < fbi->palette_size; i++) 584 pxafb_setpalettereg(i, 0, 0, 0, 0, info); 585 586 pxafb_schedule_work(fbi, C_DISABLE); 587 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ 588 break; 589 590 case FB_BLANK_UNBLANK: 591 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ 592 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 593 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 594 fb_set_cmap(&fbi->fb.cmap, info); 595 pxafb_schedule_work(fbi, C_ENABLE); 596 } 597 return 0; 598 } 599 600 static const struct fb_ops pxafb_ops = { 601 .owner = THIS_MODULE, 602 FB_DEFAULT_IOMEM_OPS, 603 .fb_check_var = pxafb_check_var, 604 .fb_set_par = pxafb_set_par, 605 .fb_pan_display = pxafb_pan_display, 606 .fb_setcolreg = pxafb_setcolreg, 607 .fb_blank = pxafb_blank, 608 }; 609 610 #ifdef CONFIG_FB_PXA_OVERLAY 611 static void overlay1fb_setup(struct pxafb_layer *ofb) 612 { 613 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; 614 unsigned long start = ofb->video_mem_phys; 615 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size); 616 } 617 618 /* Depending on the enable status of overlay1/2, the DMA should be 619 * updated from FDADRx (when disabled) or FBRx (when enabled). 620 */ 621 static void overlay1fb_enable(struct pxafb_layer *ofb) 622 { 623 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN; 624 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0); 625 626 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1); 627 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]); 628 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN); 629 } 630 631 static void overlay1fb_disable(struct pxafb_layer *ofb) 632 { 633 uint32_t lccr5; 634 635 if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN)) 636 return; 637 638 lccr5 = lcd_readl(ofb->fbi, LCCR5); 639 640 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN); 641 642 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1)); 643 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1)); 644 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3); 645 646 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) 647 pr_warn("%s: timeout disabling overlay1\n", __func__); 648 649 lcd_writel(ofb->fbi, LCCR5, lccr5); 650 } 651 652 static void overlay2fb_setup(struct pxafb_layer *ofb) 653 { 654 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); 655 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 }; 656 657 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) { 658 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; 659 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); 660 } else { 661 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual; 662 switch (pfor) { 663 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break; 664 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break; 665 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break; 666 } 667 start[1] = start[0] + size; 668 start[2] = start[1] + size / div; 669 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); 670 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div); 671 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div); 672 } 673 } 674 675 static void overlay2fb_enable(struct pxafb_layer *ofb) 676 { 677 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); 678 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN; 679 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0); 680 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0); 681 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0); 682 683 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) 684 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); 685 else { 686 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); 687 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3); 688 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4); 689 } 690 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]); 691 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN); 692 } 693 694 static void overlay2fb_disable(struct pxafb_layer *ofb) 695 { 696 uint32_t lccr5; 697 698 if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN)) 699 return; 700 701 lccr5 = lcd_readl(ofb->fbi, LCCR5); 702 703 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN); 704 705 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2)); 706 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2)); 707 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3); 708 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3); 709 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3); 710 711 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) 712 pr_warn("%s: timeout disabling overlay2\n", __func__); 713 } 714 715 static struct pxafb_layer_ops ofb_ops[] = { 716 [0] = { 717 .enable = overlay1fb_enable, 718 .disable = overlay1fb_disable, 719 .setup = overlay1fb_setup, 720 }, 721 [1] = { 722 .enable = overlay2fb_enable, 723 .disable = overlay2fb_disable, 724 .setup = overlay2fb_setup, 725 }, 726 }; 727 728 static int overlayfb_open(struct fb_info *info, int user) 729 { 730 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb); 731 732 /* no support for framebuffer console on overlay */ 733 if (user == 0) 734 return -ENODEV; 735 736 if (ofb->usage++ == 0) { 737 /* unblank the base framebuffer */ 738 console_lock(); 739 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK); 740 console_unlock(); 741 } 742 743 return 0; 744 } 745 746 static int overlayfb_release(struct fb_info *info, int user) 747 { 748 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb); 749 750 if (ofb->usage == 1) { 751 ofb->ops->disable(ofb); 752 ofb->fb.var.height = -1; 753 ofb->fb.var.width = -1; 754 ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0; 755 ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0; 756 757 ofb->usage--; 758 } 759 return 0; 760 } 761 762 static int overlayfb_check_var(struct fb_var_screeninfo *var, 763 struct fb_info *info) 764 { 765 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb); 766 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var; 767 int xpos, ypos, pfor, bpp; 768 769 xpos = NONSTD_TO_XPOS(var->nonstd); 770 ypos = NONSTD_TO_YPOS(var->nonstd); 771 pfor = NONSTD_TO_PFOR(var->nonstd); 772 773 bpp = pxafb_var_to_bpp(var); 774 if (bpp < 0) 775 return -EINVAL; 776 777 /* no support for YUV format on overlay1 */ 778 if (ofb->id == OVERLAY1 && pfor != 0) 779 return -EINVAL; 780 781 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */ 782 switch (pfor) { 783 case OVERLAY_FORMAT_RGB: 784 bpp = pxafb_var_to_bpp(var); 785 if (bpp < 0) 786 return -EINVAL; 787 788 pxafb_set_pixfmt(var, var_to_depth(var)); 789 break; 790 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; 791 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break; 792 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break; 793 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break; 794 default: 795 return -EINVAL; 796 } 797 798 /* each line must start at a 32-bit word boundary */ 799 if ((xpos * bpp) % 32) 800 return -EINVAL; 801 802 /* xres must align on 32-bit word boundary */ 803 var->xres = roundup(var->xres * bpp, 32) / bpp; 804 805 if ((xpos + var->xres > base_var->xres) || 806 (ypos + var->yres > base_var->yres)) 807 return -EINVAL; 808 809 var->xres_virtual = var->xres; 810 var->yres_virtual = max(var->yres, var->yres_virtual); 811 return 0; 812 } 813 814 static int overlayfb_check_video_memory(struct pxafb_layer *ofb) 815 { 816 struct fb_var_screeninfo *var = &ofb->fb.var; 817 int pfor = NONSTD_TO_PFOR(var->nonstd); 818 int size, bpp = 0; 819 820 switch (pfor) { 821 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break; 822 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; 823 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break; 824 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break; 825 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break; 826 } 827 828 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8; 829 830 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual); 831 832 if (ofb->video_mem) { 833 if (ofb->video_mem_size >= size) 834 return 0; 835 } 836 return -EINVAL; 837 } 838 839 static int overlayfb_set_par(struct fb_info *info) 840 { 841 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb); 842 struct fb_var_screeninfo *var = &info->var; 843 int xpos, ypos, pfor, bpp, ret; 844 845 ret = overlayfb_check_video_memory(ofb); 846 if (ret) 847 return ret; 848 849 bpp = pxafb_var_to_bpp(var); 850 xpos = NONSTD_TO_XPOS(var->nonstd); 851 ypos = NONSTD_TO_YPOS(var->nonstd); 852 pfor = NONSTD_TO_PFOR(var->nonstd); 853 854 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) | 855 OVLxC1_BPP(bpp); 856 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos); 857 858 if (ofb->id == OVERLAY2) 859 ofb->control[1] |= OVL2C2_PFOR(pfor); 860 861 ofb->ops->setup(ofb); 862 ofb->ops->enable(ofb); 863 return 0; 864 } 865 866 static const struct fb_ops overlay_fb_ops = { 867 .owner = THIS_MODULE, 868 .fb_open = overlayfb_open, 869 .fb_release = overlayfb_release, 870 .fb_check_var = overlayfb_check_var, 871 .fb_set_par = overlayfb_set_par, 872 }; 873 874 static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb, 875 int id) 876 { 877 sprintf(ofb->fb.fix.id, "overlay%d", id + 1); 878 879 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS; 880 ofb->fb.fix.xpanstep = 0; 881 ofb->fb.fix.ypanstep = 1; 882 883 ofb->fb.var.activate = FB_ACTIVATE_NOW; 884 ofb->fb.var.height = -1; 885 ofb->fb.var.width = -1; 886 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED; 887 888 ofb->fb.fbops = &overlay_fb_ops; 889 ofb->fb.node = -1; 890 ofb->fb.pseudo_palette = NULL; 891 892 ofb->id = id; 893 ofb->ops = &ofb_ops[id]; 894 ofb->usage = 0; 895 ofb->fbi = fbi; 896 init_completion(&ofb->branch_done); 897 } 898 899 static inline int pxafb_overlay_supported(void) 900 { 901 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) 902 return 1; 903 904 return 0; 905 } 906 907 static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb, 908 struct pxafb_layer *ofb) 909 { 910 /* We assume that user will use at most video_mem_size for overlay fb, 911 * anyway, it's useless to use 16bpp main plane and 24bpp overlay 912 */ 913 ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size), 914 GFP_KERNEL | __GFP_ZERO); 915 if (ofb->video_mem == NULL) 916 return -ENOMEM; 917 918 ofb->video_mem_phys = virt_to_phys(ofb->video_mem); 919 ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size); 920 921 mutex_lock(&ofb->fb.mm_lock); 922 ofb->fb.fix.smem_start = ofb->video_mem_phys; 923 ofb->fb.fix.smem_len = pxafb->video_mem_size; 924 mutex_unlock(&ofb->fb.mm_lock); 925 926 ofb->fb.screen_base = ofb->video_mem; 927 928 return 0; 929 } 930 931 static void pxafb_overlay_init(struct pxafb_info *fbi) 932 { 933 int i, ret; 934 935 if (!pxafb_overlay_supported()) 936 return; 937 938 for (i = 0; i < 2; i++) { 939 struct pxafb_layer *ofb = &fbi->overlay[i]; 940 init_pxafb_overlay(fbi, ofb, i); 941 ret = register_framebuffer(&ofb->fb); 942 if (ret) { 943 dev_err(fbi->dev, "failed to register overlay %d\n", i); 944 continue; 945 } 946 ret = pxafb_overlay_map_video_memory(fbi, ofb); 947 if (ret) { 948 dev_err(fbi->dev, 949 "failed to map video memory for overlay %d\n", 950 i); 951 unregister_framebuffer(&ofb->fb); 952 continue; 953 } 954 ofb->registered = 1; 955 } 956 957 /* mask all IU/BS/EOF/SOF interrupts */ 958 lcd_writel(fbi, LCCR5, ~0); 959 960 pr_info("PXA Overlay driver loaded successfully!\n"); 961 } 962 963 static void pxafb_overlay_exit(struct pxafb_info *fbi) 964 { 965 int i; 966 967 if (!pxafb_overlay_supported()) 968 return; 969 970 for (i = 0; i < 2; i++) { 971 struct pxafb_layer *ofb = &fbi->overlay[i]; 972 if (ofb->registered) { 973 if (ofb->video_mem) 974 free_pages_exact(ofb->video_mem, 975 ofb->video_mem_size); 976 unregister_framebuffer(&ofb->fb); 977 } 978 } 979 } 980 #else 981 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {} 982 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {} 983 #endif /* CONFIG_FB_PXA_OVERLAY */ 984 985 /* 986 * Calculate the PCD value from the clock rate (in picoseconds). 987 * We take account of the PPCR clock setting. 988 * From PXA Developer's Manual: 989 * 990 * PixelClock = LCLK 991 * ------------- 992 * 2 ( PCD + 1 ) 993 * 994 * PCD = LCLK 995 * ------------- - 1 996 * 2(PixelClock) 997 * 998 * Where: 999 * LCLK = LCD/Memory Clock 1000 * PCD = LCCR3[7:0] 1001 * 1002 * PixelClock here is in Hz while the pixclock argument given is the 1003 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) 1004 * 1005 * The function get_lclk_frequency_10khz returns LCLK in units of 1006 * 10khz. Calling the result of this function lclk gives us the 1007 * following 1008 * 1009 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) 1010 * -------------------------------------- - 1 1011 * 2 1012 * 1013 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. 1014 */ 1015 static inline unsigned int get_pcd(struct pxafb_info *fbi, 1016 unsigned int pixclock) 1017 { 1018 unsigned long long pcd; 1019 1020 /* FIXME: Need to take into account Double Pixel Clock mode 1021 * (DPC) bit? or perhaps set it based on the various clock 1022 * speeds */ 1023 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); 1024 pcd *= pixclock; 1025 do_div(pcd, 100000000 * 2); 1026 /* no need for this, since we should subtract 1 anyway. they cancel */ 1027 /* pcd += 1; */ /* make up for integer math truncations */ 1028 return (unsigned int)pcd; 1029 } 1030 1031 /* 1032 * Some touchscreens need hsync information from the video driver to 1033 * function correctly. We export it here. Note that 'hsync_time' is 1034 * the *reciprocal* of the hsync period in seconds. 1035 */ 1036 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) 1037 { 1038 unsigned long htime; 1039 1040 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { 1041 fbi->hsync_time = 0; 1042 return; 1043 } 1044 1045 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len); 1046 1047 fbi->hsync_time = htime; 1048 } 1049 1050 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, 1051 unsigned long start, size_t size) 1052 { 1053 struct pxafb_dma_descriptor *dma_desc, *pal_desc; 1054 unsigned int dma_desc_off, pal_desc_off; 1055 1056 if (dma < 0 || dma >= DMA_MAX * 2) 1057 return -EINVAL; 1058 1059 dma_desc = &fbi->dma_buff->dma_desc[dma]; 1060 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); 1061 1062 dma_desc->fsadr = start; 1063 dma_desc->fidr = 0; 1064 dma_desc->ldcmd = size; 1065 1066 if (pal < 0 || pal >= PAL_MAX * 2) { 1067 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1068 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; 1069 } else { 1070 pal_desc = &fbi->dma_buff->pal_desc[pal]; 1071 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]); 1072 1073 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE; 1074 pal_desc->fidr = 0; 1075 1076 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) 1077 pal_desc->ldcmd = fbi->palette_size * sizeof(u16); 1078 else 1079 pal_desc->ldcmd = fbi->palette_size * sizeof(u32); 1080 1081 pal_desc->ldcmd |= LDCMD_PAL; 1082 1083 /* flip back and forth between palette and frame buffer */ 1084 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1085 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off; 1086 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; 1087 } 1088 1089 return 0; 1090 } 1091 1092 static void setup_base_frame(struct pxafb_info *fbi, 1093 struct fb_var_screeninfo *var, 1094 int branch) 1095 { 1096 struct fb_fix_screeninfo *fix = &fbi->fb.fix; 1097 int nbytes, dma, pal, bpp = var->bits_per_pixel; 1098 unsigned long offset; 1099 1100 dma = DMA_BASE + (branch ? DMA_MAX : 0); 1101 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0); 1102 1103 nbytes = fix->line_length * var->yres; 1104 offset = fix->line_length * var->yoffset + fbi->video_mem_phys; 1105 1106 if (fbi->lccr0 & LCCR0_SDS) { 1107 nbytes = nbytes / 2; 1108 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes); 1109 } 1110 1111 setup_frame_dma(fbi, dma, pal, offset, nbytes); 1112 } 1113 1114 #ifdef CONFIG_FB_PXA_SMARTPANEL 1115 static int setup_smart_dma(struct pxafb_info *fbi) 1116 { 1117 struct pxafb_dma_descriptor *dma_desc; 1118 unsigned long dma_desc_off, cmd_buff_off; 1119 1120 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD]; 1121 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]); 1122 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff); 1123 1124 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1125 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off; 1126 dma_desc->fidr = 0; 1127 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t); 1128 1129 fbi->fdadr[DMA_CMD] = dma_desc->fdadr; 1130 return 0; 1131 } 1132 1133 int pxafb_smart_flush(struct fb_info *info) 1134 { 1135 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 1136 uint32_t prsr; 1137 int ret = 0; 1138 1139 /* disable controller until all registers are set up */ 1140 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1141 1142 /* 1. make it an even number of commands to align on 32-bit boundary 1143 * 2. add the interrupt command to the end of the chain so we can 1144 * keep track of the end of the transfer 1145 */ 1146 1147 while (fbi->n_smart_cmds & 1) 1148 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP; 1149 1150 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT; 1151 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC; 1152 setup_smart_dma(fbi); 1153 1154 /* continue to execute next command */ 1155 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT; 1156 lcd_writel(fbi, PRSR, prsr); 1157 1158 /* stop the processor in case it executed "wait for sync" cmd */ 1159 lcd_writel(fbi, CMDCR, 0x0001); 1160 1161 /* don't send interrupts for fifo underruns on channel 6 */ 1162 lcd_writel(fbi, LCCR5, LCCR5_IUM(6)); 1163 1164 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1165 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1166 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1167 lcd_writel(fbi, LCCR4, fbi->reg_lccr4); 1168 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 1169 lcd_writel(fbi, FDADR6, fbi->fdadr[6]); 1170 1171 /* begin sending */ 1172 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); 1173 1174 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) { 1175 pr_warn("%s: timeout waiting for command done\n", __func__); 1176 ret = -ETIMEDOUT; 1177 } 1178 1179 /* quick disable */ 1180 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT); 1181 lcd_writel(fbi, PRSR, prsr); 1182 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1183 lcd_writel(fbi, FDADR6, 0); 1184 fbi->n_smart_cmds = 0; 1185 return ret; 1186 } 1187 1188 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) 1189 { 1190 int i; 1191 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 1192 1193 for (i = 0; i < n_cmds; i++, cmds++) { 1194 /* if it is a software delay, flush and delay */ 1195 if ((*cmds & 0xff00) == SMART_CMD_DELAY) { 1196 pxafb_smart_flush(info); 1197 mdelay(*cmds & 0xff); 1198 continue; 1199 } 1200 1201 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ 1202 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8) 1203 pxafb_smart_flush(info); 1204 1205 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds; 1206 } 1207 1208 return 0; 1209 } 1210 1211 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk) 1212 { 1213 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000); 1214 return (t == 0) ? 1 : t; 1215 } 1216 1217 static void setup_smart_timing(struct pxafb_info *fbi, 1218 struct fb_var_screeninfo *var) 1219 { 1220 struct pxafb_mach_info *inf = fbi->inf; 1221 struct pxafb_mode_info *mode = &inf->modes[0]; 1222 unsigned long lclk = clk_get_rate(fbi->clk); 1223 unsigned t1, t2, t3, t4; 1224 1225 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld); 1226 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width); 1227 t3 = mode->op_hold_time; 1228 t4 = mode->cmd_inh_time; 1229 1230 fbi->reg_lccr1 = 1231 LCCR1_DisWdth(var->xres) | 1232 LCCR1_BegLnDel(__smart_timing(t1, lclk)) | 1233 LCCR1_EndLnDel(__smart_timing(t2, lclk)) | 1234 LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); 1235 1236 fbi->reg_lccr2 = LCCR2_DisHght(var->yres); 1237 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk)); 1238 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0; 1239 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; 1240 1241 /* FIXME: make this configurable */ 1242 fbi->reg_cmdcr = 1; 1243 } 1244 1245 static int pxafb_smart_thread(void *arg) 1246 { 1247 struct pxafb_info *fbi = arg; 1248 struct pxafb_mach_info *inf = fbi->inf; 1249 1250 if (!inf->smart_update) { 1251 pr_err("%s: not properly initialized, thread terminated\n", 1252 __func__); 1253 return -EINVAL; 1254 } 1255 1256 pr_debug("%s(): task starting\n", __func__); 1257 1258 set_freezable(); 1259 while (!kthread_should_stop()) { 1260 1261 if (try_to_freeze()) 1262 continue; 1263 1264 mutex_lock(&fbi->ctrlr_lock); 1265 1266 if (fbi->state == C_ENABLE) { 1267 inf->smart_update(&fbi->fb); 1268 complete(&fbi->refresh_done); 1269 } 1270 1271 mutex_unlock(&fbi->ctrlr_lock); 1272 1273 set_current_state(TASK_INTERRUPTIBLE); 1274 schedule_timeout(msecs_to_jiffies(30)); 1275 } 1276 1277 pr_debug("%s(): task ending\n", __func__); 1278 return 0; 1279 } 1280 1281 static int pxafb_smart_init(struct pxafb_info *fbi) 1282 { 1283 if (!(fbi->lccr0 & LCCR0_LCDT)) 1284 return 0; 1285 1286 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; 1287 fbi->n_smart_cmds = 0; 1288 1289 init_completion(&fbi->command_done); 1290 init_completion(&fbi->refresh_done); 1291 1292 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, 1293 "lcd_refresh"); 1294 if (IS_ERR(fbi->smart_thread)) { 1295 pr_err("%s: unable to create kernel thread\n", __func__); 1296 return PTR_ERR(fbi->smart_thread); 1297 } 1298 1299 return 0; 1300 } 1301 #else 1302 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; } 1303 #endif /* CONFIG_FB_PXA_SMARTPANEL */ 1304 1305 static void setup_parallel_timing(struct pxafb_info *fbi, 1306 struct fb_var_screeninfo *var) 1307 { 1308 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock); 1309 1310 fbi->reg_lccr1 = 1311 LCCR1_DisWdth(var->xres) + 1312 LCCR1_HorSnchWdth(var->hsync_len) + 1313 LCCR1_BegLnDel(var->left_margin) + 1314 LCCR1_EndLnDel(var->right_margin); 1315 1316 /* 1317 * If we have a dual scan LCD, we need to halve 1318 * the YRES parameter. 1319 */ 1320 lines_per_panel = var->yres; 1321 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) 1322 lines_per_panel /= 2; 1323 1324 fbi->reg_lccr2 = 1325 LCCR2_DisHght(lines_per_panel) + 1326 LCCR2_VrtSnchWdth(var->vsync_len) + 1327 LCCR2_BegFrmDel(var->upper_margin) + 1328 LCCR2_EndFrmDel(var->lower_margin); 1329 1330 fbi->reg_lccr3 = fbi->lccr3 | 1331 (var->sync & FB_SYNC_HOR_HIGH_ACT ? 1332 LCCR3_HorSnchH : LCCR3_HorSnchL) | 1333 (var->sync & FB_SYNC_VERT_HIGH_ACT ? 1334 LCCR3_VrtSnchH : LCCR3_VrtSnchL); 1335 1336 if (pcd) { 1337 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd); 1338 set_hsync_time(fbi, pcd); 1339 } 1340 } 1341 1342 /* 1343 * pxafb_activate_var(): 1344 * Configures LCD Controller based on entries in var parameter. 1345 * Settings are only written to the controller if changes were made. 1346 */ 1347 static int pxafb_activate_var(struct fb_var_screeninfo *var, 1348 struct pxafb_info *fbi) 1349 { 1350 u_long flags; 1351 1352 /* Update shadow copy atomically */ 1353 local_irq_save(flags); 1354 1355 #ifdef CONFIG_FB_PXA_SMARTPANEL 1356 if (fbi->lccr0 & LCCR0_LCDT) 1357 setup_smart_timing(fbi, var); 1358 else 1359 #endif 1360 setup_parallel_timing(fbi, var); 1361 1362 setup_base_frame(fbi, var, 0); 1363 1364 fbi->reg_lccr0 = fbi->lccr0 | 1365 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | 1366 LCCR0_QDM | LCCR0_BM | LCCR0_OUM); 1367 1368 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var); 1369 1370 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; 1371 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); 1372 local_irq_restore(flags); 1373 1374 /* 1375 * Only update the registers if the controller is enabled 1376 * and something has changed. 1377 */ 1378 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) || 1379 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || 1380 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || 1381 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || 1382 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) || 1383 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || 1384 ((fbi->lccr0 & LCCR0_SDS) && 1385 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))) 1386 pxafb_schedule_work(fbi, C_REENABLE); 1387 1388 return 0; 1389 } 1390 1391 /* 1392 * NOTE! The following functions are purely helpers for set_ctrlr_state. 1393 * Do not call them directly; set_ctrlr_state does the correct serialisation 1394 * to ensure that things happen in the right way 100% of time time. 1395 * -- rmk 1396 */ 1397 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) 1398 { 1399 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); 1400 1401 if (fbi->backlight_power) 1402 fbi->backlight_power(on); 1403 } 1404 1405 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) 1406 { 1407 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); 1408 1409 if (fbi->lcd_power) 1410 fbi->lcd_power(on, &fbi->fb.var); 1411 1412 if (fbi->lcd_supply && fbi->lcd_supply_enabled != on) { 1413 int ret; 1414 1415 if (on) 1416 ret = regulator_enable(fbi->lcd_supply); 1417 else 1418 ret = regulator_disable(fbi->lcd_supply); 1419 1420 if (ret < 0) 1421 pr_warn("Unable to %s LCD supply regulator: %d\n", 1422 on ? "enable" : "disable", ret); 1423 else 1424 fbi->lcd_supply_enabled = on; 1425 } 1426 } 1427 1428 static void pxafb_enable_controller(struct pxafb_info *fbi) 1429 { 1430 pr_debug("pxafb: Enabling LCD controller\n"); 1431 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]); 1432 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]); 1433 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); 1434 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); 1435 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); 1436 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); 1437 1438 /* enable LCD controller clock */ 1439 if (clk_prepare_enable(fbi->clk)) { 1440 pr_err("%s: Failed to prepare clock\n", __func__); 1441 return; 1442 } 1443 1444 if (fbi->lccr0 & LCCR0_LCDT) 1445 return; 1446 1447 /* Sequence from 11.7.10 */ 1448 lcd_writel(fbi, LCCR4, fbi->reg_lccr4); 1449 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1450 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1451 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1452 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1453 1454 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 1455 if (fbi->lccr0 & LCCR0_SDS) 1456 lcd_writel(fbi, FDADR1, fbi->fdadr[1]); 1457 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); 1458 } 1459 1460 static void pxafb_disable_controller(struct pxafb_info *fbi) 1461 { 1462 uint32_t lccr0; 1463 1464 #ifdef CONFIG_FB_PXA_SMARTPANEL 1465 if (fbi->lccr0 & LCCR0_LCDT) { 1466 wait_for_completion_timeout(&fbi->refresh_done, 1467 msecs_to_jiffies(200)); 1468 return; 1469 } 1470 #endif 1471 1472 /* Clear LCD Status Register */ 1473 lcd_writel(fbi, LCSR, 0xffffffff); 1474 1475 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM; 1476 lcd_writel(fbi, LCCR0, lccr0); 1477 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS); 1478 1479 wait_for_completion_timeout(&fbi->disable_done, msecs_to_jiffies(200)); 1480 1481 /* disable LCD controller clock */ 1482 clk_disable_unprepare(fbi->clk); 1483 } 1484 1485 /* 1486 * pxafb_handle_irq: Handle 'LCD DONE' interrupts. 1487 */ 1488 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) 1489 { 1490 struct pxafb_info *fbi = dev_id; 1491 unsigned int lccr0, lcsr; 1492 1493 lcsr = lcd_readl(fbi, LCSR); 1494 if (lcsr & LCSR_LDD) { 1495 lccr0 = lcd_readl(fbi, LCCR0); 1496 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); 1497 complete(&fbi->disable_done); 1498 } 1499 1500 #ifdef CONFIG_FB_PXA_SMARTPANEL 1501 if (lcsr & LCSR_CMD_INT) 1502 complete(&fbi->command_done); 1503 #endif 1504 lcd_writel(fbi, LCSR, lcsr); 1505 1506 #ifdef CONFIG_FB_PXA_OVERLAY 1507 { 1508 unsigned int lcsr1 = lcd_readl(fbi, LCSR1); 1509 if (lcsr1 & LCSR1_BS(1)) 1510 complete(&fbi->overlay[0].branch_done); 1511 1512 if (lcsr1 & LCSR1_BS(2)) 1513 complete(&fbi->overlay[1].branch_done); 1514 1515 lcd_writel(fbi, LCSR1, lcsr1); 1516 } 1517 #endif 1518 return IRQ_HANDLED; 1519 } 1520 1521 /* 1522 * This function must be called from task context only, since it will 1523 * sleep when disabling the LCD controller, or if we get two contending 1524 * processes trying to alter state. 1525 */ 1526 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) 1527 { 1528 u_int old_state; 1529 1530 mutex_lock(&fbi->ctrlr_lock); 1531 1532 old_state = fbi->state; 1533 1534 /* 1535 * Hack around fbcon initialisation. 1536 */ 1537 if (old_state == C_STARTUP && state == C_REENABLE) 1538 state = C_ENABLE; 1539 1540 switch (state) { 1541 case C_DISABLE_CLKCHANGE: 1542 /* 1543 * Disable controller for clock change. If the 1544 * controller is already disabled, then do nothing. 1545 */ 1546 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { 1547 fbi->state = state; 1548 /* TODO __pxafb_lcd_power(fbi, 0); */ 1549 pxafb_disable_controller(fbi); 1550 } 1551 break; 1552 1553 case C_DISABLE_PM: 1554 case C_DISABLE: 1555 /* 1556 * Disable controller 1557 */ 1558 if (old_state != C_DISABLE) { 1559 fbi->state = state; 1560 __pxafb_backlight_power(fbi, 0); 1561 __pxafb_lcd_power(fbi, 0); 1562 if (old_state != C_DISABLE_CLKCHANGE) 1563 pxafb_disable_controller(fbi); 1564 } 1565 break; 1566 1567 case C_ENABLE_CLKCHANGE: 1568 /* 1569 * Enable the controller after clock change. Only 1570 * do this if we were disabled for the clock change. 1571 */ 1572 if (old_state == C_DISABLE_CLKCHANGE) { 1573 fbi->state = C_ENABLE; 1574 pxafb_enable_controller(fbi); 1575 /* TODO __pxafb_lcd_power(fbi, 1); */ 1576 } 1577 break; 1578 1579 case C_REENABLE: 1580 /* 1581 * Re-enable the controller only if it was already 1582 * enabled. This is so we reprogram the control 1583 * registers. 1584 */ 1585 if (old_state == C_ENABLE) { 1586 __pxafb_lcd_power(fbi, 0); 1587 pxafb_disable_controller(fbi); 1588 pxafb_enable_controller(fbi); 1589 __pxafb_lcd_power(fbi, 1); 1590 } 1591 break; 1592 1593 case C_ENABLE_PM: 1594 /* 1595 * Re-enable the controller after PM. This is not 1596 * perfect - think about the case where we were doing 1597 * a clock change, and we suspended half-way through. 1598 */ 1599 if (old_state != C_DISABLE_PM) 1600 break; 1601 fallthrough; 1602 1603 case C_ENABLE: 1604 /* 1605 * Power up the LCD screen, enable controller, and 1606 * turn on the backlight. 1607 */ 1608 if (old_state != C_ENABLE) { 1609 fbi->state = C_ENABLE; 1610 pxafb_enable_controller(fbi); 1611 __pxafb_lcd_power(fbi, 1); 1612 __pxafb_backlight_power(fbi, 1); 1613 } 1614 break; 1615 } 1616 mutex_unlock(&fbi->ctrlr_lock); 1617 } 1618 1619 /* 1620 * Our LCD controller task (which is called when we blank or unblank) 1621 * via keventd. 1622 */ 1623 static void pxafb_task(struct work_struct *work) 1624 { 1625 struct pxafb_info *fbi = 1626 container_of(work, struct pxafb_info, task); 1627 u_int state = xchg(&fbi->task_state, -1); 1628 1629 set_ctrlr_state(fbi, state); 1630 } 1631 1632 #ifdef CONFIG_CPU_FREQ 1633 /* 1634 * CPU clock speed change handler. We need to adjust the LCD timing 1635 * parameters when the CPU clock is adjusted by the power management 1636 * subsystem. 1637 * 1638 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() 1639 */ 1640 static int 1641 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) 1642 { 1643 struct pxafb_info *fbi = TO_INF(nb, freq_transition); 1644 /* TODO struct cpufreq_freqs *f = data; */ 1645 u_int pcd; 1646 1647 switch (val) { 1648 case CPUFREQ_PRECHANGE: 1649 #ifdef CONFIG_FB_PXA_OVERLAY 1650 if (!(fbi->overlay[0].usage || fbi->overlay[1].usage)) 1651 #endif 1652 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); 1653 break; 1654 1655 case CPUFREQ_POSTCHANGE: 1656 pcd = get_pcd(fbi, fbi->fb.var.pixclock); 1657 set_hsync_time(fbi, pcd); 1658 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | 1659 LCCR3_PixClkDiv(pcd); 1660 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); 1661 break; 1662 } 1663 return 0; 1664 } 1665 #endif 1666 1667 #ifdef CONFIG_PM 1668 /* 1669 * Power management hooks. Note that we won't be called from IRQ context, 1670 * unlike the blank functions above, so we may sleep. 1671 */ 1672 static int pxafb_suspend(struct device *dev) 1673 { 1674 struct pxafb_info *fbi = dev_get_drvdata(dev); 1675 1676 set_ctrlr_state(fbi, C_DISABLE_PM); 1677 return 0; 1678 } 1679 1680 static int pxafb_resume(struct device *dev) 1681 { 1682 struct pxafb_info *fbi = dev_get_drvdata(dev); 1683 1684 set_ctrlr_state(fbi, C_ENABLE_PM); 1685 return 0; 1686 } 1687 1688 static const struct dev_pm_ops pxafb_pm_ops = { 1689 .suspend = pxafb_suspend, 1690 .resume = pxafb_resume, 1691 }; 1692 #endif 1693 1694 static int pxafb_init_video_memory(struct pxafb_info *fbi) 1695 { 1696 int size = PAGE_ALIGN(fbi->video_mem_size); 1697 1698 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO); 1699 if (fbi->video_mem == NULL) 1700 return -ENOMEM; 1701 1702 fbi->video_mem_phys = virt_to_phys(fbi->video_mem); 1703 fbi->video_mem_size = size; 1704 1705 fbi->fb.fix.smem_start = fbi->video_mem_phys; 1706 fbi->fb.fix.smem_len = fbi->video_mem_size; 1707 fbi->fb.screen_base = fbi->video_mem; 1708 1709 return fbi->video_mem ? 0 : -ENOMEM; 1710 } 1711 1712 static void pxafb_decode_mach_info(struct pxafb_info *fbi, 1713 struct pxafb_mach_info *inf) 1714 { 1715 unsigned int lcd_conn = inf->lcd_conn; 1716 struct pxafb_mode_info *m; 1717 int i; 1718 1719 fbi->cmap_inverse = inf->cmap_inverse; 1720 fbi->cmap_static = inf->cmap_static; 1721 fbi->lccr4 = inf->lccr4; 1722 1723 switch (lcd_conn & LCD_TYPE_MASK) { 1724 case LCD_TYPE_MONO_STN: 1725 fbi->lccr0 = LCCR0_CMS; 1726 break; 1727 case LCD_TYPE_MONO_DSTN: 1728 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS; 1729 break; 1730 case LCD_TYPE_COLOR_STN: 1731 fbi->lccr0 = 0; 1732 break; 1733 case LCD_TYPE_COLOR_DSTN: 1734 fbi->lccr0 = LCCR0_SDS; 1735 break; 1736 case LCD_TYPE_COLOR_TFT: 1737 fbi->lccr0 = LCCR0_PAS; 1738 break; 1739 case LCD_TYPE_SMART_PANEL: 1740 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS; 1741 break; 1742 default: 1743 /* fall back to backward compatibility way */ 1744 fbi->lccr0 = inf->lccr0; 1745 fbi->lccr3 = inf->lccr3; 1746 goto decode_mode; 1747 } 1748 1749 if (lcd_conn == LCD_MONO_STN_8BPP) 1750 fbi->lccr0 |= LCCR0_DPD; 1751 1752 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0; 1753 1754 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff); 1755 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0; 1756 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; 1757 1758 decode_mode: 1759 pxafb_setmode(&fbi->fb.var, &inf->modes[0]); 1760 1761 /* decide video memory size as follows: 1762 * 1. default to mode of maximum resolution 1763 * 2. allow platform to override 1764 * 3. allow module parameter to override 1765 */ 1766 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++) 1767 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size, 1768 m->xres * m->yres * m->bpp / 8); 1769 1770 if (inf->video_mem_size > fbi->video_mem_size) 1771 fbi->video_mem_size = inf->video_mem_size; 1772 1773 if (video_mem_size > fbi->video_mem_size) 1774 fbi->video_mem_size = video_mem_size; 1775 } 1776 1777 static struct pxafb_info *pxafb_init_fbinfo(struct device *dev, 1778 struct pxafb_mach_info *inf) 1779 { 1780 struct pxafb_info *fbi; 1781 void *addr; 1782 1783 /* Alloc the pxafb_info and pseudo_palette in one step */ 1784 fbi = devm_kzalloc(dev, sizeof(struct pxafb_info) + sizeof(u32) * 16, 1785 GFP_KERNEL); 1786 if (!fbi) 1787 return ERR_PTR(-ENOMEM); 1788 1789 fbi->dev = dev; 1790 fbi->inf = inf; 1791 1792 fbi->clk = devm_clk_get(dev, NULL); 1793 if (IS_ERR(fbi->clk)) 1794 return ERR_CAST(fbi->clk); 1795 1796 strcpy(fbi->fb.fix.id, PXA_NAME); 1797 1798 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1799 fbi->fb.fix.type_aux = 0; 1800 fbi->fb.fix.xpanstep = 0; 1801 fbi->fb.fix.ypanstep = 1; 1802 fbi->fb.fix.ywrapstep = 0; 1803 fbi->fb.fix.accel = FB_ACCEL_NONE; 1804 1805 fbi->fb.var.nonstd = 0; 1806 fbi->fb.var.activate = FB_ACTIVATE_NOW; 1807 fbi->fb.var.height = -1; 1808 fbi->fb.var.width = -1; 1809 fbi->fb.var.accel_flags = FB_ACCELF_TEXT; 1810 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; 1811 1812 fbi->fb.fbops = &pxafb_ops; 1813 fbi->fb.node = -1; 1814 1815 addr = fbi; 1816 addr = addr + sizeof(struct pxafb_info); 1817 fbi->fb.pseudo_palette = addr; 1818 1819 fbi->state = C_STARTUP; 1820 fbi->task_state = (u_char)-1; 1821 1822 pxafb_decode_mach_info(fbi, inf); 1823 1824 #ifdef CONFIG_FB_PXA_OVERLAY 1825 /* place overlay(s) on top of base */ 1826 if (pxafb_overlay_supported()) 1827 fbi->lccr0 |= LCCR0_OUC; 1828 #endif 1829 1830 init_waitqueue_head(&fbi->ctrlr_wait); 1831 INIT_WORK(&fbi->task, pxafb_task); 1832 mutex_init(&fbi->ctrlr_lock); 1833 init_completion(&fbi->disable_done); 1834 1835 return fbi; 1836 } 1837 1838 #ifdef CONFIG_FB_PXA_PARAMETERS 1839 static int parse_opt_mode(struct device *dev, const char *this_opt, 1840 struct pxafb_mach_info *inf) 1841 { 1842 const char *name = this_opt+5; 1843 unsigned int namelen = strlen(name); 1844 int res_specified = 0, bpp_specified = 0; 1845 unsigned int xres = 0, yres = 0, bpp = 0; 1846 int yres_specified = 0; 1847 int i; 1848 for (i = namelen-1; i >= 0; i--) { 1849 switch (name[i]) { 1850 case '-': 1851 namelen = i; 1852 if (!bpp_specified && !yres_specified) { 1853 bpp = simple_strtoul(&name[i+1], NULL, 0); 1854 bpp_specified = 1; 1855 } else 1856 goto done; 1857 break; 1858 case 'x': 1859 if (!yres_specified) { 1860 yres = simple_strtoul(&name[i+1], NULL, 0); 1861 yres_specified = 1; 1862 } else 1863 goto done; 1864 break; 1865 case '0' ... '9': 1866 break; 1867 default: 1868 goto done; 1869 } 1870 } 1871 if (i < 0 && yres_specified) { 1872 xres = simple_strtoul(name, NULL, 0); 1873 res_specified = 1; 1874 } 1875 done: 1876 if (res_specified) { 1877 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); 1878 inf->modes[0].xres = xres; inf->modes[0].yres = yres; 1879 } 1880 if (bpp_specified) 1881 switch (bpp) { 1882 case 1: 1883 case 2: 1884 case 4: 1885 case 8: 1886 case 16: 1887 inf->modes[0].bpp = bpp; 1888 dev_info(dev, "overriding bit depth: %d\n", bpp); 1889 break; 1890 default: 1891 dev_err(dev, "Depth %d is not valid\n", bpp); 1892 return -EINVAL; 1893 } 1894 return 0; 1895 } 1896 1897 static int parse_opt(struct device *dev, char *this_opt, 1898 struct pxafb_mach_info *inf) 1899 { 1900 struct pxafb_mode_info *mode = &inf->modes[0]; 1901 char s[64]; 1902 1903 s[0] = '\0'; 1904 1905 if (!strncmp(this_opt, "vmem:", 5)) { 1906 video_mem_size = memparse(this_opt + 5, NULL); 1907 } else if (!strncmp(this_opt, "mode:", 5)) { 1908 return parse_opt_mode(dev, this_opt, inf); 1909 } else if (!strncmp(this_opt, "pixclock:", 9)) { 1910 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); 1911 sprintf(s, "pixclock: %ld\n", mode->pixclock); 1912 } else if (!strncmp(this_opt, "left:", 5)) { 1913 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0); 1914 sprintf(s, "left: %u\n", mode->left_margin); 1915 } else if (!strncmp(this_opt, "right:", 6)) { 1916 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0); 1917 sprintf(s, "right: %u\n", mode->right_margin); 1918 } else if (!strncmp(this_opt, "upper:", 6)) { 1919 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0); 1920 sprintf(s, "upper: %u\n", mode->upper_margin); 1921 } else if (!strncmp(this_opt, "lower:", 6)) { 1922 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0); 1923 sprintf(s, "lower: %u\n", mode->lower_margin); 1924 } else if (!strncmp(this_opt, "hsynclen:", 9)) { 1925 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0); 1926 sprintf(s, "hsynclen: %u\n", mode->hsync_len); 1927 } else if (!strncmp(this_opt, "vsynclen:", 9)) { 1928 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0); 1929 sprintf(s, "vsynclen: %u\n", mode->vsync_len); 1930 } else if (!strncmp(this_opt, "hsync:", 6)) { 1931 if (simple_strtoul(this_opt+6, NULL, 0) == 0) { 1932 sprintf(s, "hsync: Active Low\n"); 1933 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT; 1934 } else { 1935 sprintf(s, "hsync: Active High\n"); 1936 mode->sync |= FB_SYNC_HOR_HIGH_ACT; 1937 } 1938 } else if (!strncmp(this_opt, "vsync:", 6)) { 1939 if (simple_strtoul(this_opt+6, NULL, 0) == 0) { 1940 sprintf(s, "vsync: Active Low\n"); 1941 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT; 1942 } else { 1943 sprintf(s, "vsync: Active High\n"); 1944 mode->sync |= FB_SYNC_VERT_HIGH_ACT; 1945 } 1946 } else if (!strncmp(this_opt, "dpc:", 4)) { 1947 if (simple_strtoul(this_opt+4, NULL, 0) == 0) { 1948 sprintf(s, "double pixel clock: false\n"); 1949 inf->lccr3 &= ~LCCR3_DPC; 1950 } else { 1951 sprintf(s, "double pixel clock: true\n"); 1952 inf->lccr3 |= LCCR3_DPC; 1953 } 1954 } else if (!strncmp(this_opt, "outputen:", 9)) { 1955 if (simple_strtoul(this_opt+9, NULL, 0) == 0) { 1956 sprintf(s, "output enable: active low\n"); 1957 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; 1958 } else { 1959 sprintf(s, "output enable: active high\n"); 1960 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; 1961 } 1962 } else if (!strncmp(this_opt, "pixclockpol:", 12)) { 1963 if (simple_strtoul(this_opt+12, NULL, 0) == 0) { 1964 sprintf(s, "pixel clock polarity: falling edge\n"); 1965 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; 1966 } else { 1967 sprintf(s, "pixel clock polarity: rising edge\n"); 1968 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; 1969 } 1970 } else if (!strncmp(this_opt, "color", 5)) { 1971 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; 1972 } else if (!strncmp(this_opt, "mono", 4)) { 1973 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; 1974 } else if (!strncmp(this_opt, "active", 6)) { 1975 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; 1976 } else if (!strncmp(this_opt, "passive", 7)) { 1977 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; 1978 } else if (!strncmp(this_opt, "single", 6)) { 1979 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; 1980 } else if (!strncmp(this_opt, "dual", 4)) { 1981 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; 1982 } else if (!strncmp(this_opt, "4pix", 4)) { 1983 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; 1984 } else if (!strncmp(this_opt, "8pix", 4)) { 1985 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; 1986 } else { 1987 dev_err(dev, "unknown option: %s\n", this_opt); 1988 return -EINVAL; 1989 } 1990 1991 if (s[0] != '\0') 1992 dev_info(dev, "override %s", s); 1993 1994 return 0; 1995 } 1996 1997 static int pxafb_parse_options(struct device *dev, char *options, 1998 struct pxafb_mach_info *inf) 1999 { 2000 char *this_opt; 2001 int ret; 2002 2003 if (!options || !*options) 2004 return 0; 2005 2006 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); 2007 2008 /* could be made table driven or similar?... */ 2009 while ((this_opt = strsep(&options, ",")) != NULL) { 2010 ret = parse_opt(dev, this_opt, inf); 2011 if (ret) 2012 return ret; 2013 } 2014 return 0; 2015 } 2016 2017 static char g_options[256] = ""; 2018 2019 #ifndef MODULE 2020 static int __init pxafb_setup_options(void) 2021 { 2022 char *options = NULL; 2023 2024 if (fb_get_options("pxafb", &options)) 2025 return -ENODEV; 2026 2027 if (options) 2028 strscpy(g_options, options, sizeof(g_options)); 2029 2030 return 0; 2031 } 2032 #else 2033 #define pxafb_setup_options() (0) 2034 2035 module_param_string(options, g_options, sizeof(g_options), 0); 2036 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.rst)"); 2037 #endif 2038 2039 #else 2040 #define pxafb_parse_options(...) (0) 2041 #define pxafb_setup_options() (0) 2042 #endif 2043 2044 #ifdef DEBUG_VAR 2045 /* Check for various illegal bit-combinations. Currently only 2046 * a warning is given. */ 2047 static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf) 2048 { 2049 if (inf->lcd_conn) 2050 return; 2051 2052 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) 2053 dev_warn(dev, "machine LCCR0 setting contains " 2054 "illegal bits: %08x\n", 2055 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); 2056 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) 2057 dev_warn(dev, "machine LCCR3 setting contains " 2058 "illegal bits: %08x\n", 2059 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); 2060 if (inf->lccr0 & LCCR0_DPD && 2061 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || 2062 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || 2063 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) 2064 dev_warn(dev, "Double Pixel Data (DPD) mode is " 2065 "only valid in passive mono" 2066 " single panel mode\n"); 2067 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && 2068 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) 2069 dev_warn(dev, "Dual panel only valid in passive mode\n"); 2070 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && 2071 (inf->modes->upper_margin || inf->modes->lower_margin)) 2072 dev_warn(dev, "Upper and lower margins must be 0 in " 2073 "passive mode\n"); 2074 } 2075 #else 2076 #define pxafb_check_options(...) do {} while (0) 2077 #endif 2078 2079 #if defined(CONFIG_OF) 2080 static const char * const lcd_types[] = { 2081 "unknown", "mono-stn", "mono-dstn", "color-stn", "color-dstn", 2082 "color-tft", "smart-panel", NULL 2083 }; 2084 2085 static int of_get_pxafb_display(struct device *dev, struct device_node *disp, 2086 struct pxafb_mach_info *info, u32 bus_width) 2087 { 2088 struct display_timings *timings; 2089 struct videomode vm; 2090 int i, ret = -EINVAL; 2091 const char *s; 2092 2093 ret = of_property_read_string(disp, "lcd-type", &s); 2094 if (ret) 2095 s = "color-tft"; 2096 2097 i = match_string(lcd_types, -1, s); 2098 if (i < 0) { 2099 dev_err(dev, "lcd-type %s is unknown\n", s); 2100 return i; 2101 } 2102 info->lcd_conn |= LCD_CONN_TYPE(i); 2103 info->lcd_conn |= LCD_CONN_WIDTH(bus_width); 2104 2105 timings = of_get_display_timings(disp); 2106 if (!timings) 2107 return -EINVAL; 2108 2109 ret = -ENOMEM; 2110 info->modes = devm_kcalloc(dev, timings->num_timings, 2111 sizeof(info->modes[0]), 2112 GFP_KERNEL); 2113 if (!info->modes) 2114 goto out; 2115 info->num_modes = timings->num_timings; 2116 2117 for (i = 0; i < timings->num_timings; i++) { 2118 ret = videomode_from_timings(timings, &vm, i); 2119 if (ret) { 2120 dev_err(dev, "videomode_from_timings %d failed: %d\n", 2121 i, ret); 2122 goto out; 2123 } 2124 if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) 2125 info->lcd_conn |= LCD_PCLK_EDGE_RISE; 2126 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 2127 info->lcd_conn |= LCD_PCLK_EDGE_FALL; 2128 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 2129 info->lcd_conn |= LCD_BIAS_ACTIVE_HIGH; 2130 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 2131 info->lcd_conn |= LCD_BIAS_ACTIVE_LOW; 2132 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 2133 info->modes[i].sync |= FB_SYNC_HOR_HIGH_ACT; 2134 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 2135 info->modes[i].sync |= FB_SYNC_VERT_HIGH_ACT; 2136 2137 info->modes[i].pixclock = 1000000000UL / (vm.pixelclock / 1000); 2138 info->modes[i].xres = vm.hactive; 2139 info->modes[i].yres = vm.vactive; 2140 info->modes[i].hsync_len = vm.hsync_len; 2141 info->modes[i].left_margin = vm.hback_porch; 2142 info->modes[i].right_margin = vm.hfront_porch; 2143 info->modes[i].vsync_len = vm.vsync_len; 2144 info->modes[i].upper_margin = vm.vback_porch; 2145 info->modes[i].lower_margin = vm.vfront_porch; 2146 } 2147 ret = 0; 2148 2149 out: 2150 display_timings_release(timings); 2151 return ret; 2152 } 2153 2154 static int of_get_pxafb_mode_info(struct device *dev, 2155 struct pxafb_mach_info *info) 2156 { 2157 struct device_node *display, *np; 2158 u32 bus_width; 2159 int ret, i; 2160 2161 np = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 2162 if (!np) { 2163 dev_err(dev, "could not find endpoint\n"); 2164 return -EINVAL; 2165 } 2166 ret = of_property_read_u32(np, "bus-width", &bus_width); 2167 if (ret) { 2168 dev_err(dev, "no bus-width specified: %d\n", ret); 2169 of_node_put(np); 2170 return ret; 2171 } 2172 2173 display = of_graph_get_remote_port_parent(np); 2174 of_node_put(np); 2175 if (!display) { 2176 dev_err(dev, "no display defined\n"); 2177 return -EINVAL; 2178 } 2179 2180 ret = of_get_pxafb_display(dev, display, info, bus_width); 2181 of_node_put(display); 2182 if (ret) 2183 return ret; 2184 2185 for (i = 0; i < info->num_modes; i++) 2186 info->modes[i].bpp = bus_width; 2187 2188 return 0; 2189 } 2190 2191 static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev) 2192 { 2193 int ret; 2194 struct pxafb_mach_info *info; 2195 2196 if (!dev->of_node) 2197 return NULL; 2198 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 2199 if (!info) 2200 return ERR_PTR(-ENOMEM); 2201 ret = of_get_pxafb_mode_info(dev, info); 2202 if (ret) 2203 return ERR_PTR(ret); 2204 2205 /* 2206 * On purpose, neither lccrX registers nor video memory size can be 2207 * specified through device-tree, they are considered more a debug hack 2208 * available through command line. 2209 */ 2210 return info; 2211 } 2212 #else 2213 static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev) 2214 { 2215 return NULL; 2216 } 2217 #endif 2218 2219 static int pxafb_probe(struct platform_device *dev) 2220 { 2221 struct pxafb_info *fbi; 2222 struct pxafb_mach_info *inf, *pdata; 2223 int irq, ret; 2224 2225 dev_dbg(&dev->dev, "pxafb_probe\n"); 2226 2227 ret = -ENOMEM; 2228 pdata = dev_get_platdata(&dev->dev); 2229 if (pdata) { 2230 inf = devm_kmemdup(&dev->dev, pdata, sizeof(*pdata), GFP_KERNEL); 2231 if (!inf) 2232 goto failed; 2233 2234 inf->modes = devm_kmemdup_array(&dev->dev, pdata->modes, pdata->num_modes, 2235 sizeof(*pdata->modes), GFP_KERNEL); 2236 if (!inf->modes) 2237 goto failed; 2238 } else { 2239 inf = of_pxafb_of_mach_info(&dev->dev); 2240 if (IS_ERR_OR_NULL(inf)) 2241 goto failed; 2242 } 2243 2244 ret = pxafb_parse_options(&dev->dev, g_options, inf); 2245 if (ret < 0) 2246 goto failed; 2247 2248 pxafb_check_options(&dev->dev, inf); 2249 2250 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n", 2251 inf->modes->xres, 2252 inf->modes->yres, 2253 inf->modes->bpp); 2254 if (inf->modes->xres == 0 || 2255 inf->modes->yres == 0 || 2256 inf->modes->bpp == 0) { 2257 dev_err(&dev->dev, "Invalid resolution or bit depth\n"); 2258 ret = -EINVAL; 2259 goto failed; 2260 } 2261 2262 fbi = pxafb_init_fbinfo(&dev->dev, inf); 2263 if (IS_ERR(fbi)) { 2264 dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); 2265 ret = PTR_ERR(fbi); 2266 goto failed; 2267 } 2268 2269 if (cpu_is_pxa3xx() && inf->acceleration_enabled) 2270 fbi->fb.fix.accel = FB_ACCEL_PXA3XX; 2271 2272 fbi->backlight_power = inf->pxafb_backlight_power; 2273 fbi->lcd_power = inf->pxafb_lcd_power; 2274 2275 fbi->lcd_supply = devm_regulator_get_optional(&dev->dev, "lcd"); 2276 if (IS_ERR(fbi->lcd_supply)) { 2277 if (PTR_ERR(fbi->lcd_supply) == -EPROBE_DEFER) 2278 return -EPROBE_DEFER; 2279 2280 fbi->lcd_supply = NULL; 2281 } 2282 2283 fbi->mmio_base = devm_platform_ioremap_resource(dev, 0); 2284 if (IS_ERR(fbi->mmio_base)) { 2285 dev_err(&dev->dev, "failed to get I/O memory\n"); 2286 ret = PTR_ERR(fbi->mmio_base); 2287 goto failed; 2288 } 2289 2290 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff)); 2291 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size, 2292 &fbi->dma_buff_phys, GFP_KERNEL); 2293 if (fbi->dma_buff == NULL) { 2294 dev_err(&dev->dev, "failed to allocate memory for DMA\n"); 2295 ret = -ENOMEM; 2296 goto failed; 2297 } 2298 2299 ret = pxafb_init_video_memory(fbi); 2300 if (ret) { 2301 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); 2302 ret = -ENOMEM; 2303 goto failed_free_dma; 2304 } 2305 2306 irq = platform_get_irq(dev, 0); 2307 if (irq < 0) { 2308 ret = -ENODEV; 2309 goto failed_free_mem; 2310 } 2311 2312 ret = devm_request_irq(&dev->dev, irq, pxafb_handle_irq, 0, "LCD", fbi); 2313 if (ret) { 2314 dev_err(&dev->dev, "request_irq failed: %d\n", ret); 2315 ret = -EBUSY; 2316 goto failed_free_mem; 2317 } 2318 2319 ret = pxafb_smart_init(fbi); 2320 if (ret) { 2321 dev_err(&dev->dev, "failed to initialize smartpanel\n"); 2322 goto failed_free_mem; 2323 } 2324 2325 /* 2326 * This makes sure that our colour bitfield 2327 * descriptors are correctly initialised. 2328 */ 2329 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb); 2330 if (ret) { 2331 dev_err(&dev->dev, "failed to get suitable mode\n"); 2332 goto failed_free_mem; 2333 } 2334 2335 ret = pxafb_set_par(&fbi->fb); 2336 if (ret) { 2337 dev_err(&dev->dev, "Failed to set parameters\n"); 2338 goto failed_free_mem; 2339 } 2340 2341 platform_set_drvdata(dev, fbi); 2342 2343 ret = register_framebuffer(&fbi->fb); 2344 if (ret < 0) { 2345 dev_err(&dev->dev, 2346 "Failed to register framebuffer device: %d\n", ret); 2347 goto failed_free_cmap; 2348 } 2349 2350 pxafb_overlay_init(fbi); 2351 2352 #ifdef CONFIG_CPU_FREQ 2353 fbi->freq_transition.notifier_call = pxafb_freq_transition; 2354 cpufreq_register_notifier(&fbi->freq_transition, 2355 CPUFREQ_TRANSITION_NOTIFIER); 2356 #endif 2357 2358 /* 2359 * Ok, now enable the LCD controller 2360 */ 2361 set_ctrlr_state(fbi, C_ENABLE); 2362 2363 return 0; 2364 2365 failed_free_cmap: 2366 if (fbi->fb.cmap.len) 2367 fb_dealloc_cmap(&fbi->fb.cmap); 2368 failed_free_mem: 2369 free_pages_exact(fbi->video_mem, fbi->video_mem_size); 2370 failed_free_dma: 2371 dma_free_coherent(&dev->dev, fbi->dma_buff_size, 2372 fbi->dma_buff, fbi->dma_buff_phys); 2373 failed: 2374 return ret; 2375 } 2376 2377 static void pxafb_remove(struct platform_device *dev) 2378 { 2379 struct pxafb_info *fbi = platform_get_drvdata(dev); 2380 struct fb_info *info; 2381 2382 if (!fbi) 2383 return; 2384 2385 info = &fbi->fb; 2386 2387 pxafb_overlay_exit(fbi); 2388 cancel_work_sync(&fbi->task); 2389 unregister_framebuffer(info); 2390 2391 pxafb_disable_controller(fbi); 2392 2393 if (fbi->fb.cmap.len) 2394 fb_dealloc_cmap(&fbi->fb.cmap); 2395 2396 free_pages_exact(fbi->video_mem, fbi->video_mem_size); 2397 2398 dma_free_coherent(&dev->dev, fbi->dma_buff_size, fbi->dma_buff, 2399 fbi->dma_buff_phys); 2400 } 2401 2402 static const struct of_device_id pxafb_of_dev_id[] = { 2403 { .compatible = "marvell,pxa270-lcdc", }, 2404 { .compatible = "marvell,pxa300-lcdc", }, 2405 { .compatible = "marvell,pxa2xx-lcdc", }, 2406 { /* sentinel */ } 2407 }; 2408 MODULE_DEVICE_TABLE(of, pxafb_of_dev_id); 2409 2410 static struct platform_driver pxafb_driver = { 2411 .probe = pxafb_probe, 2412 .remove = pxafb_remove, 2413 .driver = { 2414 .name = "pxa2xx-fb", 2415 .of_match_table = pxafb_of_dev_id, 2416 #ifdef CONFIG_PM 2417 .pm = &pxafb_pm_ops, 2418 #endif 2419 }, 2420 }; 2421 2422 static int __init pxafb_init(void) 2423 { 2424 if (pxafb_setup_options()) 2425 return -EINVAL; 2426 2427 return platform_driver_register(&pxafb_driver); 2428 } 2429 2430 static void __exit pxafb_exit(void) 2431 { 2432 platform_driver_unregister(&pxafb_driver); 2433 } 2434 2435 module_init(pxafb_init); 2436 module_exit(pxafb_exit); 2437 2438 MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); 2439 MODULE_LICENSE("GPL"); 2440