1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * OMAP1 Special OptimiSed Screen Interface support 4 * 5 * Copyright (C) 2004-2005 Nokia Corporation 6 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 7 */ 8 #include <linux/module.h> 9 #include <linux/mm.h> 10 #include <linux/clk.h> 11 #include <linux/irq.h> 12 #include <linux/io.h> 13 #include <linux/interrupt.h> 14 15 #include <linux/omap-dma.h> 16 17 #include "omapfb.h" 18 #include "lcd_dma.h" 19 #include "lcdc.h" 20 21 #define MODULE_NAME "omapfb-sossi" 22 23 #define OMAP_SOSSI_BASE 0xfffbac00 24 #define SOSSI_ID_REG 0x00 25 #define SOSSI_INIT1_REG 0x04 26 #define SOSSI_INIT2_REG 0x08 27 #define SOSSI_INIT3_REG 0x0c 28 #define SOSSI_FIFO_REG 0x10 29 #define SOSSI_REOTABLE_REG 0x14 30 #define SOSSI_TEARING_REG 0x18 31 #define SOSSI_INIT1B_REG 0x1c 32 #define SOSSI_FIFOB_REG 0x20 33 34 #define DMA_GSCR 0xfffedc04 35 #define DMA_LCD_CCR 0xfffee3c2 36 #define DMA_LCD_CTRL 0xfffee3c4 37 #define DMA_LCD_LCH_CTRL 0xfffee3ea 38 39 #define CONF_SOSSI_RESET_R (1 << 23) 40 41 #define RD_ACCESS 0 42 #define WR_ACCESS 1 43 44 #define SOSSI_MAX_XMIT_BYTES (512 * 1024) 45 46 static struct { 47 void __iomem *base; 48 struct clk *fck; 49 unsigned long fck_hz; 50 spinlock_t lock; 51 int bus_pick_count; 52 int bus_pick_width; 53 int tearsync_mode; 54 int tearsync_line; 55 void (*lcdc_callback)(void *data); 56 void *lcdc_callback_data; 57 int vsync_dma_pending; 58 /* timing for read and write access */ 59 int clk_div; 60 u8 clk_tw0[2]; 61 u8 clk_tw1[2]; 62 /* 63 * if last_access is the same as current we don't have to change 64 * the timings 65 */ 66 int last_access; 67 68 struct omapfb_device *fbdev; 69 } sossi; 70 71 static inline u32 sossi_read_reg(int reg) 72 { 73 return readl(sossi.base + reg); 74 } 75 76 static inline u16 sossi_read_reg16(int reg) 77 { 78 return readw(sossi.base + reg); 79 } 80 81 static inline u8 sossi_read_reg8(int reg) 82 { 83 return readb(sossi.base + reg); 84 } 85 86 static inline void sossi_write_reg(int reg, u32 value) 87 { 88 writel(value, sossi.base + reg); 89 } 90 91 static inline void sossi_write_reg16(int reg, u16 value) 92 { 93 writew(value, sossi.base + reg); 94 } 95 96 static inline void sossi_write_reg8(int reg, u8 value) 97 { 98 writeb(value, sossi.base + reg); 99 } 100 101 static void sossi_set_bits(int reg, u32 bits) 102 { 103 sossi_write_reg(reg, sossi_read_reg(reg) | bits); 104 } 105 106 static void sossi_clear_bits(int reg, u32 bits) 107 { 108 sossi_write_reg(reg, sossi_read_reg(reg) & ~bits); 109 } 110 111 #define HZ_TO_PS(x) (1000000000 / (x / 1000)) 112 113 static u32 ps_to_sossi_ticks(u32 ps, int div) 114 { 115 u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div; 116 return (clk_period + ps - 1) / clk_period; 117 } 118 119 static int calc_rd_timings(struct extif_timings *t) 120 { 121 u32 tw0, tw1; 122 int reon, reoff, recyc, actim; 123 int div = t->clk_div; 124 125 /* 126 * Make sure that after conversion it still holds that: 127 * reoff > reon, recyc >= reoff, actim > reon 128 */ 129 reon = ps_to_sossi_ticks(t->re_on_time, div); 130 /* reon will be exactly one sossi tick */ 131 if (reon > 1) 132 return -1; 133 134 reoff = ps_to_sossi_ticks(t->re_off_time, div); 135 136 if (reoff <= reon) 137 reoff = reon + 1; 138 139 tw0 = reoff - reon; 140 if (tw0 > 0x10) 141 return -1; 142 143 recyc = ps_to_sossi_ticks(t->re_cycle_time, div); 144 if (recyc <= reoff) 145 recyc = reoff + 1; 146 147 tw1 = recyc - tw0; 148 /* values less then 3 result in the SOSSI block resetting itself */ 149 if (tw1 < 3) 150 tw1 = 3; 151 if (tw1 > 0x40) 152 return -1; 153 154 actim = ps_to_sossi_ticks(t->access_time, div); 155 if (actim < reoff) 156 actim++; 157 /* 158 * access time (data hold time) will be exactly one sossi 159 * tick 160 */ 161 if (actim - reoff > 1) 162 return -1; 163 164 t->tim[0] = tw0 - 1; 165 t->tim[1] = tw1 - 1; 166 167 return 0; 168 } 169 170 static int calc_wr_timings(struct extif_timings *t) 171 { 172 u32 tw0, tw1; 173 int weon, weoff, wecyc; 174 int div = t->clk_div; 175 176 /* 177 * Make sure that after conversion it still holds that: 178 * weoff > weon, wecyc >= weoff 179 */ 180 weon = ps_to_sossi_ticks(t->we_on_time, div); 181 /* weon will be exactly one sossi tick */ 182 if (weon > 1) 183 return -1; 184 185 weoff = ps_to_sossi_ticks(t->we_off_time, div); 186 if (weoff <= weon) 187 weoff = weon + 1; 188 tw0 = weoff - weon; 189 if (tw0 > 0x10) 190 return -1; 191 192 wecyc = ps_to_sossi_ticks(t->we_cycle_time, div); 193 if (wecyc <= weoff) 194 wecyc = weoff + 1; 195 196 tw1 = wecyc - tw0; 197 /* values less then 3 result in the SOSSI block resetting itself */ 198 if (tw1 < 3) 199 tw1 = 3; 200 if (tw1 > 0x40) 201 return -1; 202 203 t->tim[2] = tw0 - 1; 204 t->tim[3] = tw1 - 1; 205 206 return 0; 207 } 208 209 static void _set_timing(int div, int tw0, int tw1) 210 { 211 u32 l; 212 213 #ifdef VERBOSE 214 dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n", 215 tw0 + 1, tw1 + 1, div); 216 #endif 217 218 clk_set_rate(sossi.fck, sossi.fck_hz / div); 219 clk_enable(sossi.fck); 220 l = sossi_read_reg(SOSSI_INIT1_REG); 221 l &= ~((0x0f << 20) | (0x3f << 24)); 222 l |= (tw0 << 20) | (tw1 << 24); 223 sossi_write_reg(SOSSI_INIT1_REG, l); 224 clk_disable(sossi.fck); 225 } 226 227 static void _set_bits_per_cycle(int bus_pick_count, int bus_pick_width) 228 { 229 u32 l; 230 231 l = sossi_read_reg(SOSSI_INIT3_REG); 232 l &= ~0x3ff; 233 l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f); 234 sossi_write_reg(SOSSI_INIT3_REG, l); 235 } 236 237 static void _set_tearsync_mode(int mode, unsigned line) 238 { 239 u32 l; 240 241 l = sossi_read_reg(SOSSI_TEARING_REG); 242 l &= ~(((1 << 11) - 1) << 15); 243 l |= line << 15; 244 l &= ~(0x3 << 26); 245 l |= mode << 26; 246 sossi_write_reg(SOSSI_TEARING_REG, l); 247 if (mode) 248 sossi_set_bits(SOSSI_INIT2_REG, 1 << 6); /* TE logic */ 249 else 250 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 6); 251 } 252 253 static inline void set_timing(int access) 254 { 255 if (access != sossi.last_access) { 256 sossi.last_access = access; 257 _set_timing(sossi.clk_div, 258 sossi.clk_tw0[access], sossi.clk_tw1[access]); 259 } 260 } 261 262 static void sossi_start_transfer(void) 263 { 264 /* WE */ 265 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4); 266 /* CS active low */ 267 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30); 268 } 269 270 static void sossi_stop_transfer(void) 271 { 272 /* WE */ 273 sossi_set_bits(SOSSI_INIT2_REG, 1 << 4); 274 /* CS active low */ 275 sossi_set_bits(SOSSI_INIT1_REG, 1 << 30); 276 } 277 278 static void wait_end_of_write(void) 279 { 280 /* Before reading we must check if some writings are going on */ 281 while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3))); 282 } 283 284 static void send_data(const void *data, unsigned int len) 285 { 286 while (len >= 4) { 287 sossi_write_reg(SOSSI_FIFO_REG, *(const u32 *) data); 288 len -= 4; 289 data += 4; 290 } 291 while (len >= 2) { 292 sossi_write_reg16(SOSSI_FIFO_REG, *(const u16 *) data); 293 len -= 2; 294 data += 2; 295 } 296 while (len) { 297 sossi_write_reg8(SOSSI_FIFO_REG, *(const u8 *) data); 298 len--; 299 data++; 300 } 301 } 302 303 static void set_cycles(unsigned int len) 304 { 305 unsigned long nr_cycles = len / (sossi.bus_pick_width / 8); 306 307 BUG_ON((nr_cycles - 1) & ~0x3ffff); 308 309 sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff); 310 sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff); 311 } 312 313 static int sossi_convert_timings(struct extif_timings *t) 314 { 315 int r = 0; 316 int div = t->clk_div; 317 318 t->converted = 0; 319 320 if (div <= 0 || div > 8) 321 return -1; 322 323 /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */ 324 if ((r = calc_rd_timings(t)) < 0) 325 return r; 326 327 if ((r = calc_wr_timings(t)) < 0) 328 return r; 329 330 t->tim[4] = div; 331 332 t->converted = 1; 333 334 return 0; 335 } 336 337 static void sossi_set_timings(const struct extif_timings *t) 338 { 339 BUG_ON(!t->converted); 340 341 sossi.clk_tw0[RD_ACCESS] = t->tim[0]; 342 sossi.clk_tw1[RD_ACCESS] = t->tim[1]; 343 344 sossi.clk_tw0[WR_ACCESS] = t->tim[2]; 345 sossi.clk_tw1[WR_ACCESS] = t->tim[3]; 346 347 sossi.clk_div = t->tim[4]; 348 } 349 350 static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div) 351 { 352 *clk_period = HZ_TO_PS(sossi.fck_hz); 353 *max_clk_div = 8; 354 } 355 356 static void sossi_set_bits_per_cycle(int bpc) 357 { 358 int bus_pick_count, bus_pick_width; 359 360 /* 361 * We set explicitly the the bus_pick_count as well, although 362 * with remapping/reordering disabled it will be calculated by HW 363 * as (32 / bus_pick_width). 364 */ 365 switch (bpc) { 366 case 8: 367 bus_pick_count = 4; 368 bus_pick_width = 8; 369 break; 370 case 16: 371 bus_pick_count = 2; 372 bus_pick_width = 16; 373 break; 374 default: 375 BUG(); 376 return; 377 } 378 sossi.bus_pick_width = bus_pick_width; 379 sossi.bus_pick_count = bus_pick_count; 380 } 381 382 static int sossi_setup_tearsync(unsigned pin_cnt, 383 unsigned hs_pulse_time, unsigned vs_pulse_time, 384 int hs_pol_inv, int vs_pol_inv, int div) 385 { 386 int hs, vs; 387 u32 l; 388 389 if (pin_cnt != 1 || div < 1 || div > 8) 390 return -EINVAL; 391 392 hs = ps_to_sossi_ticks(hs_pulse_time, div); 393 vs = ps_to_sossi_ticks(vs_pulse_time, div); 394 if (vs < 8 || vs <= hs || vs >= (1 << 12)) 395 return -EDOM; 396 vs /= 8; 397 vs--; 398 if (hs > 8) 399 hs = 8; 400 if (hs) 401 hs--; 402 403 dev_dbg(sossi.fbdev->dev, 404 "setup_tearsync: hs %d vs %d hs_inv %d vs_inv %d\n", 405 hs, vs, hs_pol_inv, vs_pol_inv); 406 407 clk_enable(sossi.fck); 408 l = sossi_read_reg(SOSSI_TEARING_REG); 409 l &= ~((1 << 15) - 1); 410 l |= vs << 3; 411 l |= hs; 412 if (hs_pol_inv) 413 l |= 1 << 29; 414 else 415 l &= ~(1 << 29); 416 if (vs_pol_inv) 417 l |= 1 << 28; 418 else 419 l &= ~(1 << 28); 420 sossi_write_reg(SOSSI_TEARING_REG, l); 421 clk_disable(sossi.fck); 422 423 return 0; 424 } 425 426 static int sossi_enable_tearsync(int enable, unsigned line) 427 { 428 int mode; 429 430 dev_dbg(sossi.fbdev->dev, "tearsync %d line %d\n", enable, line); 431 if (line >= 1 << 11) 432 return -EINVAL; 433 if (enable) { 434 if (line) 435 mode = 2; /* HS or VS */ 436 else 437 mode = 3; /* VS only */ 438 } else 439 mode = 0; 440 sossi.tearsync_line = line; 441 sossi.tearsync_mode = mode; 442 443 return 0; 444 } 445 446 static void sossi_write_command(const void *data, unsigned int len) 447 { 448 clk_enable(sossi.fck); 449 set_timing(WR_ACCESS); 450 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width); 451 /* CMD#/DATA */ 452 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18); 453 set_cycles(len); 454 sossi_start_transfer(); 455 send_data(data, len); 456 sossi_stop_transfer(); 457 wait_end_of_write(); 458 clk_disable(sossi.fck); 459 } 460 461 static void sossi_write_data(const void *data, unsigned int len) 462 { 463 clk_enable(sossi.fck); 464 set_timing(WR_ACCESS); 465 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width); 466 /* CMD#/DATA */ 467 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18); 468 set_cycles(len); 469 sossi_start_transfer(); 470 send_data(data, len); 471 sossi_stop_transfer(); 472 wait_end_of_write(); 473 clk_disable(sossi.fck); 474 } 475 476 static void sossi_transfer_area(int width, int height, 477 void (callback)(void *data), void *data) 478 { 479 BUG_ON(callback == NULL); 480 481 sossi.lcdc_callback = callback; 482 sossi.lcdc_callback_data = data; 483 484 clk_enable(sossi.fck); 485 set_timing(WR_ACCESS); 486 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width); 487 _set_tearsync_mode(sossi.tearsync_mode, sossi.tearsync_line); 488 /* CMD#/DATA */ 489 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18); 490 set_cycles(width * height * sossi.bus_pick_width / 8); 491 492 sossi_start_transfer(); 493 if (sossi.tearsync_mode) { 494 /* 495 * Wait for the sync signal and start the transfer only 496 * then. We can't seem to be able to use HW sync DMA for 497 * this since LCD DMA shows huge latencies, as if it 498 * would ignore some of the DMA requests from SoSSI. 499 */ 500 unsigned long flags; 501 502 spin_lock_irqsave(&sossi.lock, flags); 503 sossi.vsync_dma_pending++; 504 spin_unlock_irqrestore(&sossi.lock, flags); 505 } else 506 /* Just start the transfer right away. */ 507 omap_enable_lcd_dma(); 508 } 509 510 static void sossi_dma_callback(void *data) 511 { 512 omap_stop_lcd_dma(); 513 sossi_stop_transfer(); 514 clk_disable(sossi.fck); 515 sossi.lcdc_callback(sossi.lcdc_callback_data); 516 } 517 518 static void sossi_read_data(void *data, unsigned int len) 519 { 520 clk_enable(sossi.fck); 521 set_timing(RD_ACCESS); 522 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width); 523 /* CMD#/DATA */ 524 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18); 525 set_cycles(len); 526 sossi_start_transfer(); 527 while (len >= 4) { 528 *(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG); 529 len -= 4; 530 data += 4; 531 } 532 while (len >= 2) { 533 *(u16 *) data = sossi_read_reg16(SOSSI_FIFO_REG); 534 len -= 2; 535 data += 2; 536 } 537 while (len) { 538 *(u8 *) data = sossi_read_reg8(SOSSI_FIFO_REG); 539 len--; 540 data++; 541 } 542 sossi_stop_transfer(); 543 clk_disable(sossi.fck); 544 } 545 546 static irqreturn_t sossi_match_irq(int irq, void *data) 547 { 548 unsigned long flags; 549 550 spin_lock_irqsave(&sossi.lock, flags); 551 if (sossi.vsync_dma_pending) { 552 sossi.vsync_dma_pending--; 553 omap_enable_lcd_dma(); 554 } 555 spin_unlock_irqrestore(&sossi.lock, flags); 556 return IRQ_HANDLED; 557 } 558 559 static int sossi_init(struct omapfb_device *fbdev) 560 { 561 u32 l, k; 562 struct clk *fck; 563 struct clk *dpll1out_ck; 564 int r; 565 566 sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K); 567 if (!sossi.base) { 568 dev_err(fbdev->dev, "can't ioremap SoSSI\n"); 569 return -ENOMEM; 570 } 571 572 sossi.fbdev = fbdev; 573 spin_lock_init(&sossi.lock); 574 575 dpll1out_ck = clk_get(fbdev->dev, "ck_dpll1out"); 576 if (IS_ERR(dpll1out_ck)) { 577 dev_err(fbdev->dev, "can't get DPLL1OUT clock\n"); 578 return PTR_ERR(dpll1out_ck); 579 } 580 /* 581 * We need the parent clock rate, which we might divide further 582 * depending on the timing requirements of the controller. See 583 * _set_timings. 584 */ 585 sossi.fck_hz = clk_get_rate(dpll1out_ck); 586 clk_put(dpll1out_ck); 587 588 fck = clk_get(fbdev->dev, "ck_sossi"); 589 if (IS_ERR(fck)) { 590 dev_err(fbdev->dev, "can't get SoSSI functional clock\n"); 591 return PTR_ERR(fck); 592 } 593 sossi.fck = fck; 594 595 /* Reset and enable the SoSSI module */ 596 l = omap_readl(MOD_CONF_CTRL_1); 597 l |= CONF_SOSSI_RESET_R; 598 omap_writel(l, MOD_CONF_CTRL_1); 599 l &= ~CONF_SOSSI_RESET_R; 600 omap_writel(l, MOD_CONF_CTRL_1); 601 602 clk_enable(sossi.fck); 603 l = omap_readl(ARM_IDLECT2); 604 l &= ~(1 << 8); /* DMACK_REQ */ 605 omap_writel(l, ARM_IDLECT2); 606 607 l = sossi_read_reg(SOSSI_INIT2_REG); 608 /* Enable and reset the SoSSI block */ 609 l |= (1 << 0) | (1 << 1); 610 sossi_write_reg(SOSSI_INIT2_REG, l); 611 /* Take SoSSI out of reset */ 612 l &= ~(1 << 1); 613 sossi_write_reg(SOSSI_INIT2_REG, l); 614 615 sossi_write_reg(SOSSI_ID_REG, 0); 616 l = sossi_read_reg(SOSSI_ID_REG); 617 k = sossi_read_reg(SOSSI_ID_REG); 618 619 if (l != 0x55555555 || k != 0xaaaaaaaa) { 620 dev_err(fbdev->dev, 621 "invalid SoSSI sync pattern: %08x, %08x\n", l, k); 622 r = -ENODEV; 623 goto err; 624 } 625 626 if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) { 627 dev_err(fbdev->dev, "can't get LCDC IRQ\n"); 628 r = -ENODEV; 629 goto err; 630 } 631 632 l = sossi_read_reg(SOSSI_ID_REG); /* Component code */ 633 l = sossi_read_reg(SOSSI_ID_REG); 634 dev_info(fbdev->dev, "SoSSI version %d.%d initialized\n", 635 l >> 16, l & 0xffff); 636 637 l = sossi_read_reg(SOSSI_INIT1_REG); 638 l |= (1 << 19); /* DMA_MODE */ 639 l &= ~(1 << 31); /* REORDERING */ 640 sossi_write_reg(SOSSI_INIT1_REG, l); 641 642 if ((r = request_irq(fbdev->ext_irq, sossi_match_irq, 643 IRQ_TYPE_EDGE_FALLING, 644 "sossi_match", sossi.fbdev->dev)) < 0) { 645 dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n"); 646 goto err; 647 } 648 649 clk_disable(sossi.fck); 650 return 0; 651 652 err: 653 clk_disable(sossi.fck); 654 clk_put(sossi.fck); 655 return r; 656 } 657 658 static void sossi_cleanup(void) 659 { 660 omap_lcdc_free_dma_callback(); 661 clk_put(sossi.fck); 662 iounmap(sossi.base); 663 } 664 665 struct lcd_ctrl_extif omap1_ext_if = { 666 .init = sossi_init, 667 .cleanup = sossi_cleanup, 668 .get_clk_info = sossi_get_clk_info, 669 .convert_timings = sossi_convert_timings, 670 .set_timings = sossi_set_timings, 671 .set_bits_per_cycle = sossi_set_bits_per_cycle, 672 .setup_tearsync = sossi_setup_tearsync, 673 .enable_tearsync = sossi_enable_tearsync, 674 .write_command = sossi_write_command, 675 .read_data = sossi_read_data, 676 .write_data = sossi_write_data, 677 .transfer_area = sossi_transfer_area, 678 679 .max_transmit_size = SOSSI_MAX_XMIT_BYTES, 680 }; 681 682