1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/mb862xx/mb862xxfb.c 4 * 5 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver 6 * 7 * (C) 2008 Anatolij Gustschin <agust@denx.de> 8 * DENX Software Engineering 9 */ 10 11 #undef DEBUG 12 13 #include <linux/aperture.h> 14 #include <linux/fb.h> 15 #include <linux/delay.h> 16 #include <linux/uaccess.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/pci.h> 21 #if defined(CONFIG_OF) 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #endif 26 #include "mb862xxfb.h" 27 #include "mb862xx_reg.h" 28 29 #define NR_PALETTE 256 30 #define MB862XX_MEM_SIZE 0x1000000 31 #define CORALP_MEM_SIZE 0x2000000 32 #define CARMINE_MEM_SIZE 0x8000000 33 #define DRV_NAME "mb862xxfb" 34 35 #if defined(CONFIG_SOCRATES) 36 static struct mb862xx_gc_mode socrates_gc_mode = { 37 /* Mode for Prime View PM070WL4 TFT LCD Panel */ 38 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 }, 39 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */ 40 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63 41 }; 42 #endif 43 44 /* Helpers */ 45 static inline int h_total(struct fb_var_screeninfo *var) 46 { 47 return var->xres + var->left_margin + 48 var->right_margin + var->hsync_len; 49 } 50 51 static inline int v_total(struct fb_var_screeninfo *var) 52 { 53 return var->yres + var->upper_margin + 54 var->lower_margin + var->vsync_len; 55 } 56 57 static inline int hsp(struct fb_var_screeninfo *var) 58 { 59 return var->xres + var->right_margin - 1; 60 } 61 62 static inline int vsp(struct fb_var_screeninfo *var) 63 { 64 return var->yres + var->lower_margin - 1; 65 } 66 67 static inline int d_pitch(struct fb_var_screeninfo *var) 68 { 69 return var->xres * var->bits_per_pixel / 8; 70 } 71 72 static inline unsigned int chan_to_field(unsigned int chan, 73 struct fb_bitfield *bf) 74 { 75 chan &= 0xffff; 76 chan >>= 16 - bf->length; 77 return chan << bf->offset; 78 } 79 80 static int mb862xxfb_setcolreg(unsigned regno, 81 unsigned red, unsigned green, unsigned blue, 82 unsigned transp, struct fb_info *info) 83 { 84 struct mb862xxfb_par *par = info->par; 85 unsigned int val; 86 87 switch (info->fix.visual) { 88 case FB_VISUAL_TRUECOLOR: 89 if (regno < 16) { 90 val = chan_to_field(red, &info->var.red); 91 val |= chan_to_field(green, &info->var.green); 92 val |= chan_to_field(blue, &info->var.blue); 93 par->pseudo_palette[regno] = val; 94 } 95 break; 96 case FB_VISUAL_PSEUDOCOLOR: 97 if (regno < 256) { 98 val = (red >> 8) << 16; 99 val |= (green >> 8) << 8; 100 val |= blue >> 8; 101 outreg(disp, GC_L0PAL0 + (regno * 4), val); 102 } 103 break; 104 default: 105 return 1; /* unsupported type */ 106 } 107 return 0; 108 } 109 110 static int mb862xxfb_check_var(struct fb_var_screeninfo *var, 111 struct fb_info *fbi) 112 { 113 unsigned long tmp; 114 115 if (fbi->dev) 116 dev_dbg(fbi->dev, "%s\n", __func__); 117 118 /* check if these values fit into the registers */ 119 if (var->hsync_len > 255 || var->vsync_len > 255) 120 return -EINVAL; 121 122 if ((var->xres + var->right_margin) >= 4096) 123 return -EINVAL; 124 125 if ((var->yres + var->lower_margin) > 4096) 126 return -EINVAL; 127 128 if (h_total(var) > 4096 || v_total(var) > 4096) 129 return -EINVAL; 130 131 if (var->xres_virtual > 4096 || var->yres_virtual > 4096) 132 return -EINVAL; 133 134 if (var->bits_per_pixel <= 8) 135 var->bits_per_pixel = 8; 136 else if (var->bits_per_pixel <= 16) 137 var->bits_per_pixel = 16; 138 else if (var->bits_per_pixel <= 32) 139 var->bits_per_pixel = 32; 140 141 /* 142 * can cope with 8,16 or 24/32bpp if resulting 143 * pitch is divisible by 64 without remainder 144 */ 145 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) { 146 int r; 147 148 var->bits_per_pixel = 0; 149 do { 150 var->bits_per_pixel += 8; 151 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT; 152 } while (r && var->bits_per_pixel <= 32); 153 154 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) 155 return -EINVAL; 156 } 157 158 /* line length is going to be 128 bit aligned */ 159 tmp = (var->xres * var->bits_per_pixel) / 8; 160 if ((tmp & 15) != 0) 161 return -EINVAL; 162 163 /* set r/g/b positions and validate bpp */ 164 switch (var->bits_per_pixel) { 165 case 8: 166 var->red.length = var->bits_per_pixel; 167 var->green.length = var->bits_per_pixel; 168 var->blue.length = var->bits_per_pixel; 169 var->red.offset = 0; 170 var->green.offset = 0; 171 var->blue.offset = 0; 172 var->transp.length = 0; 173 break; 174 case 16: 175 var->red.length = 5; 176 var->green.length = 5; 177 var->blue.length = 5; 178 var->red.offset = 10; 179 var->green.offset = 5; 180 var->blue.offset = 0; 181 var->transp.length = 0; 182 break; 183 case 24: 184 case 32: 185 var->transp.length = 8; 186 var->red.length = 8; 187 var->green.length = 8; 188 var->blue.length = 8; 189 var->transp.offset = 24; 190 var->red.offset = 16; 191 var->green.offset = 8; 192 var->blue.offset = 0; 193 break; 194 default: 195 return -EINVAL; 196 } 197 return 0; 198 } 199 200 static struct fb_ops mb862xxfb_ops; 201 202 /* 203 * set display parameters 204 */ 205 static int mb862xxfb_set_par(struct fb_info *fbi) 206 { 207 struct mb862xxfb_par *par = fbi->par; 208 unsigned long reg, sc; 209 210 dev_dbg(par->dev, "%s\n", __func__); 211 if (par->type == BT_CORALP) 212 mb862xxfb_init_accel(fbi, &mb862xxfb_ops, fbi->var.xres); 213 214 if (par->pre_init) 215 return 0; 216 217 /* disp off */ 218 reg = inreg(disp, GC_DCM1); 219 reg &= ~GC_DCM01_DEN; 220 outreg(disp, GC_DCM1, reg); 221 222 /* set display reference clock div. */ 223 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1; 224 reg = inreg(disp, GC_DCM1); 225 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC); 226 reg |= sc << 8; 227 outreg(disp, GC_DCM1, reg); 228 dev_dbg(par->dev, "SC 0x%lx\n", sc); 229 230 /* disp dimension, format */ 231 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT, 232 (fbi->var.yres - 1)); 233 if (fbi->var.bits_per_pixel == 16) 234 reg |= GC_L0M_L0C_16; 235 outreg(disp, GC_L0M, reg); 236 237 if (fbi->var.bits_per_pixel == 32) { 238 reg = inreg(disp, GC_L0EM); 239 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24); 240 } 241 outreg(disp, GC_WY_WX, 0); 242 reg = pack(fbi->var.yres - 1, fbi->var.xres); 243 outreg(disp, GC_WH_WW, reg); 244 outreg(disp, GC_L0OA0, 0); 245 outreg(disp, GC_L0DA0, 0); 246 outreg(disp, GC_L0DY_L0DX, 0); 247 outreg(disp, GC_L0WY_L0WX, 0); 248 outreg(disp, GC_L0WH_L0WW, reg); 249 250 /* both HW-cursors off */ 251 reg = inreg(disp, GC_CPM_CUTC); 252 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1); 253 outreg(disp, GC_CPM_CUTC, reg); 254 255 /* timings */ 256 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1); 257 outreg(disp, GC_HDB_HDP, reg); 258 reg = pack((fbi->var.yres - 1), vsp(&fbi->var)); 259 outreg(disp, GC_VDP_VSP, reg); 260 reg = ((fbi->var.vsync_len - 1) << 24) | 261 pack((fbi->var.hsync_len - 1), hsp(&fbi->var)); 262 outreg(disp, GC_VSW_HSW_HSP, reg); 263 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0)); 264 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0)); 265 266 /* display on */ 267 reg = inreg(disp, GC_DCM1); 268 reg |= GC_DCM01_DEN | GC_DCM01_L0E; 269 reg &= ~GC_DCM01_ESY; 270 outreg(disp, GC_DCM1, reg); 271 return 0; 272 } 273 274 static int mb862xxfb_pan(struct fb_var_screeninfo *var, 275 struct fb_info *info) 276 { 277 struct mb862xxfb_par *par = info->par; 278 unsigned long reg; 279 280 reg = pack(var->yoffset, var->xoffset); 281 outreg(disp, GC_L0WY_L0WX, reg); 282 283 reg = pack(info->var.yres_virtual, info->var.xres_virtual); 284 outreg(disp, GC_L0WH_L0WW, reg); 285 return 0; 286 } 287 288 static int mb862xxfb_blank(int mode, struct fb_info *fbi) 289 { 290 struct mb862xxfb_par *par = fbi->par; 291 unsigned long reg; 292 293 dev_dbg(fbi->dev, "blank mode=%d\n", mode); 294 295 switch (mode) { 296 case FB_BLANK_POWERDOWN: 297 reg = inreg(disp, GC_DCM1); 298 reg &= ~GC_DCM01_DEN; 299 outreg(disp, GC_DCM1, reg); 300 break; 301 case FB_BLANK_UNBLANK: 302 reg = inreg(disp, GC_DCM1); 303 reg |= GC_DCM01_DEN; 304 outreg(disp, GC_DCM1, reg); 305 break; 306 case FB_BLANK_NORMAL: 307 case FB_BLANK_VSYNC_SUSPEND: 308 case FB_BLANK_HSYNC_SUSPEND: 309 default: 310 return 1; 311 } 312 return 0; 313 } 314 315 static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd, 316 unsigned long arg) 317 { 318 struct mb862xxfb_par *par = fbi->par; 319 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg; 320 void __user *argp = (void __user *)arg; 321 int *enable; 322 u32 l1em = 0; 323 324 switch (cmd) { 325 case MB862XX_L1_GET_CFG: 326 if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg))) 327 return -EFAULT; 328 break; 329 case MB862XX_L1_SET_CFG: 330 if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg))) 331 return -EFAULT; 332 if (l1_cfg->dh == 0 || l1_cfg->dw == 0) 333 return -EINVAL; 334 if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) { 335 /* downscaling */ 336 outreg(cap, GC_CAP_CSC, 337 pack((l1_cfg->sh << 11) / l1_cfg->dh, 338 (l1_cfg->sw << 11) / l1_cfg->dw)); 339 l1em = inreg(disp, GC_L1EM); 340 l1em &= ~GC_L1EM_DM; 341 } else if ((l1_cfg->sw <= l1_cfg->dw) && 342 (l1_cfg->sh <= l1_cfg->dh)) { 343 /* upscaling */ 344 outreg(cap, GC_CAP_CSC, 345 pack((l1_cfg->sh << 11) / l1_cfg->dh, 346 (l1_cfg->sw << 11) / l1_cfg->dw)); 347 outreg(cap, GC_CAP_CMSS, 348 pack(l1_cfg->sw >> 1, l1_cfg->sh)); 349 outreg(cap, GC_CAP_CMDS, 350 pack(l1_cfg->dw >> 1, l1_cfg->dh)); 351 l1em = inreg(disp, GC_L1EM); 352 l1em |= GC_L1EM_DM; 353 } 354 355 if (l1_cfg->mirror) { 356 outreg(cap, GC_CAP_CBM, 357 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV); 358 l1em |= l1_cfg->dw * 2 - 8; 359 } else { 360 outreg(cap, GC_CAP_CBM, 361 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV); 362 l1em &= 0xffff0000; 363 } 364 outreg(disp, GC_L1EM, l1em); 365 break; 366 case MB862XX_L1_ENABLE: 367 enable = (int *)arg; 368 if (*enable) { 369 outreg(disp, GC_L1DA, par->cap_buf); 370 outreg(cap, GC_CAP_IMG_START, 371 pack(l1_cfg->sy >> 1, l1_cfg->sx)); 372 outreg(cap, GC_CAP_IMG_END, 373 pack(l1_cfg->sh, l1_cfg->sw)); 374 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS | 375 (par->l1_stride << 16)); 376 outreg(disp, GC_L1WY_L1WX, 377 pack(l1_cfg->dy, l1_cfg->dx)); 378 outreg(disp, GC_L1WH_L1WW, 379 pack(l1_cfg->dh - 1, l1_cfg->dw)); 380 outreg(disp, GC_DLS, 1); 381 outreg(cap, GC_CAP_VCM, 382 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL); 383 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) | 384 GC_DCM1_DEN | GC_DCM1_L1E); 385 } else { 386 outreg(cap, GC_CAP_VCM, 387 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE); 388 outreg(disp, GC_DCM1, 389 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E); 390 } 391 break; 392 case MB862XX_L1_CAP_CTL: 393 enable = (int *)arg; 394 if (*enable) { 395 outreg(cap, GC_CAP_VCM, 396 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE); 397 } else { 398 outreg(cap, GC_CAP_VCM, 399 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE); 400 } 401 break; 402 default: 403 return -EINVAL; 404 } 405 return 0; 406 } 407 408 /* framebuffer ops */ 409 static struct fb_ops mb862xxfb_ops = { 410 .owner = THIS_MODULE, 411 .fb_check_var = mb862xxfb_check_var, 412 .fb_set_par = mb862xxfb_set_par, 413 .fb_setcolreg = mb862xxfb_setcolreg, 414 .fb_blank = mb862xxfb_blank, 415 .fb_pan_display = mb862xxfb_pan, 416 .fb_fillrect = cfb_fillrect, 417 .fb_copyarea = cfb_copyarea, 418 .fb_imageblit = cfb_imageblit, 419 .fb_ioctl = mb862xxfb_ioctl, 420 }; 421 422 /* initialize fb_info data */ 423 static int mb862xxfb_init_fbinfo(struct fb_info *fbi) 424 { 425 struct mb862xxfb_par *par = fbi->par; 426 struct mb862xx_gc_mode *mode = par->gc_mode; 427 unsigned long reg; 428 int stride; 429 430 fbi->fbops = &mb862xxfb_ops; 431 fbi->pseudo_palette = par->pseudo_palette; 432 fbi->screen_base = par->fb_base; 433 fbi->screen_size = par->mapped_vram; 434 435 strcpy(fbi->fix.id, DRV_NAME); 436 fbi->fix.smem_start = (unsigned long)par->fb_base_phys; 437 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys; 438 fbi->fix.mmio_len = par->mmio_len; 439 fbi->fix.accel = FB_ACCEL_NONE; 440 fbi->fix.type = FB_TYPE_PACKED_PIXELS; 441 fbi->fix.type_aux = 0; 442 fbi->fix.xpanstep = 1; 443 fbi->fix.ypanstep = 1; 444 fbi->fix.ywrapstep = 0; 445 446 reg = inreg(disp, GC_DCM1); 447 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) { 448 /* get the disp mode from active display cfg */ 449 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1; 450 unsigned long hsp, vsp, ht, vt; 451 452 dev_dbg(par->dev, "using bootloader's disp. mode\n"); 453 fbi->var.pixclock = (sc * 1000000) / par->refclk; 454 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1; 455 reg = inreg(disp, GC_VDP_VSP); 456 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1; 457 vsp = (reg & 0x0fff) + 1; 458 fbi->var.xres_virtual = fbi->var.xres; 459 fbi->var.yres_virtual = fbi->var.yres; 460 reg = inreg(disp, GC_L0EM); 461 if (reg & GC_L0EM_L0EC_24) { 462 fbi->var.bits_per_pixel = 32; 463 } else { 464 reg = inreg(disp, GC_L0M); 465 if (reg & GC_L0M_L0C_16) 466 fbi->var.bits_per_pixel = 16; 467 else 468 fbi->var.bits_per_pixel = 8; 469 } 470 reg = inreg(disp, GC_VSW_HSW_HSP); 471 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1; 472 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1; 473 hsp = (reg & 0xffff) + 1; 474 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1; 475 fbi->var.right_margin = hsp - fbi->var.xres; 476 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len; 477 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1; 478 fbi->var.lower_margin = vsp - fbi->var.yres; 479 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len; 480 } else if (mode) { 481 dev_dbg(par->dev, "using supplied mode\n"); 482 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode); 483 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8; 484 } else { 485 int ret; 486 487 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60", 488 NULL, 0, NULL, 16); 489 if (ret == 0 || ret == 4) { 490 dev_err(par->dev, 491 "failed to get initial mode\n"); 492 return -EINVAL; 493 } 494 } 495 496 fbi->var.xoffset = 0; 497 fbi->var.yoffset = 0; 498 fbi->var.grayscale = 0; 499 fbi->var.nonstd = 0; 500 fbi->var.height = -1; 501 fbi->var.width = -1; 502 fbi->var.accel_flags = 0; 503 fbi->var.vmode = FB_VMODE_NONINTERLACED; 504 fbi->var.activate = FB_ACTIVATE_NOW; 505 fbi->flags = FBINFO_DEFAULT | 506 #ifdef __BIG_ENDIAN 507 FBINFO_FOREIGN_ENDIAN | 508 #endif 509 FBINFO_HWACCEL_XPAN | 510 FBINFO_HWACCEL_YPAN; 511 512 /* check and possibly fix bpp */ 513 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi)) 514 dev_err(par->dev, "check_var() failed on initial setup?\n"); 515 516 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ? 517 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 518 fbi->fix.line_length = (fbi->var.xres_virtual * 519 fbi->var.bits_per_pixel) / 8; 520 fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual; 521 522 /* 523 * reserve space for capture buffers and two cursors 524 * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16. 525 */ 526 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000; 527 par->cap_len = 0x1bd800; 528 par->l1_cfg.sx = 0; 529 par->l1_cfg.sy = 0; 530 par->l1_cfg.sw = 720; 531 par->l1_cfg.sh = 576; 532 par->l1_cfg.dx = 0; 533 par->l1_cfg.dy = 0; 534 par->l1_cfg.dw = 720; 535 par->l1_cfg.dh = 576; 536 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8); 537 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0); 538 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST | 539 (par->l1_stride << 16)); 540 outreg(cap, GC_CAP_CBOA, par->cap_buf); 541 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len); 542 return 0; 543 } 544 545 /* 546 * show some display controller and cursor registers 547 */ 548 static ssize_t dispregs_show(struct device *dev, 549 struct device_attribute *attr, char *buf) 550 { 551 struct fb_info *fbi = dev_get_drvdata(dev); 552 struct mb862xxfb_par *par = fbi->par; 553 char *ptr = buf; 554 unsigned int reg; 555 556 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4) 557 ptr += sprintf(ptr, "%08x = %08x\n", 558 reg, inreg(disp, reg)); 559 560 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4) 561 ptr += sprintf(ptr, "%08x = %08x\n", 562 reg, inreg(disp, reg)); 563 564 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4) 565 ptr += sprintf(ptr, "%08x = %08x\n", 566 reg, inreg(disp, reg)); 567 568 for (reg = 0x400; reg <= 0x410; reg += 4) 569 ptr += sprintf(ptr, "geo %08x = %08x\n", 570 reg, inreg(geo, reg)); 571 572 for (reg = 0x400; reg <= 0x410; reg += 4) 573 ptr += sprintf(ptr, "draw %08x = %08x\n", 574 reg, inreg(draw, reg)); 575 576 for (reg = 0x440; reg <= 0x450; reg += 4) 577 ptr += sprintf(ptr, "draw %08x = %08x\n", 578 reg, inreg(draw, reg)); 579 580 return ptr - buf; 581 } 582 583 static DEVICE_ATTR_RO(dispregs); 584 585 static irqreturn_t mb862xx_intr(int irq, void *dev_id) 586 { 587 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id; 588 unsigned long reg_ist, mask; 589 590 if (!par) 591 return IRQ_NONE; 592 593 if (par->type == BT_CARMINE) { 594 /* Get Interrupt Status */ 595 reg_ist = inreg(ctrl, GC_CTRL_STATUS); 596 mask = inreg(ctrl, GC_CTRL_INT_MASK); 597 if (reg_ist == 0) 598 return IRQ_HANDLED; 599 600 reg_ist &= mask; 601 if (reg_ist == 0) 602 return IRQ_HANDLED; 603 604 /* Clear interrupt status */ 605 outreg(ctrl, 0x0, reg_ist); 606 } else { 607 /* Get status */ 608 reg_ist = inreg(host, GC_IST); 609 mask = inreg(host, GC_IMASK); 610 611 reg_ist &= mask; 612 if (reg_ist == 0) 613 return IRQ_HANDLED; 614 615 /* Clear status */ 616 outreg(host, GC_IST, ~reg_ist); 617 } 618 return IRQ_HANDLED; 619 } 620 621 #if defined(CONFIG_FB_MB862XX_LIME) 622 /* 623 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus 624 */ 625 static int mb862xx_gdc_init(struct mb862xxfb_par *par) 626 { 627 unsigned long ccf, mmr; 628 unsigned long ver, rev; 629 630 if (!par) 631 return -ENODEV; 632 633 #if defined(CONFIG_FB_PRE_INIT_FB) 634 par->pre_init = 1; 635 #endif 636 par->host = par->mmio_base; 637 par->i2c = par->mmio_base + MB862XX_I2C_BASE; 638 par->disp = par->mmio_base + MB862XX_DISP_BASE; 639 par->cap = par->mmio_base + MB862XX_CAP_BASE; 640 par->draw = par->mmio_base + MB862XX_DRAW_BASE; 641 par->geo = par->mmio_base + MB862XX_GEO_BASE; 642 par->pio = par->mmio_base + MB862XX_PIO_BASE; 643 644 par->refclk = GC_DISP_REFCLK_400; 645 646 ver = inreg(host, GC_CID); 647 rev = inreg(pio, GC_REVISION); 648 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) { 649 dev_info(par->dev, "Fujitsu Lime v1.%d found\n", 650 (int)rev & 0xff); 651 par->type = BT_LIME; 652 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100; 653 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2; 654 } else { 655 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev); 656 return -ENODEV; 657 } 658 659 if (!par->pre_init) { 660 outreg(host, GC_CCF, ccf); 661 udelay(200); 662 outreg(host, GC_MMR, mmr); 663 udelay(10); 664 } 665 666 /* interrupt status */ 667 outreg(host, GC_IST, 0); 668 outreg(host, GC_IMASK, GC_INT_EN); 669 return 0; 670 } 671 672 static int of_platform_mb862xx_probe(struct platform_device *ofdev) 673 { 674 struct device_node *np = ofdev->dev.of_node; 675 struct device *dev = &ofdev->dev; 676 struct mb862xxfb_par *par; 677 struct fb_info *info; 678 struct resource res; 679 resource_size_t res_size; 680 unsigned long ret = -ENODEV; 681 682 if (of_address_to_resource(np, 0, &res)) { 683 dev_err(dev, "Invalid address\n"); 684 return -ENXIO; 685 } 686 687 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev); 688 if (!info) 689 return -ENOMEM; 690 691 par = info->par; 692 par->info = info; 693 par->dev = dev; 694 695 par->irq = irq_of_parse_and_map(np, 0); 696 if (!par->irq) { 697 dev_err(dev, "failed to map irq\n"); 698 ret = -ENODEV; 699 goto fbrel; 700 } 701 702 res_size = resource_size(&res); 703 par->res = request_mem_region(res.start, res_size, DRV_NAME); 704 if (par->res == NULL) { 705 dev_err(dev, "Cannot claim framebuffer/mmio\n"); 706 ret = -ENXIO; 707 goto irqdisp; 708 } 709 710 #if defined(CONFIG_SOCRATES) 711 par->gc_mode = &socrates_gc_mode; 712 #endif 713 714 par->fb_base_phys = res.start; 715 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE; 716 par->mmio_len = MB862XX_MMIO_SIZE; 717 if (par->gc_mode) 718 par->mapped_vram = par->gc_mode->max_vram; 719 else 720 par->mapped_vram = MB862XX_MEM_SIZE; 721 722 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram); 723 if (par->fb_base == NULL) { 724 dev_err(dev, "Cannot map framebuffer\n"); 725 goto rel_reg; 726 } 727 728 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len); 729 if (par->mmio_base == NULL) { 730 dev_err(dev, "Cannot map registers\n"); 731 goto fb_unmap; 732 } 733 734 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n", 735 (u64)par->fb_base_phys, (ulong)par->mapped_vram); 736 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n", 737 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq); 738 739 if (mb862xx_gdc_init(par)) 740 goto io_unmap; 741 742 if (request_irq(par->irq, mb862xx_intr, 0, 743 DRV_NAME, (void *)par)) { 744 dev_err(dev, "Cannot request irq\n"); 745 goto io_unmap; 746 } 747 748 mb862xxfb_init_fbinfo(info); 749 750 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) { 751 dev_err(dev, "Could not allocate cmap for fb_info.\n"); 752 goto free_irq; 753 } 754 755 if ((info->fbops->fb_set_par)(info)) 756 dev_err(dev, "set_var() failed on initial setup?\n"); 757 758 if (register_framebuffer(info)) { 759 dev_err(dev, "failed to register framebuffer\n"); 760 goto rel_cmap; 761 } 762 763 dev_set_drvdata(dev, info); 764 765 if (device_create_file(dev, &dev_attr_dispregs)) 766 dev_err(dev, "Can't create sysfs regdump file\n"); 767 return 0; 768 769 rel_cmap: 770 fb_dealloc_cmap(&info->cmap); 771 free_irq: 772 outreg(host, GC_IMASK, 0); 773 free_irq(par->irq, (void *)par); 774 io_unmap: 775 iounmap(par->mmio_base); 776 fb_unmap: 777 iounmap(par->fb_base); 778 rel_reg: 779 release_mem_region(res.start, res_size); 780 irqdisp: 781 irq_dispose_mapping(par->irq); 782 fbrel: 783 framebuffer_release(info); 784 return ret; 785 } 786 787 static void of_platform_mb862xx_remove(struct platform_device *ofdev) 788 { 789 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev); 790 struct mb862xxfb_par *par = fbi->par; 791 resource_size_t res_size = resource_size(par->res); 792 unsigned long reg; 793 794 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id); 795 796 /* display off */ 797 reg = inreg(disp, GC_DCM1); 798 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E); 799 outreg(disp, GC_DCM1, reg); 800 801 /* disable interrupts */ 802 outreg(host, GC_IMASK, 0); 803 804 free_irq(par->irq, (void *)par); 805 irq_dispose_mapping(par->irq); 806 807 device_remove_file(&ofdev->dev, &dev_attr_dispregs); 808 809 unregister_framebuffer(fbi); 810 fb_dealloc_cmap(&fbi->cmap); 811 812 iounmap(par->mmio_base); 813 iounmap(par->fb_base); 814 815 release_mem_region(par->res->start, res_size); 816 framebuffer_release(fbi); 817 } 818 819 /* 820 * common types 821 */ 822 static struct of_device_id of_platform_mb862xx_tbl[] = { 823 { .compatible = "fujitsu,MB86276", }, 824 { .compatible = "fujitsu,lime", }, 825 { .compatible = "fujitsu,MB86277", }, 826 { .compatible = "fujitsu,mint", }, 827 { .compatible = "fujitsu,MB86293", }, 828 { .compatible = "fujitsu,MB86294", }, 829 { .compatible = "fujitsu,coral", }, 830 { /* end */ } 831 }; 832 MODULE_DEVICE_TABLE(of, of_platform_mb862xx_tbl); 833 834 static struct platform_driver of_platform_mb862xxfb_driver = { 835 .driver = { 836 .name = DRV_NAME, 837 .of_match_table = of_platform_mb862xx_tbl, 838 }, 839 .probe = of_platform_mb862xx_probe, 840 .remove_new = of_platform_mb862xx_remove, 841 }; 842 #endif 843 844 #if defined(CONFIG_FB_MB862XX_PCI_GDC) 845 static int coralp_init(struct mb862xxfb_par *par) 846 { 847 int cn, ver; 848 849 par->host = par->mmio_base; 850 par->i2c = par->mmio_base + MB862XX_I2C_BASE; 851 par->disp = par->mmio_base + MB862XX_DISP_BASE; 852 par->cap = par->mmio_base + MB862XX_CAP_BASE; 853 par->draw = par->mmio_base + MB862XX_DRAW_BASE; 854 par->geo = par->mmio_base + MB862XX_GEO_BASE; 855 par->pio = par->mmio_base + MB862XX_PIO_BASE; 856 857 par->refclk = GC_DISP_REFCLK_400; 858 859 if (par->mapped_vram >= 0x2000000) { 860 /* relocate gdc registers space */ 861 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW); 862 udelay(1); /* wait at least 20 bus cycles */ 863 } 864 865 ver = inreg(host, GC_CID); 866 cn = (ver & GC_CID_CNAME_MSK) >> 8; 867 ver = ver & GC_CID_VERSION_MSK; 868 if (cn == 3) { 869 unsigned long reg; 870 871 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\ 872 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?", 873 par->pdev->revision); 874 reg = inreg(disp, GC_DCM1); 875 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) 876 par->pre_init = 1; 877 878 if (!par->pre_init) { 879 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133); 880 udelay(200); 881 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL); 882 udelay(10); 883 } 884 /* Clear interrupt status */ 885 outreg(host, GC_IST, 0); 886 } else { 887 return -ENODEV; 888 } 889 890 mb862xx_i2c_init(par); 891 return 0; 892 } 893 894 static int init_dram_ctrl(struct mb862xxfb_par *par) 895 { 896 unsigned long i = 0; 897 898 /* 899 * Set io mode first! Spec. says IC may be destroyed 900 * if not set to SSTL2/LVCMOS before init. 901 */ 902 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0); 903 904 /* DRAM init */ 905 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD); 906 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE); 907 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2, 908 GC_EVB_DCTL_REFRESH_SETTIME2); 909 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1); 910 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1); 911 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES); 912 913 /* DLL reset done? */ 914 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) { 915 udelay(GC_DCTL_INIT_WAIT_INTERVAL); 916 if (i++ > GC_DCTL_INIT_WAIT_CNT) { 917 dev_err(par->dev, "VRAM init failed.\n"); 918 return -EINVAL; 919 } 920 } 921 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST); 922 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST); 923 return 0; 924 } 925 926 static int carmine_init(struct mb862xxfb_par *par) 927 { 928 unsigned long reg; 929 930 par->ctrl = par->mmio_base + MB86297_CTRL_BASE; 931 par->i2c = par->mmio_base + MB86297_I2C_BASE; 932 par->disp = par->mmio_base + MB86297_DISP0_BASE; 933 par->disp1 = par->mmio_base + MB86297_DISP1_BASE; 934 par->cap = par->mmio_base + MB86297_CAP0_BASE; 935 par->cap1 = par->mmio_base + MB86297_CAP1_BASE; 936 par->draw = par->mmio_base + MB86297_DRAW_BASE; 937 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE; 938 par->wrback = par->mmio_base + MB86297_WRBACK_BASE; 939 940 par->refclk = GC_DISP_REFCLK_533; 941 942 /* warm up */ 943 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0; 944 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg); 945 946 /* check for engine module revision */ 947 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION) 948 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n", 949 par->pdev->revision); 950 else 951 goto err_init; 952 953 reg &= ~GC_CTRL_CLK_EN_2D3D; 954 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg); 955 956 /* set up vram */ 957 if (init_dram_ctrl(par) < 0) 958 goto err_init; 959 960 outreg(ctrl, GC_CTRL_INT_MASK, 0); 961 return 0; 962 963 err_init: 964 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0); 965 return -EINVAL; 966 } 967 968 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par) 969 { 970 switch (par->type) { 971 case BT_CORALP: 972 return coralp_init(par); 973 case BT_CARMINE: 974 return carmine_init(par); 975 default: 976 return -ENODEV; 977 } 978 } 979 980 #define CHIP_ID(id) \ 981 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) } 982 983 static const struct pci_device_id mb862xx_pci_tbl[] = { 984 /* MB86295/MB86296 */ 985 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP), 986 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA), 987 /* MB86297 */ 988 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE), 989 { 0, } 990 }; 991 992 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl); 993 994 static int mb862xx_pci_probe(struct pci_dev *pdev, 995 const struct pci_device_id *ent) 996 { 997 struct mb862xxfb_par *par; 998 struct fb_info *info; 999 struct device *dev = &pdev->dev; 1000 int ret; 1001 1002 ret = aperture_remove_conflicting_pci_devices(pdev, "mb862xxfb"); 1003 if (ret) 1004 return ret; 1005 1006 ret = pci_enable_device(pdev); 1007 if (ret < 0) { 1008 dev_err(dev, "Cannot enable PCI device\n"); 1009 goto out; 1010 } 1011 1012 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev); 1013 if (!info) { 1014 ret = -ENOMEM; 1015 goto dis_dev; 1016 } 1017 1018 par = info->par; 1019 par->info = info; 1020 par->dev = dev; 1021 par->pdev = pdev; 1022 par->irq = pdev->irq; 1023 1024 ret = pci_request_regions(pdev, DRV_NAME); 1025 if (ret < 0) { 1026 dev_err(dev, "Cannot reserve region(s) for PCI device\n"); 1027 goto rel_fb; 1028 } 1029 1030 switch (pdev->device) { 1031 case PCI_DEVICE_ID_FUJITSU_CORALP: 1032 case PCI_DEVICE_ID_FUJITSU_CORALPA: 1033 par->fb_base_phys = pci_resource_start(par->pdev, 0); 1034 par->mapped_vram = CORALP_MEM_SIZE; 1035 if (par->mapped_vram >= 0x2000000) { 1036 par->mmio_base_phys = par->fb_base_phys + 1037 MB862XX_MMIO_HIGH_BASE; 1038 } else { 1039 par->mmio_base_phys = par->fb_base_phys + 1040 MB862XX_MMIO_BASE; 1041 } 1042 par->mmio_len = MB862XX_MMIO_SIZE; 1043 par->type = BT_CORALP; 1044 break; 1045 case PCI_DEVICE_ID_FUJITSU_CARMINE: 1046 par->fb_base_phys = pci_resource_start(par->pdev, 2); 1047 par->mmio_base_phys = pci_resource_start(par->pdev, 3); 1048 par->mmio_len = pci_resource_len(par->pdev, 3); 1049 par->mapped_vram = CARMINE_MEM_SIZE; 1050 par->type = BT_CARMINE; 1051 break; 1052 default: 1053 /* should never occur */ 1054 ret = -EIO; 1055 goto rel_reg; 1056 } 1057 1058 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram); 1059 if (par->fb_base == NULL) { 1060 dev_err(dev, "Cannot map framebuffer\n"); 1061 ret = -EIO; 1062 goto rel_reg; 1063 } 1064 1065 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len); 1066 if (par->mmio_base == NULL) { 1067 dev_err(dev, "Cannot map registers\n"); 1068 ret = -EIO; 1069 goto fb_unmap; 1070 } 1071 1072 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n", 1073 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram); 1074 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n", 1075 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len); 1076 1077 ret = mb862xx_pci_gdc_init(par); 1078 if (ret) 1079 goto io_unmap; 1080 1081 ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED, 1082 DRV_NAME, (void *)par); 1083 if (ret) { 1084 dev_err(dev, "Cannot request irq\n"); 1085 goto io_unmap; 1086 } 1087 1088 mb862xxfb_init_fbinfo(info); 1089 1090 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) { 1091 dev_err(dev, "Could not allocate cmap for fb_info.\n"); 1092 ret = -ENOMEM; 1093 goto free_irq; 1094 } 1095 1096 if ((info->fbops->fb_set_par)(info)) 1097 dev_err(dev, "set_var() failed on initial setup?\n"); 1098 1099 ret = register_framebuffer(info); 1100 if (ret < 0) { 1101 dev_err(dev, "failed to register framebuffer\n"); 1102 goto rel_cmap; 1103 } 1104 1105 pci_set_drvdata(pdev, info); 1106 1107 if (device_create_file(dev, &dev_attr_dispregs)) 1108 dev_err(dev, "Can't create sysfs regdump file\n"); 1109 1110 if (par->type == BT_CARMINE) 1111 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN); 1112 else 1113 outreg(host, GC_IMASK, GC_INT_EN); 1114 1115 return 0; 1116 1117 rel_cmap: 1118 fb_dealloc_cmap(&info->cmap); 1119 free_irq: 1120 free_irq(par->irq, (void *)par); 1121 io_unmap: 1122 iounmap(par->mmio_base); 1123 fb_unmap: 1124 iounmap(par->fb_base); 1125 rel_reg: 1126 pci_release_regions(pdev); 1127 rel_fb: 1128 framebuffer_release(info); 1129 dis_dev: 1130 pci_disable_device(pdev); 1131 out: 1132 return ret; 1133 } 1134 1135 static void mb862xx_pci_remove(struct pci_dev *pdev) 1136 { 1137 struct fb_info *fbi = pci_get_drvdata(pdev); 1138 struct mb862xxfb_par *par = fbi->par; 1139 unsigned long reg; 1140 1141 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id); 1142 1143 /* display off */ 1144 reg = inreg(disp, GC_DCM1); 1145 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E); 1146 outreg(disp, GC_DCM1, reg); 1147 1148 if (par->type == BT_CARMINE) { 1149 outreg(ctrl, GC_CTRL_INT_MASK, 0); 1150 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0); 1151 } else { 1152 outreg(host, GC_IMASK, 0); 1153 } 1154 1155 mb862xx_i2c_exit(par); 1156 1157 device_remove_file(&pdev->dev, &dev_attr_dispregs); 1158 1159 unregister_framebuffer(fbi); 1160 fb_dealloc_cmap(&fbi->cmap); 1161 1162 free_irq(par->irq, (void *)par); 1163 iounmap(par->mmio_base); 1164 iounmap(par->fb_base); 1165 1166 pci_release_regions(pdev); 1167 framebuffer_release(fbi); 1168 pci_disable_device(pdev); 1169 } 1170 1171 static struct pci_driver mb862xxfb_pci_driver = { 1172 .name = DRV_NAME, 1173 .id_table = mb862xx_pci_tbl, 1174 .probe = mb862xx_pci_probe, 1175 .remove = mb862xx_pci_remove, 1176 }; 1177 #endif 1178 1179 static int mb862xxfb_init(void) 1180 { 1181 int ret = -ENODEV; 1182 1183 if (fb_modesetting_disabled(DRV_NAME)) 1184 return -ENODEV; 1185 1186 #if defined(CONFIG_FB_MB862XX_LIME) 1187 ret = platform_driver_register(&of_platform_mb862xxfb_driver); 1188 #endif 1189 #if defined(CONFIG_FB_MB862XX_PCI_GDC) 1190 ret = pci_register_driver(&mb862xxfb_pci_driver); 1191 #endif 1192 return ret; 1193 } 1194 1195 static void __exit mb862xxfb_exit(void) 1196 { 1197 #if defined(CONFIG_FB_MB862XX_LIME) 1198 platform_driver_unregister(&of_platform_mb862xxfb_driver); 1199 #endif 1200 #if defined(CONFIG_FB_MB862XX_PCI_GDC) 1201 pci_unregister_driver(&mb862xxfb_pci_driver); 1202 #endif 1203 } 1204 1205 module_init(mb862xxfb_init); 1206 module_exit(mb862xxfb_exit); 1207 1208 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver"); 1209 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>"); 1210 MODULE_LICENSE("GPL v2"); 1211