1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Freescale i.MX Frame Buffer device driver 4 * 5 * Copyright (C) 2004 Sascha Hauer, Pengutronix 6 * Based on acornfb.c Copyright (C) Russell King. 7 * 8 * Please direct your questions and comments on this driver to the following 9 * email address: 10 * 11 * linux-arm-kernel@lists.arm.linux.org.uk 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/errno.h> 17 #include <linux/string.h> 18 #include <linux/interrupt.h> 19 #include <linux/slab.h> 20 #include <linux/mm.h> 21 #include <linux/fb.h> 22 #include <linux/delay.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/cpufreq.h> 26 #include <linux/clk.h> 27 #include <linux/platform_device.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/io.h> 30 #include <linux/lcd.h> 31 #include <linux/math64.h> 32 #include <linux/of.h> 33 #include <linux/bitfield.h> 34 35 #include <linux/regulator/consumer.h> 36 37 #include <video/of_display_timing.h> 38 #include <video/of_videomode.h> 39 #include <video/videomode.h> 40 41 struct imx_fb_videomode { 42 struct fb_videomode mode; 43 u32 pcr; 44 bool aus_mode; 45 unsigned char bpp; 46 }; 47 48 /* 49 * Complain if VAR is out of range. 50 */ 51 #define DEBUG_VAR 1 52 53 #define DRIVER_NAME "imx-fb" 54 55 #define LCDC_SSA 0x00 56 57 #define LCDC_SIZE 0x04 58 #define SIZE_XMAX_MASK GENMASK(25, 20) 59 60 #define YMAX_MASK_IMX1 GENMASK(8, 0) 61 #define YMAX_MASK_IMX21 GENMASK(9, 0) 62 63 #define LCDC_VPW 0x08 64 #define VPW_VPW_MASK GENMASK(9, 0) 65 66 #define LCDC_CPOS 0x0C 67 #define CPOS_CC1 BIT(31) 68 #define CPOS_CC0 BIT(30) 69 #define CPOS_OP BIT(28) 70 #define CPOS_CXP_MASK GENMASK(25, 16) 71 72 #define LCDC_LCWHB 0x10 73 #define LCWHB_BK_EN BIT(31) 74 #define LCWHB_CW_MASK GENMASK(28, 24) 75 #define LCWHB_CH_MASK GENMASK(20, 16) 76 #define LCWHB_BD_MASK GENMASK(7, 0) 77 78 #define LCDC_LCHCC 0x14 79 80 #define LCDC_PCR 0x18 81 #define PCR_TFT BIT(31) 82 #define PCR_COLOR BIT(30) 83 #define PCR_BPIX_MASK GENMASK(27, 25) 84 #define PCR_BPIX_8 3 85 #define PCR_BPIX_12 4 86 #define PCR_BPIX_16 5 87 #define PCR_BPIX_18 6 88 #define PCR_PCD_MASK GENMASK(5, 0) 89 90 #define LCDC_HCR 0x1C 91 #define HCR_H_WIDTH_MASK GENMASK(31, 26) 92 #define HCR_H_WAIT_1_MASK GENMASK(15, 8) 93 #define HCR_H_WAIT_2_MASK GENMASK(7, 0) 94 95 #define LCDC_VCR 0x20 96 #define VCR_V_WIDTH_MASK GENMASK(31, 26) 97 #define VCR_V_WAIT_1_MASK GENMASK(15, 8) 98 #define VCR_V_WAIT_2_MASK GENMASK(7, 0) 99 100 #define LCDC_POS 0x24 101 #define POS_POS_MASK GENMASK(4, 0) 102 103 #define LCDC_LSCR1 0x28 104 /* bit fields in imxfb.h */ 105 106 #define LCDC_PWMR 0x2C 107 /* bit fields in imxfb.h */ 108 109 #define LCDC_DMACR 0x30 110 /* bit fields in imxfb.h */ 111 112 #define LCDC_RMCR 0x34 113 114 #define RMCR_LCDC_EN_MX1 BIT(1) 115 116 #define RMCR_SELF_REF BIT(0) 117 118 #define LCDC_LCDICR 0x38 119 #define LCDICR_INT_SYN BIT(2) 120 #define LCDICR_INT_CON BIT(0) 121 122 #define LCDC_LCDISR 0x40 123 #define LCDISR_UDR_ERR BIT(3) 124 #define LCDISR_ERR_RES BIT(2) 125 #define LCDISR_EOF BIT(1) 126 #define LCDISR_BOF BIT(0) 127 128 #define IMXFB_LSCR1_DEFAULT 0x00120300 129 130 #define LCDC_LAUSCR 0x80 131 #define LAUSCR_AUS_MODE BIT(31) 132 133 /* Used fb-mode. Can be set on kernel command line, therefore file-static. */ 134 static const char *fb_mode; 135 136 /* 137 * These are the bitfields for each 138 * display depth that we support. 139 */ 140 struct imxfb_rgb { 141 struct fb_bitfield red; 142 struct fb_bitfield green; 143 struct fb_bitfield blue; 144 struct fb_bitfield transp; 145 }; 146 147 enum imxfb_type { 148 IMX1_FB, 149 IMX21_FB, 150 }; 151 152 enum imxfb_panel_type { 153 PANEL_TYPE_MONOCHROME, 154 PANEL_TYPE_CSTN, 155 PANEL_TYPE_TFT, 156 }; 157 158 struct imxfb_info { 159 struct platform_device *pdev; 160 void __iomem *regs; 161 struct clk *clk_ipg; 162 struct clk *clk_ahb; 163 struct clk *clk_per; 164 enum imxfb_type devtype; 165 enum imxfb_panel_type panel_type; 166 bool enabled; 167 168 /* 169 * These are the addresses we mapped 170 * the framebuffer memory region to. 171 */ 172 dma_addr_t map_dma; 173 u_int map_size; 174 175 u_int palette_size; 176 177 dma_addr_t dbar1; 178 dma_addr_t dbar2; 179 180 u_int pcr; 181 u_int lauscr; 182 u_int pwmr; 183 u_int lscr1; 184 u_int dmacr; 185 bool cmap_inverse; 186 bool cmap_static; 187 188 struct imx_fb_videomode *mode; 189 int num_modes; 190 191 struct regulator *lcd_pwr; 192 int lcd_pwr_enabled; 193 }; 194 195 static const struct platform_device_id imxfb_devtype[] = { 196 { 197 .name = "imx1-fb", 198 .driver_data = IMX1_FB, 199 }, { 200 .name = "imx21-fb", 201 .driver_data = IMX21_FB, 202 }, { 203 /* sentinel */ 204 } 205 }; 206 MODULE_DEVICE_TABLE(platform, imxfb_devtype); 207 208 static const struct of_device_id imxfb_of_dev_id[] = { 209 { 210 .compatible = "fsl,imx1-fb", 211 .data = &imxfb_devtype[IMX1_FB], 212 }, { 213 .compatible = "fsl,imx21-fb", 214 .data = &imxfb_devtype[IMX21_FB], 215 }, { 216 /* sentinel */ 217 } 218 }; 219 MODULE_DEVICE_TABLE(of, imxfb_of_dev_id); 220 221 static inline int is_imx1_fb(struct imxfb_info *fbi) 222 { 223 return fbi->devtype == IMX1_FB; 224 } 225 226 #define IMX_NAME "IMX" 227 228 /* 229 * Minimum X and Y resolutions 230 */ 231 #define MIN_XRES 64 232 #define MIN_YRES 64 233 234 /* Actually this really is 18bit support, the lowest 2 bits of each colour 235 * are unused in hardware. We claim to have 24bit support to make software 236 * like X work, which does not support 18bit. 237 */ 238 static struct imxfb_rgb def_rgb_18 = { 239 .red = {.offset = 16, .length = 8,}, 240 .green = {.offset = 8, .length = 8,}, 241 .blue = {.offset = 0, .length = 8,}, 242 .transp = {.offset = 0, .length = 0,}, 243 }; 244 245 static struct imxfb_rgb def_rgb_16_tft = { 246 .red = {.offset = 11, .length = 5,}, 247 .green = {.offset = 5, .length = 6,}, 248 .blue = {.offset = 0, .length = 5,}, 249 .transp = {.offset = 0, .length = 0,}, 250 }; 251 252 static struct imxfb_rgb def_rgb_16_stn = { 253 .red = {.offset = 8, .length = 4,}, 254 .green = {.offset = 4, .length = 4,}, 255 .blue = {.offset = 0, .length = 4,}, 256 .transp = {.offset = 0, .length = 0,}, 257 }; 258 259 static struct imxfb_rgb def_rgb_8 = { 260 .red = {.offset = 0, .length = 8,}, 261 .green = {.offset = 0, .length = 8,}, 262 .blue = {.offset = 0, .length = 8,}, 263 .transp = {.offset = 0, .length = 0,}, 264 }; 265 266 static int imxfb_activate_var(struct fb_var_screeninfo *var, 267 struct fb_info *info); 268 269 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 270 { 271 chan &= 0xffff; 272 chan >>= 16 - bf->length; 273 return chan << bf->offset; 274 } 275 276 static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, 277 u_int trans, struct fb_info *info) 278 { 279 struct imxfb_info *fbi = info->par; 280 u_int val, ret = 1; 281 282 #define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16) 283 if (regno < fbi->palette_size) { 284 val = (CNVT_TOHW(red, 4) << 8) | 285 (CNVT_TOHW(green, 4) << 4) | 286 CNVT_TOHW(blue, 4); 287 288 writel(val, fbi->regs + 0x800 + (regno << 2)); 289 ret = 0; 290 } 291 return ret; 292 } 293 294 static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 295 u_int trans, struct fb_info *info) 296 { 297 struct imxfb_info *fbi = info->par; 298 unsigned int val; 299 int ret = 1; 300 301 /* 302 * If inverse mode was selected, invert all the colours 303 * rather than the register number. The register number 304 * is what you poke into the framebuffer to produce the 305 * colour you requested. 306 */ 307 if (fbi->cmap_inverse) { 308 red = 0xffff - red; 309 green = 0xffff - green; 310 blue = 0xffff - blue; 311 } 312 313 /* 314 * If greyscale is true, then we convert the RGB value 315 * to greyscale no mater what visual we are using. 316 */ 317 if (info->var.grayscale) 318 red = green = blue = (19595 * red + 38470 * green + 319 7471 * blue) >> 16; 320 321 switch (info->fix.visual) { 322 case FB_VISUAL_TRUECOLOR: 323 /* 324 * 12 or 16-bit True Colour. We encode the RGB value 325 * according to the RGB bitfield information. 326 */ 327 if (regno < 16) { 328 u32 *pal = info->pseudo_palette; 329 330 val = chan_to_field(red, &info->var.red); 331 val |= chan_to_field(green, &info->var.green); 332 val |= chan_to_field(blue, &info->var.blue); 333 334 pal[regno] = val; 335 ret = 0; 336 } 337 break; 338 339 case FB_VISUAL_STATIC_PSEUDOCOLOR: 340 case FB_VISUAL_PSEUDOCOLOR: 341 ret = imxfb_setpalettereg(regno, red, green, blue, trans, info); 342 break; 343 } 344 345 return ret; 346 } 347 348 static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi) 349 { 350 struct imx_fb_videomode *m; 351 int i; 352 353 if (!fb_mode) 354 return &fbi->mode[0]; 355 356 for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) { 357 if (!strcmp(m->mode.name, fb_mode)) 358 return m; 359 } 360 return NULL; 361 } 362 363 /* 364 * imxfb_check_var(): 365 * Round up in the following order: bits_per_pixel, xres, 366 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 367 * bitfields, horizontal timing, vertical timing. 368 */ 369 static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 370 { 371 struct imxfb_info *fbi = info->par; 372 struct imxfb_rgb *rgb; 373 const struct imx_fb_videomode *imxfb_mode; 374 unsigned long lcd_clk; 375 unsigned long long tmp; 376 u32 pcr = 0; 377 378 if (var->xres < MIN_XRES) 379 var->xres = MIN_XRES; 380 if (var->yres < MIN_YRES) 381 var->yres = MIN_YRES; 382 383 imxfb_mode = imxfb_find_mode(fbi); 384 if (!imxfb_mode) 385 return -EINVAL; 386 387 var->xres = imxfb_mode->mode.xres; 388 var->yres = imxfb_mode->mode.yres; 389 var->bits_per_pixel = imxfb_mode->bpp; 390 var->pixclock = imxfb_mode->mode.pixclock; 391 var->hsync_len = imxfb_mode->mode.hsync_len; 392 var->left_margin = imxfb_mode->mode.left_margin; 393 var->right_margin = imxfb_mode->mode.right_margin; 394 var->vsync_len = imxfb_mode->mode.vsync_len; 395 var->upper_margin = imxfb_mode->mode.upper_margin; 396 var->lower_margin = imxfb_mode->mode.lower_margin; 397 var->sync = imxfb_mode->mode.sync; 398 var->xres_virtual = max(var->xres_virtual, var->xres); 399 var->yres_virtual = max(var->yres_virtual, var->yres); 400 401 pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); 402 403 lcd_clk = clk_get_rate(fbi->clk_per); 404 405 tmp = var->pixclock * (unsigned long long)lcd_clk; 406 407 do_div(tmp, 1000000); 408 409 if (do_div(tmp, 1000000) > 500000) 410 tmp++; 411 412 pcr = (unsigned int)tmp; 413 414 if (--pcr > PCR_PCD_MASK) { 415 pcr = PCR_PCD_MASK; 416 dev_warn(&fbi->pdev->dev, "Must limit pixel clock to %luHz\n", 417 lcd_clk / pcr); 418 } 419 420 switch (var->bits_per_pixel) { 421 case 32: 422 pcr |= FIELD_PREP(PCR_BPIX_MASK, PCR_BPIX_18); 423 rgb = &def_rgb_18; 424 break; 425 case 16: 426 default: 427 if (is_imx1_fb(fbi)) 428 pcr |= FIELD_PREP(PCR_BPIX_MASK, PCR_BPIX_12); 429 else 430 pcr |= FIELD_PREP(PCR_BPIX_MASK, PCR_BPIX_16); 431 432 if (imxfb_mode->pcr & PCR_TFT) 433 rgb = &def_rgb_16_tft; 434 else 435 rgb = &def_rgb_16_stn; 436 break; 437 case 8: 438 pcr |= FIELD_PREP(PCR_BPIX_MASK, PCR_BPIX_8); 439 rgb = &def_rgb_8; 440 break; 441 } 442 443 /* add sync polarities */ 444 pcr |= imxfb_mode->pcr & ~(PCR_PCD_MASK | PCR_BPIX_MASK); 445 446 fbi->pcr = pcr; 447 /* 448 * The LCDC AUS Mode Control Register does not exist on imx1. 449 */ 450 if (!is_imx1_fb(fbi) && imxfb_mode->aus_mode) 451 fbi->lauscr = LAUSCR_AUS_MODE; 452 453 if (imxfb_mode->pcr & PCR_TFT) 454 fbi->panel_type = PANEL_TYPE_TFT; 455 else if (imxfb_mode->pcr & PCR_COLOR) 456 fbi->panel_type = PANEL_TYPE_CSTN; 457 else 458 fbi->panel_type = PANEL_TYPE_MONOCHROME; 459 460 /* 461 * Copy the RGB parameters for this display 462 * from the machine specific parameters. 463 */ 464 var->red = rgb->red; 465 var->green = rgb->green; 466 var->blue = rgb->blue; 467 var->transp = rgb->transp; 468 469 pr_debug("RGBT length = %d:%d:%d:%d\n", 470 var->red.length, var->green.length, var->blue.length, 471 var->transp.length); 472 473 pr_debug("RGBT offset = %d:%d:%d:%d\n", 474 var->red.offset, var->green.offset, var->blue.offset, 475 var->transp.offset); 476 477 return 0; 478 } 479 480 /* 481 * imxfb_set_par(): 482 * Set the user defined part of the display for the specified console 483 */ 484 static int imxfb_set_par(struct fb_info *info) 485 { 486 struct imxfb_info *fbi = info->par; 487 struct fb_var_screeninfo *var = &info->var; 488 489 if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32) 490 info->fix.visual = FB_VISUAL_TRUECOLOR; 491 else if (!fbi->cmap_static) 492 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 493 else { 494 /* 495 * Some people have weird ideas about wanting static 496 * pseudocolor maps. I suspect their user space 497 * applications are broken. 498 */ 499 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 500 } 501 502 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; 503 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; 504 505 imxfb_activate_var(var, info); 506 507 return 0; 508 } 509 510 static int imxfb_enable_controller(struct imxfb_info *fbi) 511 { 512 int ret; 513 514 if (fbi->enabled) 515 return 0; 516 517 pr_debug("Enabling LCD controller\n"); 518 519 writel(fbi->map_dma, fbi->regs + LCDC_SSA); 520 521 /* panning offset 0 (0 pixel offset) */ 522 writel(FIELD_PREP(POS_POS_MASK, 0), fbi->regs + LCDC_POS); 523 524 /* disable hardware cursor */ 525 writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1), 526 fbi->regs + LCDC_CPOS); 527 528 /* 529 * RMCR_LCDC_EN_MX1 is present on i.MX1 only, but doesn't hurt 530 * on other SoCs 531 */ 532 writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR); 533 534 ret = clk_prepare_enable(fbi->clk_ipg); 535 if (ret) 536 goto err_enable_ipg; 537 538 ret = clk_prepare_enable(fbi->clk_ahb); 539 if (ret) 540 goto err_enable_ahb; 541 542 ret = clk_prepare_enable(fbi->clk_per); 543 if (ret) 544 goto err_enable_per; 545 546 fbi->enabled = true; 547 return 0; 548 549 err_enable_per: 550 clk_disable_unprepare(fbi->clk_ahb); 551 err_enable_ahb: 552 clk_disable_unprepare(fbi->clk_ipg); 553 err_enable_ipg: 554 writel(0, fbi->regs + LCDC_RMCR); 555 556 return ret; 557 } 558 559 static void imxfb_disable_controller(struct imxfb_info *fbi) 560 { 561 if (!fbi->enabled) 562 return; 563 564 pr_debug("Disabling LCD controller\n"); 565 566 clk_disable_unprepare(fbi->clk_per); 567 clk_disable_unprepare(fbi->clk_ahb); 568 clk_disable_unprepare(fbi->clk_ipg); 569 fbi->enabled = false; 570 571 writel(0, fbi->regs + LCDC_RMCR); 572 } 573 574 static int imxfb_blank(int blank, struct fb_info *info) 575 { 576 struct imxfb_info *fbi = info->par; 577 578 pr_debug("%s: blank=%d\n", __func__, blank); 579 580 switch (blank) { 581 case FB_BLANK_POWERDOWN: 582 case FB_BLANK_VSYNC_SUSPEND: 583 case FB_BLANK_HSYNC_SUSPEND: 584 case FB_BLANK_NORMAL: 585 imxfb_disable_controller(fbi); 586 break; 587 588 case FB_BLANK_UNBLANK: 589 return imxfb_enable_controller(fbi); 590 } 591 return 0; 592 } 593 594 static const struct fb_ops imxfb_ops = { 595 .owner = THIS_MODULE, 596 FB_DEFAULT_IOMEM_OPS, 597 .fb_check_var = imxfb_check_var, 598 .fb_set_par = imxfb_set_par, 599 .fb_setcolreg = imxfb_setcolreg, 600 .fb_blank = imxfb_blank, 601 }; 602 603 /* 604 * imxfb_activate_var(): 605 * Configures LCD Controller based on entries in var parameter. Settings are 606 * only written to the controller if changes were made. 607 */ 608 static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info) 609 { 610 struct imxfb_info *fbi = info->par; 611 u32 ymax_mask = is_imx1_fb(fbi) ? YMAX_MASK_IMX1 : YMAX_MASK_IMX21; 612 u8 left_margin_low; 613 614 pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n", 615 var->xres, var->hsync_len, 616 var->left_margin, var->right_margin); 617 pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n", 618 var->yres, var->vsync_len, 619 var->upper_margin, var->lower_margin); 620 621 if (fbi->panel_type == PANEL_TYPE_TFT) 622 left_margin_low = 3; 623 else if (fbi->panel_type == PANEL_TYPE_CSTN) 624 left_margin_low = 2; 625 else 626 left_margin_low = 0; 627 628 #if DEBUG_VAR 629 if (var->xres < 16 || var->xres > 1024) 630 dev_err(&fbi->pdev->dev, "%s: invalid xres %d\n", 631 info->fix.id, var->xres); 632 if (var->hsync_len < 1 || var->hsync_len > 64) 633 dev_err(&fbi->pdev->dev, "%s: invalid hsync_len %d\n", 634 info->fix.id, var->hsync_len); 635 if (var->left_margin < left_margin_low || var->left_margin > 255) 636 dev_err(&fbi->pdev->dev, "%s: invalid left_margin %d\n", 637 info->fix.id, var->left_margin); 638 if (var->right_margin < 1 || var->right_margin > 255) 639 dev_err(&fbi->pdev->dev, "%s: invalid right_margin %d\n", 640 info->fix.id, var->right_margin); 641 if (var->yres < 1 || var->yres > ymax_mask) 642 dev_err(&fbi->pdev->dev, "%s: invalid yres %d\n", 643 info->fix.id, var->yres); 644 if (var->vsync_len > 100) 645 dev_err(&fbi->pdev->dev, "%s: invalid vsync_len %d\n", 646 info->fix.id, var->vsync_len); 647 if (var->upper_margin > 63) 648 dev_err(&fbi->pdev->dev, "%s: invalid upper_margin %d\n", 649 info->fix.id, var->upper_margin); 650 if (var->lower_margin > 255) 651 dev_err(&fbi->pdev->dev, "%s: invalid lower_margin %d\n", 652 info->fix.id, var->lower_margin); 653 #endif 654 655 /* physical screen start address */ 656 writel(FIELD_PREP(VPW_VPW_MASK, 657 var->xres * var->bits_per_pixel / 8 / 4), 658 fbi->regs + LCDC_VPW); 659 660 writel(FIELD_PREP(HCR_H_WIDTH_MASK, var->hsync_len - 1) | 661 FIELD_PREP(HCR_H_WAIT_1_MASK, var->right_margin - 1) | 662 FIELD_PREP(HCR_H_WAIT_2_MASK, 663 var->left_margin - left_margin_low), 664 fbi->regs + LCDC_HCR); 665 666 writel(FIELD_PREP(VCR_V_WIDTH_MASK, var->vsync_len) | 667 FIELD_PREP(VCR_V_WAIT_1_MASK, var->lower_margin) | 668 FIELD_PREP(VCR_V_WAIT_2_MASK, var->upper_margin), 669 fbi->regs + LCDC_VCR); 670 671 writel(FIELD_PREP(SIZE_XMAX_MASK, var->xres >> 4) | 672 (var->yres & ymax_mask), 673 fbi->regs + LCDC_SIZE); 674 675 writel(fbi->pcr, fbi->regs + LCDC_PCR); 676 if (fbi->pwmr) 677 writel(fbi->pwmr, fbi->regs + LCDC_PWMR); 678 writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); 679 680 /* dmacr = 0 is no valid value, as we need DMA control marks. */ 681 if (fbi->dmacr) 682 writel(fbi->dmacr, fbi->regs + LCDC_DMACR); 683 684 if (fbi->lauscr) 685 writel(fbi->lauscr, fbi->regs + LCDC_LAUSCR); 686 687 return 0; 688 } 689 690 static int imxfb_init_fbinfo(struct platform_device *pdev) 691 { 692 struct fb_info *info = platform_get_drvdata(pdev); 693 struct imxfb_info *fbi = info->par; 694 struct device_node *np; 695 696 info->pseudo_palette = devm_kmalloc_array(&pdev->dev, 16, 697 sizeof(u32), GFP_KERNEL); 698 if (!info->pseudo_palette) 699 return -ENOMEM; 700 701 memset(fbi, 0, sizeof(struct imxfb_info)); 702 703 fbi->pdev = pdev; 704 fbi->devtype = pdev->id_entry->driver_data; 705 706 strscpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); 707 708 info->fix.type = FB_TYPE_PACKED_PIXELS; 709 info->fix.type_aux = 0; 710 info->fix.xpanstep = 0; 711 info->fix.ypanstep = 0; 712 info->fix.ywrapstep = 0; 713 info->fix.accel = FB_ACCEL_NONE; 714 715 info->var.nonstd = 0; 716 info->var.activate = FB_ACTIVATE_NOW; 717 info->var.height = -1; 718 info->var.width = -1; 719 info->var.accel_flags = 0; 720 info->var.vmode = FB_VMODE_NONINTERLACED; 721 722 info->fbops = &imxfb_ops; 723 info->flags = FBINFO_READS_FAST; 724 725 np = pdev->dev.of_node; 726 info->var.grayscale = of_property_read_bool(np, 727 "cmap-greyscale"); 728 fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse"); 729 fbi->cmap_static = of_property_read_bool(np, "cmap-static"); 730 731 fbi->lscr1 = IMXFB_LSCR1_DEFAULT; 732 733 of_property_read_u32(np, "fsl,lpccr", &fbi->pwmr); 734 735 of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1); 736 737 of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr); 738 739 return 0; 740 } 741 742 static int imxfb_of_read_mode(struct device *dev, struct device_node *np, 743 struct imx_fb_videomode *imxfb_mode) 744 { 745 int ret; 746 struct fb_videomode *of_mode = &imxfb_mode->mode; 747 u32 bpp; 748 u32 pcr; 749 750 ret = of_property_read_string(np, "model", &of_mode->name); 751 if (ret) 752 of_mode->name = NULL; 753 754 ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE); 755 if (ret) { 756 dev_err(dev, "Failed to get videomode from DT\n"); 757 return ret; 758 } 759 760 ret = of_property_read_u32(np, "bits-per-pixel", &bpp); 761 ret |= of_property_read_u32(np, "fsl,pcr", &pcr); 762 763 if (ret) { 764 dev_err(dev, "Failed to read bpp and pcr from DT\n"); 765 return -EINVAL; 766 } 767 768 if (bpp < 1 || bpp > 255) { 769 dev_err(dev, "Bits per pixel have to be between 1 and 255\n"); 770 return -EINVAL; 771 } 772 773 imxfb_mode->bpp = bpp; 774 imxfb_mode->pcr = pcr; 775 776 /* 777 * fsl,aus-mode is optional 778 */ 779 imxfb_mode->aus_mode = of_property_read_bool(np, "fsl,aus-mode"); 780 781 return 0; 782 } 783 784 static int imxfb_lcd_get_contrast(struct lcd_device *lcddev) 785 { 786 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 787 788 return fbi->pwmr & 0xff; 789 } 790 791 static int imxfb_lcd_set_contrast(struct lcd_device *lcddev, int contrast) 792 { 793 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 794 795 if (fbi->pwmr && fbi->enabled) { 796 if (contrast > 255) 797 contrast = 255; 798 else if (contrast < 0) 799 contrast = 0; 800 801 fbi->pwmr &= ~0xff; 802 fbi->pwmr |= contrast; 803 804 writel(fbi->pwmr, fbi->regs + LCDC_PWMR); 805 } 806 807 return 0; 808 } 809 810 static int imxfb_lcd_get_power(struct lcd_device *lcddev) 811 { 812 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 813 814 if (!IS_ERR(fbi->lcd_pwr) && 815 !regulator_is_enabled(fbi->lcd_pwr)) 816 return LCD_POWER_OFF; 817 818 return LCD_POWER_ON; 819 } 820 821 static int imxfb_regulator_set(struct imxfb_info *fbi, int enable) 822 { 823 int ret; 824 825 if (enable == fbi->lcd_pwr_enabled) 826 return 0; 827 828 if (enable) 829 ret = regulator_enable(fbi->lcd_pwr); 830 else 831 ret = regulator_disable(fbi->lcd_pwr); 832 833 if (ret == 0) 834 fbi->lcd_pwr_enabled = enable; 835 836 return ret; 837 } 838 839 static int imxfb_lcd_set_power(struct lcd_device *lcddev, int power) 840 { 841 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 842 843 if (!IS_ERR(fbi->lcd_pwr)) 844 return imxfb_regulator_set(fbi, power == LCD_POWER_ON); 845 846 return 0; 847 } 848 849 static const struct lcd_ops imxfb_lcd_ops = { 850 .get_contrast = imxfb_lcd_get_contrast, 851 .set_contrast = imxfb_lcd_set_contrast, 852 .get_power = imxfb_lcd_get_power, 853 .set_power = imxfb_lcd_set_power, 854 }; 855 856 static int imxfb_setup(void) 857 { 858 char *opt, *options = NULL; 859 860 if (fb_get_options("imxfb", &options)) 861 return -ENODEV; 862 863 if (!options || !*options) 864 return 0; 865 866 while ((opt = strsep(&options, ",")) != NULL) { 867 if (!*opt) 868 continue; 869 else 870 fb_mode = opt; 871 } 872 873 return 0; 874 } 875 876 static int imxfb_probe(struct platform_device *pdev) 877 { 878 struct imxfb_info *fbi; 879 struct lcd_device *lcd; 880 struct fb_info *info; 881 struct imx_fb_videomode *m; 882 struct device_node *display_np; 883 int ret, i; 884 int bytes_per_pixel; 885 886 dev_info(&pdev->dev, "i.MX Framebuffer driver\n"); 887 888 ret = imxfb_setup(); 889 if (ret < 0) 890 return ret; 891 892 pdev->id_entry = of_device_get_match_data(&pdev->dev); 893 894 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); 895 if (!info) 896 return -ENOMEM; 897 898 fbi = info->par; 899 900 platform_set_drvdata(pdev, info); 901 902 ret = imxfb_init_fbinfo(pdev); 903 if (ret < 0) 904 goto failed_init; 905 906 fb_mode = NULL; 907 908 display_np = of_parse_phandle(pdev->dev.of_node, "display", 0); 909 if (!display_np) { 910 dev_err(&pdev->dev, "No display defined in devicetree\n"); 911 ret = -EINVAL; 912 goto failed_init; 913 } 914 915 /* 916 * imxfb does not support more modes, we choose only the native 917 * mode. 918 */ 919 fbi->num_modes = 1; 920 921 fbi->mode = devm_kzalloc(&pdev->dev, 922 sizeof(struct imx_fb_videomode), GFP_KERNEL); 923 if (!fbi->mode) { 924 ret = -ENOMEM; 925 of_node_put(display_np); 926 goto failed_init; 927 } 928 929 ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode); 930 of_node_put(display_np); 931 if (ret) 932 goto failed_init; 933 934 /* 935 * Calculate maximum bytes used per pixel. In most cases this should 936 * be the same as m->bpp/8 937 */ 938 m = &fbi->mode[0]; 939 bytes_per_pixel = (m->bpp + 7) / 8; 940 for (i = 0; i < fbi->num_modes; i++, m++) 941 info->fix.smem_len = max_t(size_t, info->fix.smem_len, 942 m->mode.xres * m->mode.yres * bytes_per_pixel); 943 944 fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 945 if (IS_ERR(fbi->clk_ipg)) { 946 ret = PTR_ERR(fbi->clk_ipg); 947 goto failed_init; 948 } 949 950 /* 951 * The LCDC controller does not have an enable bit. The 952 * controller starts directly when the clocks are enabled. 953 * If the clocks are enabled when the controller is not yet 954 * programmed with proper register values (enabled at the 955 * bootloader, for example) then it just goes into some undefined 956 * state. 957 * To avoid this issue, let's enable and disable LCDC IPG clock 958 * so that we force some kind of 'reset' to the LCDC block. 959 */ 960 ret = clk_prepare_enable(fbi->clk_ipg); 961 if (ret) 962 goto failed_init; 963 clk_disable_unprepare(fbi->clk_ipg); 964 965 fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 966 if (IS_ERR(fbi->clk_ahb)) { 967 ret = PTR_ERR(fbi->clk_ahb); 968 goto failed_init; 969 } 970 971 fbi->clk_per = devm_clk_get(&pdev->dev, "per"); 972 if (IS_ERR(fbi->clk_per)) { 973 ret = PTR_ERR(fbi->clk_per); 974 goto failed_init; 975 } 976 977 fbi->regs = devm_platform_ioremap_resource(pdev, 0); 978 if (IS_ERR(fbi->regs)) { 979 ret = PTR_ERR(fbi->regs); 980 goto failed_init; 981 } 982 983 fbi->map_size = PAGE_ALIGN(info->fix.smem_len); 984 info->screen_buffer = dma_alloc_wc(&pdev->dev, fbi->map_size, 985 &fbi->map_dma, GFP_KERNEL); 986 if (!info->screen_buffer) { 987 dev_err(&pdev->dev, "Failed to allocate video RAM\n"); 988 ret = -ENOMEM; 989 goto failed_init; 990 } 991 992 info->fix.smem_start = fbi->map_dma; 993 994 INIT_LIST_HEAD(&info->modelist); 995 for (i = 0; i < fbi->num_modes; i++) { 996 ret = fb_add_videomode(&fbi->mode[i].mode, &info->modelist); 997 if (ret) { 998 dev_err(&pdev->dev, "Failed to add videomode\n"); 999 goto failed_cmap; 1000 } 1001 } 1002 1003 /* 1004 * This makes sure that our colour bitfield 1005 * descriptors are correctly initialised. 1006 */ 1007 imxfb_check_var(&info->var, info); 1008 1009 /* 1010 * For modes > 8bpp, the color map is bypassed. 1011 * Therefore, 256 entries are enough. 1012 */ 1013 ret = fb_alloc_cmap(&info->cmap, 256, 0); 1014 if (ret < 0) 1015 goto failed_cmap; 1016 1017 imxfb_set_par(info); 1018 1019 fbi->lcd_pwr = devm_regulator_get(&pdev->dev, "lcd"); 1020 if (PTR_ERR(fbi->lcd_pwr) == -EPROBE_DEFER) { 1021 ret = -EPROBE_DEFER; 1022 goto failed_lcd; 1023 } 1024 1025 lcd = devm_lcd_device_register(&pdev->dev, "imxfb-lcd", &pdev->dev, fbi, 1026 &imxfb_lcd_ops); 1027 if (IS_ERR(lcd)) { 1028 ret = PTR_ERR(lcd); 1029 goto failed_lcd; 1030 } 1031 1032 lcd->props.max_contrast = 0xff; 1033 1034 info->lcd_dev = lcd; 1035 1036 ret = register_framebuffer(info); 1037 if (ret < 0) { 1038 dev_err(&pdev->dev, "failed to register framebuffer\n"); 1039 goto failed_lcd; 1040 } 1041 1042 imxfb_enable_controller(fbi); 1043 1044 return 0; 1045 1046 failed_lcd: 1047 fb_dealloc_cmap(&info->cmap); 1048 failed_cmap: 1049 dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer, 1050 fbi->map_dma); 1051 failed_init: 1052 framebuffer_release(info); 1053 return ret; 1054 } 1055 1056 static void imxfb_remove(struct platform_device *pdev) 1057 { 1058 struct fb_info *info = platform_get_drvdata(pdev); 1059 struct imxfb_info *fbi = info->par; 1060 1061 imxfb_disable_controller(fbi); 1062 1063 unregister_framebuffer(info); 1064 fb_dealloc_cmap(&info->cmap); 1065 dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer, 1066 fbi->map_dma); 1067 framebuffer_release(info); 1068 } 1069 1070 static int imxfb_suspend(struct device *dev) 1071 { 1072 struct fb_info *info = dev_get_drvdata(dev); 1073 struct imxfb_info *fbi = info->par; 1074 1075 imxfb_disable_controller(fbi); 1076 1077 return 0; 1078 } 1079 1080 static int imxfb_resume(struct device *dev) 1081 { 1082 struct fb_info *info = dev_get_drvdata(dev); 1083 struct imxfb_info *fbi = info->par; 1084 1085 imxfb_enable_controller(fbi); 1086 1087 return 0; 1088 } 1089 1090 static DEFINE_SIMPLE_DEV_PM_OPS(imxfb_pm_ops, imxfb_suspend, imxfb_resume); 1091 1092 static struct platform_driver imxfb_driver = { 1093 .driver = { 1094 .name = DRIVER_NAME, 1095 .of_match_table = imxfb_of_dev_id, 1096 .pm = pm_sleep_ptr(&imxfb_pm_ops), 1097 }, 1098 .probe = imxfb_probe, 1099 .remove = imxfb_remove, 1100 .id_table = imxfb_devtype, 1101 }; 1102 module_platform_driver(imxfb_driver); 1103 1104 MODULE_DESCRIPTION("Freescale i.MX framebuffer driver"); 1105 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1106 MODULE_LICENSE("GPL"); 1107