1 /* 2 * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo 3 * 4 * This file is derived from the powermac console "imstt" driver: 5 * Copyright (C) 1997 Sigurdur Asgeirsson 6 * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu) 7 * Modified by Danilo Beuche 1998 8 * Some register values added by Damien Doligez, INRIA Rocquencourt 9 * Various cleanups by Paul Mundt (lethal@chaoticdreams.org) 10 * 11 * This file was written by Ryan Nielsen (ran@krazynet.com) 12 * Most of the frame buffer device stuff was copied from atyfb.c 13 * 14 * This file is subject to the terms and conditions of the GNU General Public 15 * License. See the file COPYING in the main directory of this archive for 16 * more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/errno.h> 22 #include <linux/string.h> 23 #include <linux/mm.h> 24 #include <linux/vmalloc.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/fb.h> 28 #include <linux/init.h> 29 #include <linux/pci.h> 30 #include <asm/io.h> 31 #include <linux/uaccess.h> 32 33 #if defined(CONFIG_PPC) 34 #include <linux/nvram.h> 35 #include <asm/prom.h> 36 #include <asm/pci-bridge.h> 37 #include "macmodes.h" 38 #endif 39 40 #ifndef __powerpc__ 41 #define eieio() /* Enforce In-order Execution of I/O */ 42 #endif 43 44 /* TwinTurbo (Cosmo) registers */ 45 enum { 46 S1SA = 0, /* 0x00 */ 47 S2SA = 1, /* 0x04 */ 48 SP = 2, /* 0x08 */ 49 DSA = 3, /* 0x0C */ 50 CNT = 4, /* 0x10 */ 51 DP_OCTL = 5, /* 0x14 */ 52 CLR = 6, /* 0x18 */ 53 BI = 8, /* 0x20 */ 54 MBC = 9, /* 0x24 */ 55 BLTCTL = 10, /* 0x28 */ 56 57 /* Scan Timing Generator Registers */ 58 HES = 12, /* 0x30 */ 59 HEB = 13, /* 0x34 */ 60 HSB = 14, /* 0x38 */ 61 HT = 15, /* 0x3C */ 62 VES = 16, /* 0x40 */ 63 VEB = 17, /* 0x44 */ 64 VSB = 18, /* 0x48 */ 65 VT = 19, /* 0x4C */ 66 HCIV = 20, /* 0x50 */ 67 VCIV = 21, /* 0x54 */ 68 TCDR = 22, /* 0x58 */ 69 VIL = 23, /* 0x5C */ 70 STGCTL = 24, /* 0x60 */ 71 72 /* Screen Refresh Generator Registers */ 73 SSR = 25, /* 0x64 */ 74 HRIR = 26, /* 0x68 */ 75 SPR = 27, /* 0x6C */ 76 CMR = 28, /* 0x70 */ 77 SRGCTL = 29, /* 0x74 */ 78 79 /* RAM Refresh Generator Registers */ 80 RRCIV = 30, /* 0x78 */ 81 RRSC = 31, /* 0x7C */ 82 RRCR = 34, /* 0x88 */ 83 84 /* System Registers */ 85 GIOE = 32, /* 0x80 */ 86 GIO = 33, /* 0x84 */ 87 SCR = 35, /* 0x8C */ 88 SSTATUS = 36, /* 0x90 */ 89 PRC = 37, /* 0x94 */ 90 91 #if 0 92 /* PCI Registers */ 93 DVID = 0x00000000L, 94 SC = 0x00000004L, 95 CCR = 0x00000008L, 96 OG = 0x0000000CL, 97 BARM = 0x00000010L, 98 BARER = 0x00000030L, 99 #endif 100 }; 101 102 /* IBM 624 RAMDAC Direct Registers */ 103 enum { 104 PADDRW = 0x00, 105 PDATA = 0x04, 106 PPMASK = 0x08, 107 PADDRR = 0x0c, 108 PIDXLO = 0x10, 109 PIDXHI = 0x14, 110 PIDXDATA= 0x18, 111 PIDXCTL = 0x1c 112 }; 113 114 /* IBM 624 RAMDAC Indirect Registers */ 115 enum { 116 CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */ 117 SYNCCTL = 0x03, /* (0x00) Sync Control */ 118 HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */ 119 PWRMNGMT = 0x05, /* (0x00) Power Management */ 120 DACOP = 0x06, /* (0x02) DAC Operation */ 121 PALETCTL = 0x07, /* (0x00) Palette Control */ 122 SYSCLKCTL = 0x08, /* (0x01) System Clock Control */ 123 PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */ 124 BPP8 = 0x0b, /* () 8 Bits/Pixel Control */ 125 BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */ 126 BPP24 = 0x0d, /* () 24 Bits/Pixel Control */ 127 BPP32 = 0x0e, /* () 32 Bits/Pixel Control */ 128 PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */ 129 PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */ 130 SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */ 131 SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */ 132 SYSCLKP = 0x17, /* () System Clock P */ 133 SYSCLKC = 0x18, /* () System Clock C */ 134 /* 135 * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1) 136 * c is charge pump bias which depends on the VCO frequency 137 */ 138 PIXM0 = 0x20, /* () Pixel M 0 */ 139 PIXN0 = 0x21, /* () Pixel N 0 */ 140 PIXP0 = 0x22, /* () Pixel P 0 */ 141 PIXC0 = 0x23, /* () Pixel C 0 */ 142 CURSCTL = 0x30, /* (0x00) Cursor Control */ 143 CURSXLO = 0x31, /* () Cursor X position, low 8 bits */ 144 CURSXHI = 0x32, /* () Cursor X position, high 8 bits */ 145 CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */ 146 CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */ 147 CURSHOTX = 0x35, /* () Cursor Hot Spot X */ 148 CURSHOTY = 0x36, /* () Cursor Hot Spot Y */ 149 CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */ 150 CURSACATTR = 0x38, /* () Advanced Cursor Attribute */ 151 CURS1R = 0x40, /* () Cursor 1 Red */ 152 CURS1G = 0x41, /* () Cursor 1 Green */ 153 CURS1B = 0x42, /* () Cursor 1 Blue */ 154 CURS2R = 0x43, /* () Cursor 2 Red */ 155 CURS2G = 0x44, /* () Cursor 2 Green */ 156 CURS2B = 0x45, /* () Cursor 2 Blue */ 157 CURS3R = 0x46, /* () Cursor 3 Red */ 158 CURS3G = 0x47, /* () Cursor 3 Green */ 159 CURS3B = 0x48, /* () Cursor 3 Blue */ 160 BORDR = 0x60, /* () Border Color Red */ 161 BORDG = 0x61, /* () Border Color Green */ 162 BORDB = 0x62, /* () Border Color Blue */ 163 MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */ 164 MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */ 165 MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */ 166 KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */ 167 }; 168 169 /* TI TVP 3030 RAMDAC Direct Registers */ 170 enum { 171 TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Address/Index */ 172 TVPPDATA = 0x04, /* 1 Palette Data RAM Data */ 173 TVPPMASK = 0x08, /* 2 Pixel Read-Mask */ 174 TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Address */ 175 TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */ 176 TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */ 177 /* 6 reserved */ 178 TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */ 179 /* 8 reserved */ 180 TVPDCCTL = 0x24, /* 9 Direct Cursor Control */ 181 TVPIDATA = 0x28, /* 10 Index Data */ 182 TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */ 183 TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */ 184 TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */ 185 TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */ 186 TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */ 187 }; 188 189 /* TI TVP 3030 RAMDAC Indirect Registers */ 190 enum { 191 TVPIRREV = 0x01, /* Silicon Revision [RO] */ 192 TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */ 193 TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */ 194 TVPIRLAC = 0x0f, /* Latch Control (0x06) */ 195 TVPIRTCC = 0x18, /* True Color Control (0x80) */ 196 TVPIRMXC = 0x19, /* Multiplex Control (0x98) */ 197 TVPIRCLS = 0x1a, /* Clock Selection (0x07) */ 198 TVPIRPPG = 0x1c, /* Palette Page (0x00) */ 199 TVPIRGEC = 0x1d, /* General Control (0x00) */ 200 TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */ 201 TVPIRPLA = 0x2c, /* PLL Address */ 202 TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */ 203 TVPIRMPD = 0x2e, /* Memory Clock PLL Data */ 204 TVPIRLPD = 0x2f, /* Loop Clock PLL Data */ 205 TVPIRCKL = 0x30, /* Color-Key Overlay Low */ 206 TVPIRCKH = 0x31, /* Color-Key Overlay High */ 207 TVPIRCRL = 0x32, /* Color-Key Red Low */ 208 TVPIRCRH = 0x33, /* Color-Key Red High */ 209 TVPIRCGL = 0x34, /* Color-Key Green Low */ 210 TVPIRCGH = 0x35, /* Color-Key Green High */ 211 TVPIRCBL = 0x36, /* Color-Key Blue Low */ 212 TVPIRCBH = 0x37, /* Color-Key Blue High */ 213 TVPIRCKC = 0x38, /* Color-Key Control (0x00) */ 214 TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */ 215 TVPIRSEN = 0x3a, /* Sense Test (0x00) */ 216 TVPIRTMD = 0x3b, /* Test Mode Data */ 217 TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */ 218 TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */ 219 TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */ 220 TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */ 221 TVPIRRES = 0xff /* Software Reset [WO] */ 222 }; 223 224 struct initvalues { 225 __u8 addr, value; 226 }; 227 228 static struct initvalues ibm_initregs[] = { 229 { CLKCTL, 0x21 }, 230 { SYNCCTL, 0x00 }, 231 { HSYNCPOS, 0x00 }, 232 { PWRMNGMT, 0x00 }, 233 { DACOP, 0x02 }, 234 { PALETCTL, 0x00 }, 235 { SYSCLKCTL, 0x01 }, 236 237 /* 238 * Note that colors in X are correct only if all video data is 239 * passed through the palette in the DAC. That is, "indirect 240 * color" must be configured. This is the case for the IBM DAC 241 * used in the 2MB and 4MB cards, at least. 242 */ 243 { BPP8, 0x00 }, 244 { BPP16, 0x01 }, 245 { BPP24, 0x00 }, 246 { BPP32, 0x00 }, 247 248 { PIXCTL1, 0x05 }, 249 { PIXCTL2, 0x00 }, 250 { SYSCLKN, 0x08 }, 251 { SYSCLKM, 0x4f }, 252 { SYSCLKP, 0x00 }, 253 { SYSCLKC, 0x00 }, 254 { CURSCTL, 0x00 }, 255 { CURSACCTL, 0x01 }, 256 { CURSACATTR, 0xa8 }, 257 { CURS1R, 0xff }, 258 { CURS1G, 0xff }, 259 { CURS1B, 0xff }, 260 { CURS2R, 0xff }, 261 { CURS2G, 0xff }, 262 { CURS2B, 0xff }, 263 { CURS3R, 0xff }, 264 { CURS3G, 0xff }, 265 { CURS3B, 0xff }, 266 { BORDR, 0xff }, 267 { BORDG, 0xff }, 268 { BORDB, 0xff }, 269 { MISCTL1, 0x01 }, 270 { MISCTL2, 0x45 }, 271 { MISCTL3, 0x00 }, 272 { KEYCTL, 0x00 } 273 }; 274 275 static struct initvalues tvp_initregs[] = { 276 { TVPIRICC, 0x00 }, 277 { TVPIRBRC, 0xe4 }, 278 { TVPIRLAC, 0x06 }, 279 { TVPIRTCC, 0x80 }, 280 { TVPIRMXC, 0x4d }, 281 { TVPIRCLS, 0x05 }, 282 { TVPIRPPG, 0x00 }, 283 { TVPIRGEC, 0x00 }, 284 { TVPIRMIC, 0x08 }, 285 { TVPIRCKL, 0xff }, 286 { TVPIRCKH, 0xff }, 287 { TVPIRCRL, 0xff }, 288 { TVPIRCRH, 0xff }, 289 { TVPIRCGL, 0xff }, 290 { TVPIRCGH, 0xff }, 291 { TVPIRCBL, 0xff }, 292 { TVPIRCBH, 0xff }, 293 { TVPIRCKC, 0x00 }, 294 { TVPIRPLA, 0x00 }, 295 { TVPIRPPD, 0xc0 }, 296 { TVPIRPPD, 0xd5 }, 297 { TVPIRPPD, 0xea }, 298 { TVPIRPLA, 0x00 }, 299 { TVPIRMPD, 0xb9 }, 300 { TVPIRMPD, 0x3a }, 301 { TVPIRMPD, 0xb1 }, 302 { TVPIRPLA, 0x00 }, 303 { TVPIRLPD, 0xc1 }, 304 { TVPIRLPD, 0x3d }, 305 { TVPIRLPD, 0xf3 }, 306 }; 307 308 struct imstt_regvals { 309 __u32 pitch; 310 __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil; 311 __u8 pclk_m, pclk_n, pclk_p; 312 /* Values of the tvp which change depending on colormode x resolution */ 313 __u8 mlc[3]; /* Memory Loop Config 0x39 */ 314 __u8 lckl_p[3]; /* P value of LCKL PLL */ 315 }; 316 317 struct imstt_par { 318 struct imstt_regvals init; 319 __u32 __iomem *dc_regs; 320 unsigned long cmap_regs_phys; 321 __u8 *cmap_regs; 322 __u32 ramdac; 323 __u32 palette[16]; 324 }; 325 326 enum { 327 IBM = 0, 328 TVP = 1 329 }; 330 331 #define USE_NV_MODES 1 332 #define INIT_BPP 8 333 #define INIT_XRES 640 334 #define INIT_YRES 480 335 336 static int inverse = 0; 337 static char fontname[40] __initdata = { 0 }; 338 #if defined(CONFIG_PPC) 339 static signed char init_vmode = -1, init_cmode = -1; 340 #endif 341 342 static struct imstt_regvals tvp_reg_init_2 = { 343 512, 344 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196, 345 0xec, 0x2a, 0xf3, 346 { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 } 347 }; 348 349 static struct imstt_regvals tvp_reg_init_6 = { 350 640, 351 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a, 352 0xef, 0x2e, 0xb2, 353 { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 } 354 }; 355 356 static struct imstt_regvals tvp_reg_init_12 = { 357 800, 358 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270, 359 0xf6, 0x2e, 0xf2, 360 { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 } 361 }; 362 363 static struct imstt_regvals tvp_reg_init_13 = { 364 832, 365 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000, 366 0xfe, 0x3e, 0xf1, 367 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 } 368 }; 369 370 static struct imstt_regvals tvp_reg_init_17 = { 371 1024, 372 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000, 373 0xfc, 0x3a, 0xf1, 374 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 } 375 }; 376 377 static struct imstt_regvals tvp_reg_init_18 = { 378 1152, 379 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000, 380 0xfd, 0x3a, 0xf1, 381 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 } 382 }; 383 384 static struct imstt_regvals tvp_reg_init_19 = { 385 1280, 386 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7, 387 0xf7, 0x36, 0xf0, 388 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 } 389 }; 390 391 static struct imstt_regvals tvp_reg_init_20 = { 392 1280, 393 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000, 394 0xf0, 0x2d, 0xf0, 395 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 } 396 }; 397 398 /* 399 * PCI driver prototypes 400 */ 401 static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 402 static void imsttfb_remove(struct pci_dev *pdev); 403 404 /* 405 * Register access 406 */ 407 static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex) 408 { 409 #ifdef __powerpc__ 410 return in_le32(base + regindex); 411 #else 412 return readl(base + regindex); 413 #endif 414 } 415 416 static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val) 417 { 418 #ifdef __powerpc__ 419 out_le32(base + regindex, val); 420 #else 421 writel(val, base + regindex); 422 #endif 423 } 424 425 static __u32 426 getclkMHz(struct imstt_par *par) 427 { 428 __u32 clk_m, clk_n, clk_p; 429 430 clk_m = par->init.pclk_m; 431 clk_n = par->init.pclk_n; 432 clk_p = par->init.pclk_p; 433 434 return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1)); 435 } 436 437 static void 438 setclkMHz(struct imstt_par *par, __u32 MHz) 439 { 440 __u32 clk_m, clk_n, x, stage, spilled; 441 442 clk_m = clk_n = 0; 443 stage = spilled = 0; 444 for (;;) { 445 switch (stage) { 446 case 0: 447 clk_m++; 448 break; 449 case 1: 450 clk_n++; 451 break; 452 } 453 x = 20 * (clk_m + 1) / (clk_n + 1); 454 if (x == MHz) 455 break; 456 if (x > MHz) { 457 spilled = 1; 458 stage = 1; 459 } else if (spilled && x < MHz) { 460 stage = 0; 461 } 462 } 463 464 par->init.pclk_m = clk_m; 465 par->init.pclk_n = clk_n; 466 par->init.pclk_p = 0; 467 } 468 469 static struct imstt_regvals * 470 compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres) 471 { 472 struct imstt_regvals *init = &par->init; 473 __u32 MHz, hes, heb, veb, htp, vtp; 474 475 switch (xres) { 476 case 640: 477 hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2; 478 MHz = 30 /* .25 */ ; 479 break; 480 case 832: 481 hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3; 482 MHz = 57 /* .27_ */ ; 483 break; 484 case 1024: 485 hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3; 486 MHz = 80; 487 break; 488 case 1152: 489 hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3; 490 MHz = 101 /* .6_ */ ; 491 break; 492 case 1280: 493 hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1; 494 MHz = yres == 960 ? 126 : 135; 495 break; 496 case 1600: 497 hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3; 498 MHz = 200; 499 break; 500 default: 501 return NULL; 502 } 503 504 setclkMHz(par, MHz); 505 506 init->hes = hes; 507 init->heb = heb; 508 init->hsb = init->heb + (xres >> 3); 509 init->ht = init->hsb + htp; 510 init->ves = 0x0003; 511 init->veb = veb; 512 init->vsb = init->veb + yres; 513 init->vt = init->vsb + vtp; 514 init->vil = init->vsb; 515 516 init->pitch = xres; 517 return init; 518 } 519 520 static struct imstt_regvals * 521 compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres) 522 { 523 struct imstt_regvals *init; 524 525 switch (xres) { 526 case 512: 527 init = &tvp_reg_init_2; 528 break; 529 case 640: 530 init = &tvp_reg_init_6; 531 break; 532 case 800: 533 init = &tvp_reg_init_12; 534 break; 535 case 832: 536 init = &tvp_reg_init_13; 537 break; 538 case 1024: 539 init = &tvp_reg_init_17; 540 break; 541 case 1152: 542 init = &tvp_reg_init_18; 543 break; 544 case 1280: 545 init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20; 546 break; 547 default: 548 return NULL; 549 } 550 par->init = *init; 551 return init; 552 } 553 554 static struct imstt_regvals * 555 compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres) 556 { 557 if (par->ramdac == IBM) 558 return compute_imstt_regvals_ibm(par, xres, yres); 559 else 560 return compute_imstt_regvals_tvp(par, xres, yres); 561 } 562 563 static void 564 set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp) 565 { 566 struct imstt_regvals *init = &par->init; 567 __u8 pformat = (bpp >> 3) + 2; 568 569 par->cmap_regs[PIDXHI] = 0; eieio(); 570 par->cmap_regs[PIDXLO] = PIXM0; eieio(); 571 par->cmap_regs[PIDXDATA] = init->pclk_m;eieio(); 572 par->cmap_regs[PIDXLO] = PIXN0; eieio(); 573 par->cmap_regs[PIDXDATA] = init->pclk_n;eieio(); 574 par->cmap_regs[PIDXLO] = PIXP0; eieio(); 575 par->cmap_regs[PIDXDATA] = init->pclk_p;eieio(); 576 par->cmap_regs[PIDXLO] = PIXC0; eieio(); 577 par->cmap_regs[PIDXDATA] = 0x02; eieio(); 578 579 par->cmap_regs[PIDXLO] = PIXFMT; eieio(); 580 par->cmap_regs[PIDXDATA] = pformat; eieio(); 581 } 582 583 static void 584 set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp) 585 { 586 struct imstt_regvals *init = &par->init; 587 __u8 tcc, mxc, lckl_n, mic; 588 __u8 mlc, lckl_p; 589 590 switch (bpp) { 591 default: 592 case 8: 593 tcc = 0x80; 594 mxc = 0x4d; 595 lckl_n = 0xc1; 596 mlc = init->mlc[0]; 597 lckl_p = init->lckl_p[0]; 598 break; 599 case 16: 600 tcc = 0x44; 601 mxc = 0x55; 602 lckl_n = 0xe1; 603 mlc = init->mlc[1]; 604 lckl_p = init->lckl_p[1]; 605 break; 606 case 24: 607 tcc = 0x5e; 608 mxc = 0x5d; 609 lckl_n = 0xf1; 610 mlc = init->mlc[2]; 611 lckl_p = init->lckl_p[2]; 612 break; 613 case 32: 614 tcc = 0x46; 615 mxc = 0x5d; 616 lckl_n = 0xf1; 617 mlc = init->mlc[2]; 618 lckl_p = init->lckl_p[2]; 619 break; 620 } 621 mic = 0x08; 622 623 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio(); 624 par->cmap_regs[TVPIDATA] = 0x00; eieio(); 625 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio(); 626 par->cmap_regs[TVPIDATA] = init->pclk_m; eieio(); 627 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio(); 628 par->cmap_regs[TVPIDATA] = init->pclk_n; eieio(); 629 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio(); 630 par->cmap_regs[TVPIDATA] = init->pclk_p; eieio(); 631 632 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio(); 633 par->cmap_regs[TVPIDATA] = tcc; eieio(); 634 par->cmap_regs[TVPADDRW] = TVPIRMXC; eieio(); 635 par->cmap_regs[TVPIDATA] = mxc; eieio(); 636 par->cmap_regs[TVPADDRW] = TVPIRMIC; eieio(); 637 par->cmap_regs[TVPIDATA] = mic; eieio(); 638 639 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio(); 640 par->cmap_regs[TVPIDATA] = 0x00; eieio(); 641 par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio(); 642 par->cmap_regs[TVPIDATA] = lckl_n; eieio(); 643 644 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio(); 645 par->cmap_regs[TVPIDATA] = 0x15; eieio(); 646 par->cmap_regs[TVPADDRW] = TVPIRMLC; eieio(); 647 par->cmap_regs[TVPIDATA] = mlc; eieio(); 648 649 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio(); 650 par->cmap_regs[TVPIDATA] = 0x2a; eieio(); 651 par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio(); 652 par->cmap_regs[TVPIDATA] = lckl_p; eieio(); 653 } 654 655 static void 656 set_imstt_regvals (struct fb_info *info, u_int bpp) 657 { 658 struct imstt_par *par = info->par; 659 struct imstt_regvals *init = &par->init; 660 __u32 ctl, pitch, byteswap, scr; 661 662 if (par->ramdac == IBM) 663 set_imstt_regvals_ibm(par, bpp); 664 else 665 set_imstt_regvals_tvp(par, bpp); 666 667 /* 668 * From what I (jsk) can gather poking around with MacsBug, 669 * bits 8 and 9 in the SCR register control endianness 670 * correction (byte swapping). These bits must be set according 671 * to the color depth as follows: 672 * Color depth Bit 9 Bit 8 673 * ========== ===== ===== 674 * 8bpp 0 0 675 * 16bpp 0 1 676 * 32bpp 1 1 677 */ 678 switch (bpp) { 679 default: 680 case 8: 681 ctl = 0x17b1; 682 pitch = init->pitch >> 2; 683 byteswap = 0x000; 684 break; 685 case 16: 686 ctl = 0x17b3; 687 pitch = init->pitch >> 1; 688 byteswap = 0x100; 689 break; 690 case 24: 691 ctl = 0x17b9; 692 pitch = init->pitch - (init->pitch >> 2); 693 byteswap = 0x200; 694 break; 695 case 32: 696 ctl = 0x17b5; 697 pitch = init->pitch; 698 byteswap = 0x300; 699 break; 700 } 701 if (par->ramdac == TVP) 702 ctl -= 0x30; 703 704 write_reg_le32(par->dc_regs, HES, init->hes); 705 write_reg_le32(par->dc_regs, HEB, init->heb); 706 write_reg_le32(par->dc_regs, HSB, init->hsb); 707 write_reg_le32(par->dc_regs, HT, init->ht); 708 write_reg_le32(par->dc_regs, VES, init->ves); 709 write_reg_le32(par->dc_regs, VEB, init->veb); 710 write_reg_le32(par->dc_regs, VSB, init->vsb); 711 write_reg_le32(par->dc_regs, VT, init->vt); 712 write_reg_le32(par->dc_regs, VIL, init->vil); 713 write_reg_le32(par->dc_regs, HCIV, 1); 714 write_reg_le32(par->dc_regs, VCIV, 1); 715 write_reg_le32(par->dc_regs, TCDR, 4); 716 write_reg_le32(par->dc_regs, RRCIV, 1); 717 write_reg_le32(par->dc_regs, RRSC, 0x980); 718 write_reg_le32(par->dc_regs, RRCR, 0x11); 719 720 if (par->ramdac == IBM) { 721 write_reg_le32(par->dc_regs, HRIR, 0x0100); 722 write_reg_le32(par->dc_regs, CMR, 0x00ff); 723 write_reg_le32(par->dc_regs, SRGCTL, 0x0073); 724 } else { 725 write_reg_le32(par->dc_regs, HRIR, 0x0200); 726 write_reg_le32(par->dc_regs, CMR, 0x01ff); 727 write_reg_le32(par->dc_regs, SRGCTL, 0x0003); 728 } 729 730 switch (info->fix.smem_len) { 731 case 0x200000: 732 scr = 0x059d | byteswap; 733 break; 734 /* case 0x400000: 735 case 0x800000: */ 736 default: 737 pitch >>= 1; 738 scr = 0x150dd | byteswap; 739 break; 740 } 741 742 write_reg_le32(par->dc_regs, SCR, scr); 743 write_reg_le32(par->dc_regs, SPR, pitch); 744 write_reg_le32(par->dc_regs, STGCTL, ctl); 745 } 746 747 static inline void 748 set_offset (struct fb_var_screeninfo *var, struct fb_info *info) 749 { 750 struct imstt_par *par = info->par; 751 __u32 off = var->yoffset * (info->fix.line_length >> 3) 752 + ((var->xoffset * (info->var.bits_per_pixel >> 3)) >> 3); 753 write_reg_le32(par->dc_regs, SSR, off); 754 } 755 756 static inline void 757 set_555 (struct imstt_par *par) 758 { 759 if (par->ramdac == IBM) { 760 par->cmap_regs[PIDXHI] = 0; eieio(); 761 par->cmap_regs[PIDXLO] = BPP16; eieio(); 762 par->cmap_regs[PIDXDATA] = 0x01; eieio(); 763 } else { 764 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio(); 765 par->cmap_regs[TVPIDATA] = 0x44; eieio(); 766 } 767 } 768 769 static inline void 770 set_565 (struct imstt_par *par) 771 { 772 if (par->ramdac == IBM) { 773 par->cmap_regs[PIDXHI] = 0; eieio(); 774 par->cmap_regs[PIDXLO] = BPP16; eieio(); 775 par->cmap_regs[PIDXDATA] = 0x03; eieio(); 776 } else { 777 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio(); 778 par->cmap_regs[TVPIDATA] = 0x45; eieio(); 779 } 780 } 781 782 static int 783 imsttfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 784 { 785 if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16 786 && var->bits_per_pixel != 24 && var->bits_per_pixel != 32) 787 || var->xres_virtual < var->xres || var->yres_virtual < var->yres 788 || var->nonstd 789 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 790 return -EINVAL; 791 792 if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > info->fix.smem_len 793 || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > info->fix.smem_len) 794 return -EINVAL; 795 796 switch (var->bits_per_pixel) { 797 case 8: 798 var->red.offset = 0; 799 var->red.length = 8; 800 var->green.offset = 0; 801 var->green.length = 8; 802 var->blue.offset = 0; 803 var->blue.length = 8; 804 var->transp.offset = 0; 805 var->transp.length = 0; 806 break; 807 case 16: /* RGB 555 or 565 */ 808 if (var->green.length != 6) 809 var->red.offset = 10; 810 var->red.length = 5; 811 var->green.offset = 5; 812 if (var->green.length != 6) 813 var->green.length = 5; 814 var->blue.offset = 0; 815 var->blue.length = 5; 816 var->transp.offset = 0; 817 var->transp.length = 0; 818 break; 819 case 24: /* RGB 888 */ 820 var->red.offset = 16; 821 var->red.length = 8; 822 var->green.offset = 8; 823 var->green.length = 8; 824 var->blue.offset = 0; 825 var->blue.length = 8; 826 var->transp.offset = 0; 827 var->transp.length = 0; 828 break; 829 case 32: /* RGBA 8888 */ 830 var->red.offset = 16; 831 var->red.length = 8; 832 var->green.offset = 8; 833 var->green.length = 8; 834 var->blue.offset = 0; 835 var->blue.length = 8; 836 var->transp.offset = 24; 837 var->transp.length = 8; 838 break; 839 } 840 841 if (var->yres == var->yres_virtual) { 842 __u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2)); 843 var->yres_virtual = ((vram << 3) / var->bits_per_pixel) / var->xres_virtual; 844 if (var->yres_virtual < var->yres) 845 var->yres_virtual = var->yres; 846 } 847 848 var->red.msb_right = 0; 849 var->green.msb_right = 0; 850 var->blue.msb_right = 0; 851 var->transp.msb_right = 0; 852 var->height = -1; 853 var->width = -1; 854 var->vmode = FB_VMODE_NONINTERLACED; 855 var->left_margin = var->right_margin = 16; 856 var->upper_margin = var->lower_margin = 16; 857 var->hsync_len = var->vsync_len = 8; 858 return 0; 859 } 860 861 static int 862 imsttfb_set_par(struct fb_info *info) 863 { 864 struct imstt_par *par = info->par; 865 866 if (!compute_imstt_regvals(par, info->var.xres, info->var.yres)) 867 return -EINVAL; 868 869 if (info->var.green.length == 6) 870 set_565(par); 871 else 872 set_555(par); 873 set_imstt_regvals(info, info->var.bits_per_pixel); 874 info->var.pixclock = 1000000 / getclkMHz(par); 875 return 0; 876 } 877 878 static int 879 imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue, 880 u_int transp, struct fb_info *info) 881 { 882 struct imstt_par *par = info->par; 883 u_int bpp = info->var.bits_per_pixel; 884 885 if (regno > 255) 886 return 1; 887 888 red >>= 8; 889 green >>= 8; 890 blue >>= 8; 891 892 /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */ 893 if (0 && bpp == 16) /* screws up X */ 894 par->cmap_regs[PADDRW] = regno << 3; 895 else 896 par->cmap_regs[PADDRW] = regno; 897 eieio(); 898 899 par->cmap_regs[PDATA] = red; eieio(); 900 par->cmap_regs[PDATA] = green; eieio(); 901 par->cmap_regs[PDATA] = blue; eieio(); 902 903 if (regno < 16) 904 switch (bpp) { 905 case 16: 906 par->palette[regno] = 907 (regno << (info->var.green.length == 908 5 ? 10 : 11)) | (regno << 5) | regno; 909 break; 910 case 24: 911 par->palette[regno] = 912 (regno << 16) | (regno << 8) | regno; 913 break; 914 case 32: { 915 int i = (regno << 8) | regno; 916 par->palette[regno] = (i << 16) |i; 917 break; 918 } 919 } 920 return 0; 921 } 922 923 static int 924 imsttfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 925 { 926 if (var->xoffset + info->var.xres > info->var.xres_virtual 927 || var->yoffset + info->var.yres > info->var.yres_virtual) 928 return -EINVAL; 929 930 info->var.xoffset = var->xoffset; 931 info->var.yoffset = var->yoffset; 932 set_offset(var, info); 933 return 0; 934 } 935 936 static int 937 imsttfb_blank(int blank, struct fb_info *info) 938 { 939 struct imstt_par *par = info->par; 940 __u32 ctrl; 941 942 ctrl = read_reg_le32(par->dc_regs, STGCTL); 943 if (blank > 0) { 944 switch (blank) { 945 case FB_BLANK_NORMAL: 946 case FB_BLANK_POWERDOWN: 947 ctrl &= ~0x00000380; 948 if (par->ramdac == IBM) { 949 par->cmap_regs[PIDXHI] = 0; eieio(); 950 par->cmap_regs[PIDXLO] = MISCTL2; eieio(); 951 par->cmap_regs[PIDXDATA] = 0x55; eieio(); 952 par->cmap_regs[PIDXLO] = MISCTL1; eieio(); 953 par->cmap_regs[PIDXDATA] = 0x11; eieio(); 954 par->cmap_regs[PIDXLO] = SYNCCTL; eieio(); 955 par->cmap_regs[PIDXDATA] = 0x0f; eieio(); 956 par->cmap_regs[PIDXLO] = PWRMNGMT; eieio(); 957 par->cmap_regs[PIDXDATA] = 0x1f; eieio(); 958 par->cmap_regs[PIDXLO] = CLKCTL; eieio(); 959 par->cmap_regs[PIDXDATA] = 0xc0; 960 } 961 break; 962 case FB_BLANK_VSYNC_SUSPEND: 963 ctrl &= ~0x00000020; 964 break; 965 case FB_BLANK_HSYNC_SUSPEND: 966 ctrl &= ~0x00000010; 967 break; 968 } 969 } else { 970 if (par->ramdac == IBM) { 971 ctrl |= 0x000017b0; 972 par->cmap_regs[PIDXHI] = 0; eieio(); 973 par->cmap_regs[PIDXLO] = CLKCTL; eieio(); 974 par->cmap_regs[PIDXDATA] = 0x01; eieio(); 975 par->cmap_regs[PIDXLO] = PWRMNGMT; eieio(); 976 par->cmap_regs[PIDXDATA] = 0x00; eieio(); 977 par->cmap_regs[PIDXLO] = SYNCCTL; eieio(); 978 par->cmap_regs[PIDXDATA] = 0x00; eieio(); 979 par->cmap_regs[PIDXLO] = MISCTL1; eieio(); 980 par->cmap_regs[PIDXDATA] = 0x01; eieio(); 981 par->cmap_regs[PIDXLO] = MISCTL2; eieio(); 982 par->cmap_regs[PIDXDATA] = 0x45; eieio(); 983 } else 984 ctrl |= 0x00001780; 985 } 986 write_reg_le32(par->dc_regs, STGCTL, ctrl); 987 return 0; 988 } 989 990 static void 991 imsttfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 992 { 993 struct imstt_par *par = info->par; 994 __u32 Bpp, line_pitch, bgc, dx, dy, width, height; 995 996 bgc = rect->color; 997 bgc |= (bgc << 8); 998 bgc |= (bgc << 16); 999 1000 Bpp = info->var.bits_per_pixel >> 3, 1001 line_pitch = info->fix.line_length; 1002 1003 dy = rect->dy * line_pitch; 1004 dx = rect->dx * Bpp; 1005 height = rect->height; 1006 height--; 1007 width = rect->width * Bpp; 1008 width--; 1009 1010 if (rect->rop == ROP_COPY) { 1011 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1012 write_reg_le32(par->dc_regs, DSA, dy + dx); 1013 write_reg_le32(par->dc_regs, CNT, (height << 16) | width); 1014 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch); 1015 write_reg_le32(par->dc_regs, BI, 0xffffffff); 1016 write_reg_le32(par->dc_regs, MBC, 0xffffffff); 1017 write_reg_le32(par->dc_regs, CLR, bgc); 1018 write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */ 1019 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1020 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40); 1021 } else { 1022 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1023 write_reg_le32(par->dc_regs, DSA, dy + dx); 1024 write_reg_le32(par->dc_regs, S1SA, dy + dx); 1025 write_reg_le32(par->dc_regs, CNT, (height << 16) | width); 1026 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch); 1027 write_reg_le32(par->dc_regs, SP, line_pitch); 1028 write_reg_le32(par->dc_regs, BLTCTL, 0x40005); 1029 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1030 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40); 1031 } 1032 } 1033 1034 static void 1035 imsttfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 1036 { 1037 struct imstt_par *par = info->par; 1038 __u32 Bpp, line_pitch, fb_offset_old, fb_offset_new, sp, dp_octl; 1039 __u32 cnt, bltctl, sx, sy, dx, dy, height, width; 1040 1041 Bpp = info->var.bits_per_pixel >> 3, 1042 1043 sx = area->sx * Bpp; 1044 sy = area->sy; 1045 dx = area->dx * Bpp; 1046 dy = area->dy; 1047 height = area->height; 1048 height--; 1049 width = area->width * Bpp; 1050 width--; 1051 1052 line_pitch = info->fix.line_length; 1053 bltctl = 0x05; 1054 sp = line_pitch << 16; 1055 cnt = height << 16; 1056 1057 if (sy < dy) { 1058 sy += height; 1059 dy += height; 1060 sp |= -(line_pitch) & 0xffff; 1061 dp_octl = -(line_pitch) & 0xffff; 1062 } else { 1063 sp |= line_pitch; 1064 dp_octl = line_pitch; 1065 } 1066 if (sx < dx) { 1067 sx += width; 1068 dx += width; 1069 bltctl |= 0x80; 1070 cnt |= -(width) & 0xffff; 1071 } else { 1072 cnt |= width; 1073 } 1074 fb_offset_old = sy * line_pitch + sx; 1075 fb_offset_new = dy * line_pitch + dx; 1076 1077 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1078 write_reg_le32(par->dc_regs, S1SA, fb_offset_old); 1079 write_reg_le32(par->dc_regs, SP, sp); 1080 write_reg_le32(par->dc_regs, DSA, fb_offset_new); 1081 write_reg_le32(par->dc_regs, CNT, cnt); 1082 write_reg_le32(par->dc_regs, DP_OCTL, dp_octl); 1083 write_reg_le32(par->dc_regs, BLTCTL, bltctl); 1084 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1085 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40); 1086 } 1087 1088 #if 0 1089 static int 1090 imsttfb_load_cursor_image(struct imstt_par *par, int width, int height, __u8 fgc) 1091 { 1092 u_int x, y; 1093 1094 if (width > 32 || height > 32) 1095 return -EINVAL; 1096 1097 if (par->ramdac == IBM) { 1098 par->cmap_regs[PIDXHI] = 1; eieio(); 1099 for (x = 0; x < 0x100; x++) { 1100 par->cmap_regs[PIDXLO] = x; eieio(); 1101 par->cmap_regs[PIDXDATA] = 0x00; eieio(); 1102 } 1103 par->cmap_regs[PIDXHI] = 1; eieio(); 1104 for (y = 0; y < height; y++) 1105 for (x = 0; x < width >> 2; x++) { 1106 par->cmap_regs[PIDXLO] = x + y * 8; eieio(); 1107 par->cmap_regs[PIDXDATA] = 0xff; eieio(); 1108 } 1109 par->cmap_regs[PIDXHI] = 0; eieio(); 1110 par->cmap_regs[PIDXLO] = CURS1R; eieio(); 1111 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1112 par->cmap_regs[PIDXLO] = CURS1G; eieio(); 1113 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1114 par->cmap_regs[PIDXLO] = CURS1B; eieio(); 1115 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1116 par->cmap_regs[PIDXLO] = CURS2R; eieio(); 1117 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1118 par->cmap_regs[PIDXLO] = CURS2G; eieio(); 1119 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1120 par->cmap_regs[PIDXLO] = CURS2B; eieio(); 1121 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1122 par->cmap_regs[PIDXLO] = CURS3R; eieio(); 1123 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1124 par->cmap_regs[PIDXLO] = CURS3G; eieio(); 1125 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1126 par->cmap_regs[PIDXLO] = CURS3B; eieio(); 1127 par->cmap_regs[PIDXDATA] = fgc; eieio(); 1128 } else { 1129 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio(); 1130 par->cmap_regs[TVPIDATA] &= 0x03; eieio(); 1131 par->cmap_regs[TVPADDRW] = 0; eieio(); 1132 for (x = 0; x < 0x200; x++) { 1133 par->cmap_regs[TVPCRDAT] = 0x00; eieio(); 1134 } 1135 for (x = 0; x < 0x200; x++) { 1136 par->cmap_regs[TVPCRDAT] = 0xff; eieio(); 1137 } 1138 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio(); 1139 par->cmap_regs[TVPIDATA] &= 0x03; eieio(); 1140 for (y = 0; y < height; y++) 1141 for (x = 0; x < width >> 3; x++) { 1142 par->cmap_regs[TVPADDRW] = x + y * 8; eieio(); 1143 par->cmap_regs[TVPCRDAT] = 0xff; eieio(); 1144 } 1145 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio(); 1146 par->cmap_regs[TVPIDATA] |= 0x08; eieio(); 1147 for (y = 0; y < height; y++) 1148 for (x = 0; x < width >> 3; x++) { 1149 par->cmap_regs[TVPADDRW] = x + y * 8; eieio(); 1150 par->cmap_regs[TVPCRDAT] = 0xff; eieio(); 1151 } 1152 par->cmap_regs[TVPCADRW] = 0x00; eieio(); 1153 for (x = 0; x < 12; x++) { 1154 par->cmap_regs[TVPCDATA] = fgc; 1155 eieio(); 1156 } 1157 } 1158 return 1; 1159 } 1160 1161 static void 1162 imstt_set_cursor(struct imstt_par *par, struct fb_image *d, int on) 1163 { 1164 if (par->ramdac == IBM) { 1165 par->cmap_regs[PIDXHI] = 0; eieio(); 1166 if (!on) { 1167 par->cmap_regs[PIDXLO] = CURSCTL; eieio(); 1168 par->cmap_regs[PIDXDATA] = 0x00; eieio(); 1169 } else { 1170 par->cmap_regs[PIDXLO] = CURSXHI; eieio(); 1171 par->cmap_regs[PIDXDATA] = d->dx >> 8; eieio(); 1172 par->cmap_regs[PIDXLO] = CURSXLO; eieio(); 1173 par->cmap_regs[PIDXDATA] = d->dx & 0xff;eieio(); 1174 par->cmap_regs[PIDXLO] = CURSYHI; eieio(); 1175 par->cmap_regs[PIDXDATA] = d->dy >> 8; eieio(); 1176 par->cmap_regs[PIDXLO] = CURSYLO; eieio(); 1177 par->cmap_regs[PIDXDATA] = d->dy & 0xff;eieio(); 1178 par->cmap_regs[PIDXLO] = CURSCTL; eieio(); 1179 par->cmap_regs[PIDXDATA] = 0x02; eieio(); 1180 } 1181 } else { 1182 if (!on) { 1183 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio(); 1184 par->cmap_regs[TVPIDATA] = 0x00; eieio(); 1185 } else { 1186 __u16 x = d->dx + 0x40, y = d->dy + 0x40; 1187 1188 par->cmap_regs[TVPCXPOH] = x >> 8; eieio(); 1189 par->cmap_regs[TVPCXPOL] = x & 0xff; eieio(); 1190 par->cmap_regs[TVPCYPOH] = y >> 8; eieio(); 1191 par->cmap_regs[TVPCYPOL] = y & 0xff; eieio(); 1192 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio(); 1193 par->cmap_regs[TVPIDATA] = 0x02; eieio(); 1194 } 1195 } 1196 } 1197 1198 static int 1199 imsttfb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1200 { 1201 struct imstt_par *par = info->par; 1202 u32 flags = cursor->set, fg, bg, xx, yy; 1203 1204 if (cursor->dest == NULL && cursor->rop == ROP_XOR) 1205 return 1; 1206 1207 imstt_set_cursor(info, cursor, 0); 1208 1209 if (flags & FB_CUR_SETPOS) { 1210 xx = cursor->image.dx - info->var.xoffset; 1211 yy = cursor->image.dy - info->var.yoffset; 1212 } 1213 1214 if (flags & FB_CUR_SETSIZE) { 1215 } 1216 1217 if (flags & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) { 1218 int fg_idx = cursor->image.fg_color; 1219 int width = (cursor->image.width+7)/8; 1220 u8 *dat = (u8 *) cursor->image.data; 1221 u8 *dst = (u8 *) cursor->dest; 1222 u8 *msk = (u8 *) cursor->mask; 1223 1224 switch (cursor->rop) { 1225 case ROP_XOR: 1226 for (i = 0; i < cursor->image.height; i++) { 1227 for (j = 0; j < width; j++) { 1228 d_idx = i * MAX_CURS/8 + j; 1229 data[d_idx] = byte_rev[dat[s_idx] ^ 1230 dst[s_idx]]; 1231 mask[d_idx] = byte_rev[msk[s_idx]]; 1232 s_idx++; 1233 } 1234 } 1235 break; 1236 case ROP_COPY: 1237 default: 1238 for (i = 0; i < cursor->image.height; i++) { 1239 for (j = 0; j < width; j++) { 1240 d_idx = i * MAX_CURS/8 + j; 1241 data[d_idx] = byte_rev[dat[s_idx]]; 1242 mask[d_idx] = byte_rev[msk[s_idx]]; 1243 s_idx++; 1244 } 1245 } 1246 break; 1247 } 1248 1249 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 1250 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 1251 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; 1252 1253 imsttfb_load_cursor_image(par, xx, yy, fgc); 1254 } 1255 if (cursor->enable) 1256 imstt_set_cursor(info, cursor, 1); 1257 return 0; 1258 } 1259 #endif 1260 1261 #define FBIMSTT_SETREG 0x545401 1262 #define FBIMSTT_GETREG 0x545402 1263 #define FBIMSTT_SETCMAPREG 0x545403 1264 #define FBIMSTT_GETCMAPREG 0x545404 1265 #define FBIMSTT_SETIDXREG 0x545405 1266 #define FBIMSTT_GETIDXREG 0x545406 1267 1268 static int 1269 imsttfb_ioctl(struct fb_info *info, u_int cmd, u_long arg) 1270 { 1271 struct imstt_par *par = info->par; 1272 void __user *argp = (void __user *)arg; 1273 __u32 reg[2]; 1274 __u8 idx[2]; 1275 1276 switch (cmd) { 1277 case FBIMSTT_SETREG: 1278 if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) 1279 return -EFAULT; 1280 write_reg_le32(par->dc_regs, reg[0], reg[1]); 1281 return 0; 1282 case FBIMSTT_GETREG: 1283 if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) 1284 return -EFAULT; 1285 reg[1] = read_reg_le32(par->dc_regs, reg[0]); 1286 if (copy_to_user((void __user *)(arg + 4), ®[1], 4)) 1287 return -EFAULT; 1288 return 0; 1289 case FBIMSTT_SETCMAPREG: 1290 if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) 1291 return -EFAULT; 1292 write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]); 1293 return 0; 1294 case FBIMSTT_GETCMAPREG: 1295 if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) 1296 return -EFAULT; 1297 reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]); 1298 if (copy_to_user((void __user *)(arg + 4), ®[1], 4)) 1299 return -EFAULT; 1300 return 0; 1301 case FBIMSTT_SETIDXREG: 1302 if (copy_from_user(idx, argp, 2)) 1303 return -EFAULT; 1304 par->cmap_regs[PIDXHI] = 0; eieio(); 1305 par->cmap_regs[PIDXLO] = idx[0]; eieio(); 1306 par->cmap_regs[PIDXDATA] = idx[1]; eieio(); 1307 return 0; 1308 case FBIMSTT_GETIDXREG: 1309 if (copy_from_user(idx, argp, 1)) 1310 return -EFAULT; 1311 par->cmap_regs[PIDXHI] = 0; eieio(); 1312 par->cmap_regs[PIDXLO] = idx[0]; eieio(); 1313 idx[1] = par->cmap_regs[PIDXDATA]; 1314 if (copy_to_user((void __user *)(arg + 1), &idx[1], 1)) 1315 return -EFAULT; 1316 return 0; 1317 default: 1318 return -ENOIOCTLCMD; 1319 } 1320 } 1321 1322 static struct pci_device_id imsttfb_pci_tbl[] = { 1323 { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT128, 1324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, IBM }, 1325 { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT3D, 1326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TVP }, 1327 { 0, } 1328 }; 1329 1330 MODULE_DEVICE_TABLE(pci, imsttfb_pci_tbl); 1331 1332 static struct pci_driver imsttfb_pci_driver = { 1333 .name = "imsttfb", 1334 .id_table = imsttfb_pci_tbl, 1335 .probe = imsttfb_probe, 1336 .remove = imsttfb_remove, 1337 }; 1338 1339 static struct fb_ops imsttfb_ops = { 1340 .owner = THIS_MODULE, 1341 .fb_check_var = imsttfb_check_var, 1342 .fb_set_par = imsttfb_set_par, 1343 .fb_setcolreg = imsttfb_setcolreg, 1344 .fb_pan_display = imsttfb_pan_display, 1345 .fb_blank = imsttfb_blank, 1346 .fb_fillrect = imsttfb_fillrect, 1347 .fb_copyarea = imsttfb_copyarea, 1348 .fb_imageblit = cfb_imageblit, 1349 .fb_ioctl = imsttfb_ioctl, 1350 }; 1351 1352 static void init_imstt(struct fb_info *info) 1353 { 1354 struct imstt_par *par = info->par; 1355 __u32 i, tmp, *ip, *end; 1356 1357 tmp = read_reg_le32(par->dc_regs, PRC); 1358 if (par->ramdac == IBM) 1359 info->fix.smem_len = (tmp & 0x0004) ? 0x400000 : 0x200000; 1360 else 1361 info->fix.smem_len = 0x800000; 1362 1363 ip = (__u32 *)info->screen_base; 1364 end = (__u32 *)(info->screen_base + info->fix.smem_len); 1365 while (ip < end) 1366 *ip++ = 0; 1367 1368 /* initialize the card */ 1369 tmp = read_reg_le32(par->dc_regs, STGCTL); 1370 write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1); 1371 write_reg_le32(par->dc_regs, SSR, 0); 1372 1373 /* set default values for DAC registers */ 1374 if (par->ramdac == IBM) { 1375 par->cmap_regs[PPMASK] = 0xff; 1376 eieio(); 1377 par->cmap_regs[PIDXHI] = 0; 1378 eieio(); 1379 for (i = 0; i < ARRAY_SIZE(ibm_initregs); i++) { 1380 par->cmap_regs[PIDXLO] = ibm_initregs[i].addr; 1381 eieio(); 1382 par->cmap_regs[PIDXDATA] = ibm_initregs[i].value; 1383 eieio(); 1384 } 1385 } else { 1386 for (i = 0; i < ARRAY_SIZE(tvp_initregs); i++) { 1387 par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr; 1388 eieio(); 1389 par->cmap_regs[TVPIDATA] = tvp_initregs[i].value; 1390 eieio(); 1391 } 1392 } 1393 1394 #if USE_NV_MODES && defined(CONFIG_PPC32) 1395 { 1396 int vmode = init_vmode, cmode = init_cmode; 1397 1398 if (vmode == -1) { 1399 vmode = nvram_read_byte(NV_VMODE); 1400 if (vmode <= 0 || vmode > VMODE_MAX) 1401 vmode = VMODE_640_480_67; 1402 } 1403 if (cmode == -1) { 1404 cmode = nvram_read_byte(NV_CMODE); 1405 if (cmode < CMODE_8 || cmode > CMODE_32) 1406 cmode = CMODE_8; 1407 } 1408 if (mac_vmode_to_var(vmode, cmode, &info->var)) { 1409 info->var.xres = info->var.xres_virtual = INIT_XRES; 1410 info->var.yres = info->var.yres_virtual = INIT_YRES; 1411 info->var.bits_per_pixel = INIT_BPP; 1412 } 1413 } 1414 #else 1415 info->var.xres = info->var.xres_virtual = INIT_XRES; 1416 info->var.yres = info->var.yres_virtual = INIT_YRES; 1417 info->var.bits_per_pixel = INIT_BPP; 1418 #endif 1419 1420 if ((info->var.xres * info->var.yres) * (info->var.bits_per_pixel >> 3) > info->fix.smem_len 1421 || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) { 1422 printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel); 1423 framebuffer_release(info); 1424 return; 1425 } 1426 1427 sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP"); 1428 info->fix.mmio_len = 0x1000; 1429 info->fix.accel = FB_ACCEL_IMS_TWINTURBO; 1430 info->fix.type = FB_TYPE_PACKED_PIXELS; 1431 info->fix.visual = info->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR 1432 : FB_VISUAL_DIRECTCOLOR; 1433 info->fix.line_length = info->var.xres * (info->var.bits_per_pixel >> 3); 1434 info->fix.xpanstep = 8; 1435 info->fix.ypanstep = 1; 1436 info->fix.ywrapstep = 0; 1437 1438 info->var.accel_flags = FB_ACCELF_TEXT; 1439 1440 // if (par->ramdac == IBM) 1441 // imstt_cursor_init(info); 1442 if (info->var.green.length == 6) 1443 set_565(par); 1444 else 1445 set_555(par); 1446 set_imstt_regvals(info, info->var.bits_per_pixel); 1447 1448 info->var.pixclock = 1000000 / getclkMHz(par); 1449 1450 info->fbops = &imsttfb_ops; 1451 info->flags = FBINFO_DEFAULT | 1452 FBINFO_HWACCEL_COPYAREA | 1453 FBINFO_HWACCEL_FILLRECT | 1454 FBINFO_HWACCEL_YPAN; 1455 1456 fb_alloc_cmap(&info->cmap, 0, 0); 1457 1458 if (register_framebuffer(info) < 0) { 1459 framebuffer_release(info); 1460 return; 1461 } 1462 1463 tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8; 1464 fb_info(info, "%s frame buffer; %uMB vram; chip version %u\n", 1465 info->fix.id, info->fix.smem_len >> 20, tmp); 1466 } 1467 1468 static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1469 { 1470 unsigned long addr, size; 1471 struct imstt_par *par; 1472 struct fb_info *info; 1473 struct device_node *dp; 1474 1475 dp = pci_device_to_OF_node(pdev); 1476 if(dp) 1477 printk(KERN_INFO "%s: OF name %s\n",__func__, dp->name); 1478 else if (IS_ENABLED(CONFIG_OF)) 1479 printk(KERN_ERR "imsttfb: no OF node for pci device\n"); 1480 1481 info = framebuffer_alloc(sizeof(struct imstt_par), &pdev->dev); 1482 1483 if (!info) { 1484 printk(KERN_ERR "imsttfb: Can't allocate memory\n"); 1485 return -ENOMEM; 1486 } 1487 1488 par = info->par; 1489 1490 addr = pci_resource_start (pdev, 0); 1491 size = pci_resource_len (pdev, 0); 1492 1493 if (!request_mem_region(addr, size, "imsttfb")) { 1494 printk(KERN_ERR "imsttfb: Can't reserve memory region\n"); 1495 framebuffer_release(info); 1496 return -ENODEV; 1497 } 1498 1499 switch (pdev->device) { 1500 case PCI_DEVICE_ID_IMS_TT128: /* IMS,tt128mbA */ 1501 par->ramdac = IBM; 1502 if (dp && ((strcmp(dp->name, "IMS,tt128mb8") == 0) || 1503 (strcmp(dp->name, "IMS,tt128mb8A") == 0))) 1504 par->ramdac = TVP; 1505 break; 1506 case PCI_DEVICE_ID_IMS_TT3D: /* IMS,tt3d */ 1507 par->ramdac = TVP; 1508 break; 1509 default: 1510 printk(KERN_INFO "imsttfb: Device 0x%x unknown, " 1511 "contact maintainer.\n", pdev->device); 1512 release_mem_region(addr, size); 1513 framebuffer_release(info); 1514 return -ENODEV; 1515 } 1516 1517 info->fix.smem_start = addr; 1518 info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ? 1519 0x400000 : 0x800000); 1520 info->fix.mmio_start = addr + 0x800000; 1521 par->dc_regs = ioremap(addr + 0x800000, 0x1000); 1522 par->cmap_regs_phys = addr + 0x840000; 1523 par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000); 1524 info->pseudo_palette = par->palette; 1525 init_imstt(info); 1526 1527 pci_set_drvdata(pdev, info); 1528 return 0; 1529 } 1530 1531 static void imsttfb_remove(struct pci_dev *pdev) 1532 { 1533 struct fb_info *info = pci_get_drvdata(pdev); 1534 struct imstt_par *par = info->par; 1535 int size = pci_resource_len(pdev, 0); 1536 1537 unregister_framebuffer(info); 1538 iounmap(par->cmap_regs); 1539 iounmap(par->dc_regs); 1540 iounmap(info->screen_base); 1541 release_mem_region(info->fix.smem_start, size); 1542 framebuffer_release(info); 1543 } 1544 1545 #ifndef MODULE 1546 static int __init 1547 imsttfb_setup(char *options) 1548 { 1549 char *this_opt; 1550 1551 if (!options || !*options) 1552 return 0; 1553 1554 while ((this_opt = strsep(&options, ",")) != NULL) { 1555 if (!strncmp(this_opt, "font:", 5)) { 1556 char *p; 1557 int i; 1558 1559 p = this_opt + 5; 1560 for (i = 0; i < sizeof(fontname) - 1; i++) 1561 if (!*p || *p == ' ' || *p == ',') 1562 break; 1563 memcpy(fontname, this_opt + 5, i); 1564 fontname[i] = 0; 1565 } else if (!strncmp(this_opt, "inverse", 7)) { 1566 inverse = 1; 1567 fb_invert_cmaps(); 1568 } 1569 #if defined(CONFIG_PPC) 1570 else if (!strncmp(this_opt, "vmode:", 6)) { 1571 int vmode = simple_strtoul(this_opt+6, NULL, 0); 1572 if (vmode > 0 && vmode <= VMODE_MAX) 1573 init_vmode = vmode; 1574 } else if (!strncmp(this_opt, "cmode:", 6)) { 1575 int cmode = simple_strtoul(this_opt+6, NULL, 0); 1576 switch (cmode) { 1577 case CMODE_8: 1578 case 8: 1579 init_cmode = CMODE_8; 1580 break; 1581 case CMODE_16: 1582 case 15: 1583 case 16: 1584 init_cmode = CMODE_16; 1585 break; 1586 case CMODE_32: 1587 case 24: 1588 case 32: 1589 init_cmode = CMODE_32; 1590 break; 1591 } 1592 } 1593 #endif 1594 } 1595 return 0; 1596 } 1597 1598 #endif /* MODULE */ 1599 1600 static int __init imsttfb_init(void) 1601 { 1602 #ifndef MODULE 1603 char *option = NULL; 1604 1605 if (fb_get_options("imsttfb", &option)) 1606 return -ENODEV; 1607 1608 imsttfb_setup(option); 1609 #endif 1610 return pci_register_driver(&imsttfb_pci_driver); 1611 } 1612 1613 static void __exit imsttfb_exit(void) 1614 { 1615 pci_unregister_driver(&imsttfb_pci_driver); 1616 } 1617 1618 MODULE_LICENSE("GPL"); 1619 1620 module_init(imsttfb_init); 1621 module_exit(imsttfb_exit); 1622 1623