1 /* 2 * Common utility functions for VGA-based graphics cards. 3 * 4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive for 8 * more details. 9 * 10 * Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) 11 */ 12 13 #include <linux/export.h> 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/string.h> 17 #include <linux/fb.h> 18 #include <linux/math.h> 19 #include <linux/svga.h> 20 #include <asm/types.h> 21 #include <asm/io.h> 22 23 24 /* Write a CRT register value spread across multiple registers */ 25 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) 26 { 27 u8 regval, bitval, bitnum; 28 29 while (regset->regnum != VGA_REGSET_END_VAL) { 30 regval = vga_rcrt(regbase, regset->regnum); 31 bitnum = regset->lowbit; 32 while (bitnum <= regset->highbit) { 33 bitval = 1 << bitnum; 34 regval = regval & ~bitval; 35 if (value & 1) regval = regval | bitval; 36 bitnum ++; 37 value = value >> 1; 38 } 39 vga_wcrt(regbase, regset->regnum, regval); 40 regset ++; 41 } 42 } 43 44 /* Write a sequencer register value spread across multiple registers */ 45 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) 46 { 47 u8 regval, bitval, bitnum; 48 49 while (regset->regnum != VGA_REGSET_END_VAL) { 50 regval = vga_rseq(regbase, regset->regnum); 51 bitnum = regset->lowbit; 52 while (bitnum <= regset->highbit) { 53 bitval = 1 << bitnum; 54 regval = regval & ~bitval; 55 if (value & 1) regval = regval | bitval; 56 bitnum ++; 57 value = value >> 1; 58 } 59 vga_wseq(regbase, regset->regnum, regval); 60 regset ++; 61 } 62 } 63 64 static unsigned int svga_regset_size(const struct vga_regset *regset) 65 { 66 u8 count = 0; 67 68 while (regset->regnum != VGA_REGSET_END_VAL) { 69 count += regset->highbit - regset->lowbit + 1; 70 regset ++; 71 } 72 return 1 << count; 73 } 74 75 76 /* ------------------------------------------------------------------------- */ 77 78 79 /* Set graphics controller registers to sane values */ 80 void svga_set_default_gfx_regs(void __iomem *regbase) 81 { 82 /* All standard GFX registers (GR00 - GR08) */ 83 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00); 84 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00); 85 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00); 86 vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0x00); 87 vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0x00); 88 vga_wgfx(regbase, VGA_GFX_MODE, 0x00); 89 /* vga_wgfx(regbase, VGA_GFX_MODE, 0x20); */ 90 /* vga_wgfx(regbase, VGA_GFX_MODE, 0x40); */ 91 vga_wgfx(regbase, VGA_GFX_MISC, 0x05); 92 /* vga_wgfx(regbase, VGA_GFX_MISC, 0x01); */ 93 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x0F); 94 vga_wgfx(regbase, VGA_GFX_BIT_MASK, 0xFF); 95 } 96 97 /* Set attribute controller registers to sane values */ 98 void svga_set_default_atc_regs(void __iomem *regbase) 99 { 100 u8 count; 101 102 vga_r(regbase, 0x3DA); 103 vga_w(regbase, VGA_ATT_W, 0x00); 104 105 /* All standard ATC registers (AR00 - AR14) */ 106 for (count = 0; count <= 0xF; count ++) 107 svga_wattr(regbase, count, count); 108 109 svga_wattr(regbase, VGA_ATC_MODE, 0x01); 110 /* svga_wattr(regbase, VGA_ATC_MODE, 0x41); */ 111 svga_wattr(regbase, VGA_ATC_OVERSCAN, 0x00); 112 svga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 0x0F); 113 svga_wattr(regbase, VGA_ATC_PEL, 0x00); 114 svga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0x00); 115 116 vga_r(regbase, 0x3DA); 117 vga_w(regbase, VGA_ATT_W, 0x20); 118 } 119 120 /* Set sequencer registers to sane values */ 121 void svga_set_default_seq_regs(void __iomem *regbase) 122 { 123 /* Standard sequencer registers (SR01 - SR04), SR00 is not set */ 124 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS); 125 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES); 126 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0x00); 127 /* vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */ 128 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE); 129 } 130 131 /* Set CRTC registers to sane values */ 132 void svga_set_default_crt_regs(void __iomem *regbase) 133 { 134 /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */ 135 svga_wcrt_mask(regbase, 0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */ 136 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0); 137 svga_wcrt_mask(regbase, VGA_CRTC_MAX_SCAN, 0, 0x1F); 138 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0); 139 vga_wcrt(regbase, VGA_CRTC_MODE, 0xE3); 140 } 141 142 void svga_set_textmode_vga_regs(void __iomem *regbase) 143 { 144 /* svga_wseq_mask(regbase, 0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */ 145 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM); 146 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x03); 147 148 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */ 149 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0x1f); 150 svga_wcrt_mask(regbase, VGA_CRTC_MODE, 0x23, 0x7f); 151 152 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0x0d); 153 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 0x0e); 154 vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0x00); 155 vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0x00); 156 157 vga_wgfx(regbase, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */ 158 vga_wgfx(regbase, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */ 159 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x00); 160 161 vga_r(regbase, 0x3DA); 162 vga_w(regbase, VGA_ATT_W, 0x00); 163 164 svga_wattr(regbase, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ 165 svga_wattr(regbase, 0x13, 0x08); /* Horizontal Pixel Panning Register */ 166 167 vga_r(regbase, 0x3DA); 168 vga_w(regbase, VGA_ATT_W, 0x20); 169 } 170 171 #if 0 172 void svga_dump_var(struct fb_var_screeninfo *var, int node) 173 { 174 pr_debug("fb%d: var.vmode : 0x%X\n", node, var->vmode); 175 pr_debug("fb%d: var.xres : %d\n", node, var->xres); 176 pr_debug("fb%d: var.yres : %d\n", node, var->yres); 177 pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel); 178 pr_debug("fb%d: var.xres_virtual : %d\n", node, var->xres_virtual); 179 pr_debug("fb%d: var.yres_virtual : %d\n", node, var->yres_virtual); 180 pr_debug("fb%d: var.left_margin : %d\n", node, var->left_margin); 181 pr_debug("fb%d: var.right_margin : %d\n", node, var->right_margin); 182 pr_debug("fb%d: var.upper_margin : %d\n", node, var->upper_margin); 183 pr_debug("fb%d: var.lower_margin : %d\n", node, var->lower_margin); 184 pr_debug("fb%d: var.hsync_len : %d\n", node, var->hsync_len); 185 pr_debug("fb%d: var.vsync_len : %d\n", node, var->vsync_len); 186 pr_debug("fb%d: var.sync : 0x%X\n", node, var->sync); 187 pr_debug("fb%d: var.pixclock : %d\n\n", node, var->pixclock); 188 } 189 #endif /* 0 */ 190 191 192 /* ------------------------------------------------------------------------- */ 193 194 195 void svga_settile(struct fb_info *info, struct fb_tilemap *map) 196 { 197 const u8 *font = map->data; 198 u8 __iomem *fb = (u8 __iomem *)info->screen_base; 199 int i, c; 200 201 if ((map->width != 8) || (map->height != 16) || 202 (map->depth != 1) || (map->length != 256)) { 203 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", 204 map->width, map->height, map->depth, map->length); 205 return; 206 } 207 208 fb += 2; 209 for (c = 0; c < map->length; c++) { 210 for (i = 0; i < map->height; i++) { 211 fb_writeb(font[i], fb + i * 4); 212 // fb[i * 4] = font[i]; 213 } 214 fb += 128; 215 font += map->height; 216 } 217 } 218 219 /* Copy area in text (tileblit) mode */ 220 void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area) 221 { 222 int dx, dy; 223 /* colstride is halved in this function because u16 are used */ 224 int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); 225 int rowstride = colstride * (info->var.xres_virtual / 8); 226 u16 __iomem *fb = (u16 __iomem *) info->screen_base; 227 u16 __iomem *src, *dst; 228 229 if ((area->sy > area->dy) || 230 ((area->sy == area->dy) && (area->sx > area->dx))) { 231 src = fb + area->sx * colstride + area->sy * rowstride; 232 dst = fb + area->dx * colstride + area->dy * rowstride; 233 } else { 234 src = fb + (area->sx + area->width - 1) * colstride 235 + (area->sy + area->height - 1) * rowstride; 236 dst = fb + (area->dx + area->width - 1) * colstride 237 + (area->dy + area->height - 1) * rowstride; 238 239 colstride = -colstride; 240 rowstride = -rowstride; 241 } 242 243 for (dy = 0; dy < area->height; dy++) { 244 u16 __iomem *src2 = src; 245 u16 __iomem *dst2 = dst; 246 for (dx = 0; dx < area->width; dx++) { 247 fb_writew(fb_readw(src2), dst2); 248 // *dst2 = *src2; 249 src2 += colstride; 250 dst2 += colstride; 251 } 252 src += rowstride; 253 dst += rowstride; 254 } 255 } 256 257 /* Fill area in text (tileblit) mode */ 258 void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect) 259 { 260 int dx, dy; 261 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); 262 int rowstride = colstride * (info->var.xres_virtual / 8); 263 int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg); 264 u8 __iomem *fb = (u8 __iomem *)info->screen_base; 265 fb += rect->sx * colstride + rect->sy * rowstride; 266 267 for (dy = 0; dy < rect->height; dy++) { 268 u8 __iomem *fb2 = fb; 269 for (dx = 0; dx < rect->width; dx++) { 270 fb_writeb(rect->index, fb2); 271 fb_writeb(attr, fb2 + 1); 272 fb2 += colstride; 273 } 274 fb += rowstride; 275 } 276 } 277 278 /* Write text in text (tileblit) mode */ 279 void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit) 280 { 281 int dx, dy, i; 282 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); 283 int rowstride = colstride * (info->var.xres_virtual / 8); 284 int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg); 285 u8 __iomem *fb = (u8 __iomem *)info->screen_base; 286 fb += blit->sx * colstride + blit->sy * rowstride; 287 288 i=0; 289 for (dy=0; dy < blit->height; dy ++) { 290 u8 __iomem *fb2 = fb; 291 for (dx = 0; dx < blit->width; dx ++) { 292 fb_writeb(blit->indices[i], fb2); 293 fb_writeb(attr, fb2 + 1); 294 fb2 += colstride; 295 i ++; 296 if (i == blit->length) return; 297 } 298 fb += rowstride; 299 } 300 301 } 302 303 /* Set cursor in text (tileblit) mode */ 304 void svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor) 305 { 306 u8 cs = 0x0d; 307 u8 ce = 0x0e; 308 u16 pos = cursor->sx + (info->var.xoffset / 8) 309 + (cursor->sy + (info->var.yoffset / 16)) 310 * (info->var.xres_virtual / 8); 311 312 if (! cursor -> mode) 313 return; 314 315 svga_wcrt_mask(regbase, 0x0A, 0x20, 0x20); /* disable cursor */ 316 317 if (cursor -> shape == FB_TILE_CURSOR_NONE) 318 return; 319 320 switch (cursor -> shape) { 321 case FB_TILE_CURSOR_UNDERLINE: 322 cs = 0x0d; 323 break; 324 case FB_TILE_CURSOR_LOWER_THIRD: 325 cs = 0x09; 326 break; 327 case FB_TILE_CURSOR_LOWER_HALF: 328 cs = 0x07; 329 break; 330 case FB_TILE_CURSOR_TWO_THIRDS: 331 cs = 0x05; 332 break; 333 case FB_TILE_CURSOR_BLOCK: 334 cs = 0x01; 335 break; 336 } 337 338 /* set cursor position */ 339 vga_wcrt(regbase, 0x0E, pos >> 8); 340 vga_wcrt(regbase, 0x0F, pos & 0xFF); 341 342 vga_wcrt(regbase, 0x0B, ce); /* set cursor end */ 343 vga_wcrt(regbase, 0x0A, cs); /* set cursor start and enable it */ 344 } 345 346 int svga_get_tilemax(struct fb_info *info) 347 { 348 return 256; 349 } 350 351 /* Get capabilities of accelerator based on the mode */ 352 353 void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps, 354 struct fb_var_screeninfo *var) 355 { 356 if (var->bits_per_pixel == 0) { 357 /* can only support 256 8x16 bitmap */ 358 bitmap_zero(caps->x, FB_MAX_BLIT_WIDTH); 359 set_bit(8 - 1, caps->x); 360 bitmap_zero(caps->y, FB_MAX_BLIT_HEIGHT); 361 set_bit(16 - 1, caps->y); 362 caps->len = 256; 363 } else { 364 if (var->bits_per_pixel == 4) { 365 bitmap_zero(caps->x, FB_MAX_BLIT_WIDTH); 366 set_bit(8 - 1, caps->x); 367 } else { 368 bitmap_fill(caps->x, FB_MAX_BLIT_WIDTH); 369 } 370 bitmap_fill(caps->y, FB_MAX_BLIT_HEIGHT); 371 caps->len = ~(u32)0; 372 } 373 } 374 EXPORT_SYMBOL(svga_get_caps); 375 376 /* ------------------------------------------------------------------------- */ 377 378 379 /* 380 * Compute PLL settings (M, N, R) 381 * F_VCO = (F_BASE * M) / N 382 * F_OUT = F_VCO / (2^R) 383 */ 384 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) 385 { 386 u16 am, an, ar; 387 u32 f_vco, f_current, delta_current, delta_best; 388 389 pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted); 390 391 ar = pll->r_max; 392 f_vco = f_wanted << ar; 393 394 /* overflow check */ 395 if ((f_vco >> ar) != f_wanted) 396 return -EINVAL; 397 398 /* It is usually better to have greater VCO clock 399 because of better frequency stability. 400 So first try r_max, then r smaller. */ 401 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { 402 ar--; 403 f_vco = f_vco >> 1; 404 } 405 406 /* VCO bounds check */ 407 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) 408 return -EINVAL; 409 410 delta_best = 0xFFFFFFFF; 411 *m = 0; 412 *n = 0; 413 *r = ar; 414 415 am = pll->m_min; 416 an = pll->n_min; 417 418 while ((am <= pll->m_max) && (an <= pll->n_max)) { 419 f_current = (pll->f_base * am) / an; 420 delta_current = abs_diff (f_current, f_vco); 421 422 if (delta_current < delta_best) { 423 delta_best = delta_current; 424 *m = am; 425 *n = an; 426 } 427 428 if (f_current <= f_vco) { 429 am ++; 430 } else { 431 an ++; 432 } 433 } 434 435 f_current = (pll->f_base * *m) / *n; 436 pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current); 437 pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r); 438 return 0; 439 } 440 441 442 /* ------------------------------------------------------------------------- */ 443 444 445 /* Check CRT timing values */ 446 int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node) 447 { 448 u32 value; 449 450 var->xres = (var->xres+7)&~7; 451 var->left_margin = (var->left_margin+7)&~7; 452 var->right_margin = (var->right_margin+7)&~7; 453 var->hsync_len = (var->hsync_len+7)&~7; 454 455 /* Check horizontal total */ 456 value = var->xres + var->left_margin + var->right_margin + var->hsync_len; 457 if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs)) 458 return -EINVAL; 459 460 /* Check horizontal display and blank start */ 461 value = var->xres; 462 if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs)) 463 return -EINVAL; 464 if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs)) 465 return -EINVAL; 466 467 /* Check horizontal sync start */ 468 value = var->xres + var->right_margin; 469 if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs)) 470 return -EINVAL; 471 472 /* Check horizontal blank end (or length) */ 473 value = var->left_margin + var->right_margin + var->hsync_len; 474 if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs))) 475 return -EINVAL; 476 477 /* Check horizontal sync end (or length) */ 478 value = var->hsync_len; 479 if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs))) 480 return -EINVAL; 481 482 /* Check vertical total */ 483 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; 484 if ((value - 1) >= svga_regset_size(tm->v_total_regs)) 485 return -EINVAL; 486 487 /* Check vertical display and blank start */ 488 value = var->yres; 489 if ((value - 1) >= svga_regset_size(tm->v_display_regs)) 490 return -EINVAL; 491 if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs)) 492 return -EINVAL; 493 494 /* Check vertical sync start */ 495 value = var->yres + var->lower_margin; 496 if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs)) 497 return -EINVAL; 498 499 /* Check vertical blank end (or length) */ 500 value = var->upper_margin + var->lower_margin + var->vsync_len; 501 if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs))) 502 return -EINVAL; 503 504 /* Check vertical sync end (or length) */ 505 value = var->vsync_len; 506 if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs))) 507 return -EINVAL; 508 509 return 0; 510 } 511 512 /* Set CRT timing registers */ 513 void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm, 514 struct fb_var_screeninfo *var, 515 u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node) 516 { 517 u8 regval; 518 u32 value; 519 520 value = var->xres + var->left_margin + var->right_margin + var->hsync_len; 521 value = (value * hmul) / hdiv; 522 pr_debug("fb%d: horizontal total : %d\n", node, value); 523 svga_wcrt_multi(regbase, tm->h_total_regs, (value / 8) - 5); 524 525 value = var->xres; 526 value = (value * hmul) / hdiv; 527 pr_debug("fb%d: horizontal display : %d\n", node, value); 528 svga_wcrt_multi(regbase, tm->h_display_regs, (value / 8) - 1); 529 530 value = var->xres; 531 value = (value * hmul) / hdiv; 532 pr_debug("fb%d: horizontal blank start: %d\n", node, value); 533 svga_wcrt_multi(regbase, tm->h_blank_start_regs, (value / 8) - 1 + hborder); 534 535 value = var->xres + var->left_margin + var->right_margin + var->hsync_len; 536 value = (value * hmul) / hdiv; 537 pr_debug("fb%d: horizontal blank end : %d\n", node, value); 538 svga_wcrt_multi(regbase, tm->h_blank_end_regs, (value / 8) - 1 - hborder); 539 540 value = var->xres + var->right_margin; 541 value = (value * hmul) / hdiv; 542 pr_debug("fb%d: horizontal sync start : %d\n", node, value); 543 svga_wcrt_multi(regbase, tm->h_sync_start_regs, (value / 8)); 544 545 value = var->xres + var->right_margin + var->hsync_len; 546 value = (value * hmul) / hdiv; 547 pr_debug("fb%d: horizontal sync end : %d\n", node, value); 548 svga_wcrt_multi(regbase, tm->h_sync_end_regs, (value / 8)); 549 550 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; 551 value = (value * vmul) / vdiv; 552 pr_debug("fb%d: vertical total : %d\n", node, value); 553 svga_wcrt_multi(regbase, tm->v_total_regs, value - 2); 554 555 value = var->yres; 556 value = (value * vmul) / vdiv; 557 pr_debug("fb%d: vertical display : %d\n", node, value); 558 svga_wcrt_multi(regbase, tm->v_display_regs, value - 1); 559 560 value = var->yres; 561 value = (value * vmul) / vdiv; 562 pr_debug("fb%d: vertical blank start : %d\n", node, value); 563 svga_wcrt_multi(regbase, tm->v_blank_start_regs, value); 564 565 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; 566 value = (value * vmul) / vdiv; 567 pr_debug("fb%d: vertical blank end : %d\n", node, value); 568 svga_wcrt_multi(regbase, tm->v_blank_end_regs, value - 2); 569 570 value = var->yres + var->lower_margin; 571 value = (value * vmul) / vdiv; 572 pr_debug("fb%d: vertical sync start : %d\n", node, value); 573 svga_wcrt_multi(regbase, tm->v_sync_start_regs, value); 574 575 value = var->yres + var->lower_margin + var->vsync_len; 576 value = (value * vmul) / vdiv; 577 pr_debug("fb%d: vertical sync end : %d\n", node, value); 578 svga_wcrt_multi(regbase, tm->v_sync_end_regs, value); 579 580 /* Set horizontal and vertical sync pulse polarity in misc register */ 581 582 regval = vga_r(regbase, VGA_MIS_R); 583 if (var->sync & FB_SYNC_HOR_HIGH_ACT) { 584 pr_debug("fb%d: positive horizontal sync\n", node); 585 regval = regval & ~0x80; 586 } else { 587 pr_debug("fb%d: negative horizontal sync\n", node); 588 regval = regval | 0x80; 589 } 590 if (var->sync & FB_SYNC_VERT_HIGH_ACT) { 591 pr_debug("fb%d: positive vertical sync\n", node); 592 regval = regval & ~0x40; 593 } else { 594 pr_debug("fb%d: negative vertical sync\n\n", node); 595 regval = regval | 0x40; 596 } 597 vga_w(regbase, VGA_MIS_W, regval); 598 } 599 600 601 /* ------------------------------------------------------------------------- */ 602 603 604 static inline int match_format(const struct svga_fb_format *frm, 605 struct fb_var_screeninfo *var) 606 { 607 int i = 0; 608 int stored = -EINVAL; 609 610 while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL) 611 { 612 if ((var->bits_per_pixel == frm->bits_per_pixel) && 613 (var->red.length <= frm->red.length) && 614 (var->green.length <= frm->green.length) && 615 (var->blue.length <= frm->blue.length) && 616 (var->transp.length <= frm->transp.length) && 617 (var->nonstd == frm->nonstd)) 618 return i; 619 if (var->bits_per_pixel == frm->bits_per_pixel) 620 stored = i; 621 i++; 622 frm++; 623 } 624 return stored; 625 } 626 627 int svga_match_format(const struct svga_fb_format *frm, 628 struct fb_var_screeninfo *var, 629 struct fb_fix_screeninfo *fix) 630 { 631 int i = match_format(frm, var); 632 633 if (i >= 0) { 634 var->bits_per_pixel = frm[i].bits_per_pixel; 635 var->red = frm[i].red; 636 var->green = frm[i].green; 637 var->blue = frm[i].blue; 638 var->transp = frm[i].transp; 639 var->nonstd = frm[i].nonstd; 640 if (fix != NULL) { 641 fix->type = frm[i].type; 642 fix->type_aux = frm[i].type_aux; 643 fix->visual = frm[i].visual; 644 fix->xpanstep = frm[i].xpanstep; 645 } 646 } 647 648 return i; 649 } 650 651 652 EXPORT_SYMBOL(svga_wcrt_multi); 653 EXPORT_SYMBOL(svga_wseq_multi); 654 655 EXPORT_SYMBOL(svga_set_default_gfx_regs); 656 EXPORT_SYMBOL(svga_set_default_atc_regs); 657 EXPORT_SYMBOL(svga_set_default_seq_regs); 658 EXPORT_SYMBOL(svga_set_default_crt_regs); 659 EXPORT_SYMBOL(svga_set_textmode_vga_regs); 660 661 EXPORT_SYMBOL(svga_settile); 662 EXPORT_SYMBOL(svga_tilecopy); 663 EXPORT_SYMBOL(svga_tilefill); 664 EXPORT_SYMBOL(svga_tileblit); 665 EXPORT_SYMBOL(svga_tilecursor); 666 EXPORT_SYMBOL(svga_get_tilemax); 667 668 EXPORT_SYMBOL(svga_compute_pll); 669 EXPORT_SYMBOL(svga_check_timings); 670 EXPORT_SYMBOL(svga_set_timings); 671 EXPORT_SYMBOL(svga_match_format); 672 673 MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>"); 674 MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards"); 675 MODULE_LICENSE("GPL"); 676