1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cg3.c: CGTHREE frame buffer driver 3 * 4 * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz) 6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) 7 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 8 * 9 * Driver layout based loosely on tgafb.c, see that file for credits. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/errno.h> 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/fb.h> 19 #include <linux/mm.h> 20 #include <linux/of_device.h> 21 22 #include <asm/io.h> 23 #include <asm/fbio.h> 24 25 #include "sbuslib.h" 26 27 /* 28 * Local functions. 29 */ 30 31 static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned, 32 unsigned, struct fb_info *); 33 static int cg3_blank(int, struct fb_info *); 34 35 static int cg3_sbusfb_mmap(struct fb_info *info, struct vm_area_struct *vma); 36 static int cg3_sbusfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg); 37 38 /* 39 * Frame buffer operations 40 */ 41 42 static const struct fb_ops cg3_ops = { 43 .owner = THIS_MODULE, 44 FB_DEFAULT_SBUS_OPS(cg3), 45 .fb_setcolreg = cg3_setcolreg, 46 .fb_blank = cg3_blank, 47 }; 48 49 50 /* Control Register Constants */ 51 #define CG3_CR_ENABLE_INTS 0x80 52 #define CG3_CR_ENABLE_VIDEO 0x40 53 #define CG3_CR_ENABLE_TIMING 0x20 54 #define CG3_CR_ENABLE_CURCMP 0x10 55 #define CG3_CR_XTAL_MASK 0x0c 56 #define CG3_CR_DIVISOR_MASK 0x03 57 58 /* Status Register Constants */ 59 #define CG3_SR_PENDING_INT 0x80 60 #define CG3_SR_RES_MASK 0x70 61 #define CG3_SR_1152_900_76_A 0x40 62 #define CG3_SR_1152_900_76_B 0x60 63 #define CG3_SR_ID_MASK 0x0f 64 #define CG3_SR_ID_COLOR 0x01 65 #define CG3_SR_ID_MONO 0x02 66 #define CG3_SR_ID_MONO_ECL 0x03 67 68 enum cg3_type { 69 CG3_AT_66HZ = 0, 70 CG3_AT_76HZ, 71 CG3_RDI 72 }; 73 74 struct bt_regs { 75 u32 addr; 76 u32 color_map; 77 u32 control; 78 u32 cursor; 79 }; 80 81 struct cg3_regs { 82 struct bt_regs cmap; 83 u8 control; 84 u8 status; 85 u8 cursor_start; 86 u8 cursor_end; 87 u8 h_blank_start; 88 u8 h_blank_end; 89 u8 h_sync_start; 90 u8 h_sync_end; 91 u8 comp_sync_end; 92 u8 v_blank_start_high; 93 u8 v_blank_start_low; 94 u8 v_blank_end; 95 u8 v_sync_start; 96 u8 v_sync_end; 97 u8 xfer_holdoff_start; 98 u8 xfer_holdoff_end; 99 }; 100 101 /* Offset of interesting structures in the OBIO space */ 102 #define CG3_REGS_OFFSET 0x400000UL 103 #define CG3_RAM_OFFSET 0x800000UL 104 105 struct cg3_par { 106 spinlock_t lock; 107 struct cg3_regs __iomem *regs; 108 u32 sw_cmap[((256 * 3) + 3) / 4]; 109 110 u32 flags; 111 #define CG3_FLAG_BLANKED 0x00000001 112 #define CG3_FLAG_RDI 0x00000002 113 114 unsigned long which_io; 115 }; 116 117 /** 118 * cg3_setcolreg - Optional function. Sets a color register. 119 * @regno: boolean, 0 copy local, 1 get_user() function 120 * @red: frame buffer colormap structure 121 * @green: The green value which can be up to 16 bits wide 122 * @blue: The blue value which can be up to 16 bits wide. 123 * @transp: If supported the alpha value which can be up to 16 bits wide. 124 * @info: frame buffer info structure 125 * 126 * The cg3 palette is loaded with 4 color values at each time 127 * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on. 128 * We keep a sw copy of the hw cmap to assist us in this esoteric 129 * loading procedure. 130 */ 131 static int cg3_setcolreg(unsigned regno, 132 unsigned red, unsigned green, unsigned blue, 133 unsigned transp, struct fb_info *info) 134 { 135 struct cg3_par *par = (struct cg3_par *) info->par; 136 struct bt_regs __iomem *bt = &par->regs->cmap; 137 unsigned long flags; 138 u32 *p32; 139 u8 *p8; 140 int count; 141 142 if (regno >= 256) 143 return 1; 144 145 red >>= 8; 146 green >>= 8; 147 blue >>= 8; 148 149 spin_lock_irqsave(&par->lock, flags); 150 151 p8 = (u8 *)par->sw_cmap + (regno * 3); 152 p8[0] = red; 153 p8[1] = green; 154 p8[2] = blue; 155 156 #define D4M3(x) ((((x)>>2)<<1) + ((x)>>2)) /* (x/4)*3 */ 157 #define D4M4(x) ((x)&~0x3) /* (x/4)*4 */ 158 159 count = 3; 160 p32 = &par->sw_cmap[D4M3(regno)]; 161 sbus_writel(D4M4(regno), &bt->addr); 162 while (count--) 163 sbus_writel(*p32++, &bt->color_map); 164 165 #undef D4M3 166 #undef D4M4 167 168 spin_unlock_irqrestore(&par->lock, flags); 169 170 return 0; 171 } 172 173 /** 174 * cg3_blank - Optional function. Blanks the display. 175 * @blank: the blank mode we want. 176 * @info: frame buffer structure that represents a single frame buffer 177 */ 178 static int cg3_blank(int blank, struct fb_info *info) 179 { 180 struct cg3_par *par = (struct cg3_par *) info->par; 181 struct cg3_regs __iomem *regs = par->regs; 182 unsigned long flags; 183 u8 val; 184 185 spin_lock_irqsave(&par->lock, flags); 186 187 switch (blank) { 188 case FB_BLANK_UNBLANK: /* Unblanking */ 189 val = sbus_readb(®s->control); 190 val |= CG3_CR_ENABLE_VIDEO; 191 sbus_writeb(val, ®s->control); 192 par->flags &= ~CG3_FLAG_BLANKED; 193 break; 194 195 case FB_BLANK_NORMAL: /* Normal blanking */ 196 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ 197 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ 198 case FB_BLANK_POWERDOWN: /* Poweroff */ 199 val = sbus_readb(®s->control); 200 val &= ~CG3_CR_ENABLE_VIDEO; 201 sbus_writeb(val, ®s->control); 202 par->flags |= CG3_FLAG_BLANKED; 203 break; 204 } 205 206 spin_unlock_irqrestore(&par->lock, flags); 207 208 return 0; 209 } 210 211 static struct sbus_mmap_map cg3_mmap_map[] = { 212 { 213 .voff = CG3_MMAP_OFFSET, 214 .poff = CG3_RAM_OFFSET, 215 .size = SBUS_MMAP_FBSIZE(1) 216 }, 217 { .size = 0 } 218 }; 219 220 static int cg3_sbusfb_mmap(struct fb_info *info, struct vm_area_struct *vma) 221 { 222 struct cg3_par *par = (struct cg3_par *)info->par; 223 224 return sbusfb_mmap_helper(cg3_mmap_map, 225 info->fix.smem_start, info->fix.smem_len, 226 par->which_io, 227 vma); 228 } 229 230 static int cg3_sbusfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) 231 { 232 return sbusfb_ioctl_helper(cmd, arg, info, 233 FBTYPE_SUN3COLOR, 8, info->fix.smem_len); 234 } 235 236 /* 237 * Initialisation 238 */ 239 240 static void cg3_init_fix(struct fb_info *info, int linebytes, 241 struct device_node *dp) 242 { 243 snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp); 244 245 info->fix.type = FB_TYPE_PACKED_PIXELS; 246 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 247 248 info->fix.line_length = linebytes; 249 250 info->fix.accel = FB_ACCEL_SUN_CGTHREE; 251 } 252 253 static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var, 254 struct device_node *dp) 255 { 256 const char *params; 257 char *p; 258 int ww, hh; 259 260 params = of_get_property(dp, "params", NULL); 261 if (params) { 262 ww = simple_strtoul(params, &p, 10); 263 if (ww && *p == 'x') { 264 hh = simple_strtoul(p + 1, &p, 10); 265 if (hh && *p == '-') { 266 if (var->xres != ww || 267 var->yres != hh) { 268 var->xres = var->xres_virtual = ww; 269 var->yres = var->yres_virtual = hh; 270 } 271 } 272 } 273 } 274 } 275 276 static u8 cg3regvals_66hz[] = { /* 1152 x 900, 66 Hz */ 277 0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14, 278 0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24, 279 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01, 280 0x10, 0x20, 0 281 }; 282 283 static u8 cg3regvals_76hz[] = { /* 1152 x 900, 76 Hz */ 284 0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f, 285 0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a, 286 0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01, 287 0x10, 0x24, 0 288 }; 289 290 static u8 cg3regvals_rdi[] = { /* 640 x 480, cgRDI */ 291 0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10, 292 0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51, 293 0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01, 294 0x10, 0x22, 0 295 }; 296 297 static u8 *cg3_regvals[] = { 298 cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi 299 }; 300 301 static u_char cg3_dacvals[] = { 302 4, 0xff, 5, 0x00, 6, 0x70, 7, 0x00, 0 303 }; 304 305 static int cg3_do_default_mode(struct cg3_par *par) 306 { 307 enum cg3_type type; 308 u8 *p; 309 310 if (par->flags & CG3_FLAG_RDI) 311 type = CG3_RDI; 312 else { 313 u8 status = sbus_readb(&par->regs->status), mon; 314 if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) { 315 mon = status & CG3_SR_RES_MASK; 316 if (mon == CG3_SR_1152_900_76_A || 317 mon == CG3_SR_1152_900_76_B) 318 type = CG3_AT_76HZ; 319 else 320 type = CG3_AT_66HZ; 321 } else { 322 printk(KERN_ERR "cgthree: can't handle SR %02x\n", 323 status); 324 return -EINVAL; 325 } 326 } 327 328 for (p = cg3_regvals[type]; *p; p += 2) { 329 u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]]; 330 sbus_writeb(p[1], regp); 331 } 332 for (p = cg3_dacvals; *p; p += 2) { 333 u8 __iomem *regp; 334 335 regp = (u8 __iomem *)&par->regs->cmap.addr; 336 sbus_writeb(p[0], regp); 337 regp = (u8 __iomem *)&par->regs->cmap.control; 338 sbus_writeb(p[1], regp); 339 } 340 return 0; 341 } 342 343 static int cg3_probe(struct platform_device *op) 344 { 345 struct device_node *dp = op->dev.of_node; 346 struct fb_info *info; 347 struct cg3_par *par; 348 int linebytes, err; 349 350 info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev); 351 352 err = -ENOMEM; 353 if (!info) 354 goto out_err; 355 par = info->par; 356 357 spin_lock_init(&par->lock); 358 359 info->fix.smem_start = op->resource[0].start; 360 par->which_io = op->resource[0].flags & IORESOURCE_BITS; 361 362 sbusfb_fill_var(&info->var, dp, 8); 363 info->var.red.length = 8; 364 info->var.green.length = 8; 365 info->var.blue.length = 8; 366 if (of_node_name_eq(dp, "cgRDI")) 367 par->flags |= CG3_FLAG_RDI; 368 if (par->flags & CG3_FLAG_RDI) 369 cg3_rdi_maybe_fixup_var(&info->var, dp); 370 371 linebytes = of_getintprop_default(dp, "linebytes", 372 info->var.xres); 373 info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres); 374 375 par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET, 376 sizeof(struct cg3_regs), "cg3 regs"); 377 if (!par->regs) 378 goto out_release_fb; 379 380 info->fbops = &cg3_ops; 381 info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET, 382 info->fix.smem_len, "cg3 ram"); 383 if (!info->screen_base) 384 goto out_unmap_regs; 385 386 cg3_blank(FB_BLANK_UNBLANK, info); 387 388 if (!of_property_present(dp, "width")) { 389 err = cg3_do_default_mode(par); 390 if (err) 391 goto out_unmap_screen; 392 } 393 394 err = fb_alloc_cmap(&info->cmap, 256, 0); 395 if (err) 396 goto out_unmap_screen; 397 398 fb_set_cmap(&info->cmap, info); 399 400 cg3_init_fix(info, linebytes, dp); 401 402 err = register_framebuffer(info); 403 if (err < 0) 404 goto out_dealloc_cmap; 405 406 dev_set_drvdata(&op->dev, info); 407 408 printk(KERN_INFO "%pOF: cg3 at %lx:%lx\n", 409 dp, par->which_io, info->fix.smem_start); 410 411 return 0; 412 413 out_dealloc_cmap: 414 fb_dealloc_cmap(&info->cmap); 415 416 out_unmap_screen: 417 of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len); 418 419 out_unmap_regs: 420 of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs)); 421 422 out_release_fb: 423 framebuffer_release(info); 424 425 out_err: 426 return err; 427 } 428 429 static void cg3_remove(struct platform_device *op) 430 { 431 struct fb_info *info = dev_get_drvdata(&op->dev); 432 struct cg3_par *par = info->par; 433 434 unregister_framebuffer(info); 435 fb_dealloc_cmap(&info->cmap); 436 437 of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs)); 438 of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len); 439 440 framebuffer_release(info); 441 } 442 443 static const struct of_device_id cg3_match[] = { 444 { 445 .name = "cgthree", 446 }, 447 { 448 .name = "cgRDI", 449 }, 450 {}, 451 }; 452 MODULE_DEVICE_TABLE(of, cg3_match); 453 454 static struct platform_driver cg3_driver = { 455 .driver = { 456 .name = "cg3", 457 .of_match_table = cg3_match, 458 }, 459 .probe = cg3_probe, 460 .remove_new = cg3_remove, 461 }; 462 463 static int __init cg3_init(void) 464 { 465 if (fb_get_options("cg3fb", NULL)) 466 return -ENODEV; 467 468 return platform_driver_register(&cg3_driver); 469 } 470 471 static void __exit cg3_exit(void) 472 { 473 platform_driver_unregister(&cg3_driver); 474 } 475 476 module_init(cg3_init); 477 module_exit(cg3_exit); 478 479 MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets"); 480 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>"); 481 MODULE_VERSION("2.0"); 482 MODULE_LICENSE("GPL"); 483